JPS6016772B2 - Signal transmission method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transmission system for encoding and transmitting analog signals.

FIG. 1 shows an audio file device to which this type of transmission method is applied.

1 to 4 are input/output devices for the computer 5, such as a clock, a CRT display, a keyboard, and a printer, respectively.

6 is a magnetic disk device in which audio signals are digitized and recorded.

Reference numeral 7 denotes an audio signal processing circuit that includes an encoder that digitizes an analog audio signal inputted from a terminal 71 and a decoder that converts the digital signal back into an analog signal and outputs it to a terminal 72.

Since the encoding/decoding speed of the audio signal and the transfer speed of the disk device 6 are different, reference numerals 8 and 9 are buffer memories for mutual speed conversion when writing to and reading from the disk. It operates in a so-called chaining system in which writing and reading are performed alternately.

Reference numerals 10 and 11 are signal switching circuits for switching the signal path during the chaining.

A circuit 12 receives instructions from the computer 5 and controls the buffer memories 8 and 9 and the magnetic disk device 6.

In this device, an analog signal input to a terminal 71 is converted into a digital signal by a processing circuit 7 and stored in buffer memories 8 and 9 via a signal switching circuit 10.

In this state, an address, etc. is specified on the computer 5 by a command inputted from the keyboard 3, etc., and the control circuit 12
The digital signals read from the buffer memories 8 and 9 are recorded in the magnetic disk device 6 under the control of the buffer memories 8 and 9. Conversely, the recorded information specified on the keyboard 3 etc. is stored in the control circuit 1.
2, the signal is applied to the processing circuit 7 via the signal switching circuit 11, the buffer memories 8 and 9, and the signal switching circuit 10, and is converted into an analog signal and sent out from the terminal 72. In the above-described apparatus, it is necessary to increase the compression ratio of the signal in order to substantially increase the recording capacity, but there is no need to give much consideration to the continuity required for normal audio signal transmission.

That is, the audio signals at the terminals 71 and 72 need to be continuous, but the audio signal processing circuit 7 including the encoder-decoder
There is no problem even if the transmission of audio signals is discontinuous between the buffer memories 8 and 9 and the buffer memories 8 and 9. When used in such applications, the encoder according to the invention incorporates the idea of variable length coding. That is, when encoding and transmitting an analog signal, the present invention divides the signal to be transmitted into fixed periods, detects the number of bits required to transmit the maximum value in that period, and calculates the maximum value for each block. The compression ratio is increased by transmitting data using the number of bits required for transmission. Next, one embodiment will be described according to the drawings.

FIG. 2a shows an encoder, and b shows a decoder suitable for this.

13 is an analog audio signal input terminal, 14 is an A/D converter, 15 is a detection circuit for the required number of bits required to transmit the maximum sample value of the input signal for a certain period, and 16 is an A/D converter for this certain period only. 17 is a buffer register control circuit, 18 is a buffer register, 19 is a multiplex circuit, and 20 is an output terminal.

The analog signal coming in from terminal 13 is sent to A/○ converter 1.
4 into a digital signal.

The required number of bits detection circuit 15 monitors the output code of the A/D converter 14 for a time T, and detects the required number of bits required to represent the maximum level during that time. The delay circuit 16 delays the output of the A/D converter 14 for T. Buffer register 18 writes and reads the output of delay circuit 16 in accordance with the output of buffer register control circuit 17. The buffer register control circuit 17 controls the timing and number of clocks used when writing and outputting the output of the delay circuit 16 to the buffer register 8 according to the output of the required number of bits detection circuit 15. The output is a signal with a reduced number of bits.
The multiplex circuit 19 receives the output data of the buffer register 18,
This is a circuit that multiplexes bit information indicating how many bits each T block sample is being transmitted. Figures 3 and 4
The figure illustrates the above relationship.

FIG. 3a shows the output code of the A/D converter 14, and each A/B at time T. represents a block. b is the output of the delay circuit 16, and is delayed by one block with respect to a. Detection of the required number of bits is performed for each Ai of the signal a, and the result is applied to each peak of b. FIG. 4 illustrates a method for reducing the number of bits.

p,. ,...po,q,. etc. are binary numbers representing each sample value of the output of the A/D converter 14. The binary numbers here are so-called folded binary numbers. That is, p, . ,q,．・
...,t,. ,..., etc. are sign bits that mean whether the sign of the sample value is positive or negative, and p・o,
... po, q, o, ... qo; ... etc. represent the absolute value of each sample value. a is A/ in a certain block
○Represents the output of the converter 14. In this block, if ~0001, r4, and 3r2r, are the sample values with the maximum absolute value, then all the sample values in this block have the sign bit 1 and the absolute value of each sample value, as in b. In fact, the buffer memories 8, 9, etc. following the terminal 20 are often processed in parallel with 8 bits, so in this case, they are transmitted in 8 bits arranged as shown in c. In this case, R7...Ro is a code indicating the number of bits that the sample in this block should be transmitted.The * mark indicates that when arranged in 8 bits like this, the total number of bits included in the block is 8. This is the remainder that occurs when it is not divisible by , and it can be of any sign.a~
The change in c is performed in the buffer register 18 according to the buffer register control circuit 17, and the codes R7 . . . Ro representing bit number information are multiplexed in the multiplexing circuit 19. Eventually, a sign c appears at the terminal 20. Next, Figure 2b
The following describes the decoder.

22 is a separation circuit that separates data from the bit number information R7 . . . Ro from the code as shown in FIG. 4c.

The separated bit number information is sent to the buffer register control circuit 2.
3 and controls the buffer register 24. As a result, the output of the buffer register 24 obtains the original code as shown in FIG. 4a, and the D/A converter 25 analyzes this. return to the green signal. FIG. 6 shows one embodiment of the buffer register 18. 181 is a parallel/serial conversion register, and 182 is a serial/parallel conversion register.

The 12-bit parallel code output of delay circuit 16 is loaded into 12-bit register 181 in parallel. shift register 1
The parallel code input to 81 is converted into serial data and then transferred to shift register 182 until new 12-bit parallel data is loaded into shift register 181 . The shift register 182 is an 8-bit register, and each time the transfer of 8-bit data is completed, the buffer
The data is transferred to memories 9 and 10 as 8-bit parallel data. At this time, the register 81 outputs 12 bits as a serial signal every time 12 bits of parallel data is loaded, but the register 182 outputs 12 bits as a serial signal every time 12 bits of parallel data is loaded. Capture only the necessary bits.

For example, in the above example, P.loo0001p4p3p2
When the codes p and po are loaded into the register 181,
Register 182 begins with the first p, . is taken in, but the next three zeros are not taken in.

Subsequently, data is fetched from the fourth zero, and when p is fetched, the register 182 becomes full and is transferred to the buffer memory 9 or 10 as 8-bit parallel data. Next, po, q, etc. are taken into the register 182, the next three zeros are ignored, and the fourth zero to q2 are taken in, the register 182 becomes full and is sent to the buffer memory 9 or 10 as 8-bit parallel data. be transferred. Similarly, if the bit number information is multiplexed on the data transferred to the buffer memory every 8 bits, a code as shown in FIG. 4c is obtained. The register 182 takes in or ignores bits by controlling the clock applied to the register 182. FIG. 6 shows an embodiment of the buffer register 24 in FIG. 2b. 241 is an 8-bit parallel/serial shift register, 242 is a 12-bit serial/parallel shift register, and 243 is a 12-bit latch.

The register 241 is loaded with 8-bit parallel data from the buffer memory 9 or 10 each time the data transfer to the register 242 is completed. The serial data from the register 241 is written into the register 242, and when it becomes full, it is latched into the latch 243 as 12-bit data, which becomes the output code to the D/A converter 25. For example, in the above example, p
、． 001p4p3p2p, is loaded into register 241, register 242 first loads the first p, . is taken in, and register 241 is not shifted for the next three clocks, and zero is written to register 242.

The contents of register 241 are then shifted again and register 242 takes in the following bits 001p4p3p2p, and register 242 receives the new 8 bits poq, . 0001
q3q2 is loaded. Then po is register 24
2, the latch 243 shifts the contents of the register 242 p, . ,...p. is latched and output to the D/A 25 as 12-bit data. Following po, q, . is register 2
42, it is sent to the register 241 again for 3 bits.
takes a break from shifting, during which time zero is written to register 242. Similarly, the 8-bit code outputted from the buffer memories 9 and 10 in the form shown in FIG. 4c is returned to the original 12-bit code shown in FIG. 4a. FIG. 7 shows a case where the above concept is applied to a predictive encoder. Terminals or blocks indicated by the same numbers as above are terminals through which the signals of the same machine go in and out, and blocks that function as the same machine. a is an encoder and b is a decoder. The subtracter 27, adder 28, and predictor 29 are well-known predictive encoders. In other words, this output contains the difference between the actual sample value and the predicted value from the past sample value. The output of this predictor is passed through the previously explained circuit consisting of 16 to 19 instead of the output of the A/D converter explained in FIG. Since audio signals and the like have a high correlation between sample values, a greater reduction in the number of bits can be achieved. In b, the adder 28 and the predictor 29 are decoders for the predictive encoder in a, and the numbers indicated by the same numbers are the same blocks. As can be seen from the foregoing description, by 22-24, the adder 28
Since the same signals a and b are obtained at the inputs of , the D/A converter 25 outputs the original signal to the terminal 26. can be obtained.
As described above, according to the present invention, only the necessary number of bits (albeit in blocks) of a signal to be recorded need be sent, so the amount of information that must be stored by a storage means such as a magnetic disk is much smaller. The effect is remarkable.

Note that the data does not appear at the output terminal with a fixed cycle clock, so there is a problem if you use it as is for normal communication, but if you use it for an audio file device as shown in Figure 1, for example, the final As long as a continuous signal can be obtained, this is not a problem at all.

[Brief explanation of drawings]

Figure 1 is a block diagram of the audio file device, Figure 2 a, b
is a block diagram of an encoder and a decoder using the method of the present invention,
Figures 3 and 4 are schematic diagrams explaining the principle of the present invention, and Figure 5.
6 are block diagrams showing detailed configurations of the same essential parts, and FIGS. 7a and 7b are block diagrams of other embodiments. 14...A/○ converter, 15...Bit number detection circuit, 16...Delay circuit, 17...
- Buffer register control circuit, 18...Buffer register, 19...Multiple circuit. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 (QJ 'mu)

Claims (1)

[Claims] 1. In a method of encoding and transmitting analog signals, the signal to be transmitted is divided at regular time intervals, and the number of bits required to transmit the maximum sample value included in each block for each block. transmitting all the sample values in the block containing the sample value, and transmitting for each block a code indicating the bit position where the most significant digit of the digital quantity indicating the maximum sample value appears. A signal transmission method characterized by 2. The signal transmission method according to claim 1, wherein the signal to be transmitted is a prediction error. 3. Receive a signal divided at fixed time intervals and transmitted with the number of bits corresponding to the maximum sample value for each block, and extract the signal from the code indicating the bit position of the most significant digit included in the block. A signal transmission method characterized in that the number of bits of a code included in the code is identified, and the transmission signal is decoded in units of the blocks using the number of bits.