JPS60165748A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPS60165748A
JPS60165748A JP2098584A JP2098584A JPS60165748A JP S60165748 A JPS60165748 A JP S60165748A JP 2098584 A JP2098584 A JP 2098584A JP 2098584 A JP2098584 A JP 2098584A JP S60165748 A JPS60165748 A JP S60165748A
Authority
JP
Japan
Prior art keywords
leads
extension
frame
lead
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2098584A
Other languages
Japanese (ja)
Inventor
Masami Shimada
島田　政見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2098584A priority Critical patent/JPS60165748A/en
Publication of JPS60165748A publication Critical patent/JPS60165748A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To facilitate the handling at a test time by coupling an extension having a wider interval than a plurality of outer leads with the ends of the outer leads projected from a resin sealer including a plurality of inner leads, performing an aging test using it, and cutting off the extension of the approved frame. CONSTITUTION:A resin sealer 11 sealed to include a plurality of inner leads is secured to a frame 122 by using leads 121 opposed via the sealer 11. When a plurality of outer leads 123 projected in four directions are provided at the sealer 11, extension leads 124, 125 coupled with a resin auxiliary frame 30 are connected with the ends of the leads 123. At this time, the interval W1 of the leads 124, 125 is formed wider than the interval W2 of the leads 123, an aging test is performed using them, thereby avoiding the contact of the leads 123 at the testing time.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、樹脂封止型半導体装置のリードフレームに関
するもので、特にフラットノ母ッケージ（ＦＬＰ　）型
のＩＣ用に好適なリードフレームに関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a lead frame for a resin-sealed semiconductor device, and particularly to a lead frame suitable for a flat motherboard package (FLP) type IC.

〔発明の技術的背景〕[Technical background of the invention]

現在、ｒｃとＩ〜でＦＬＰ型のものが広く使用されてい
る。第１図はＦＬＰ型のＩＣの製造過程中における状態
を示す平面図で、第２図ｔ」、第１図のＡ−Ａ’線に沿
った断面図である。これらの図において、１１は内部に
半導体素子１ｏの収納された樹脂封止部であり、半導体
素子１０は樹脂封止部内においてリードフレーム１２の
インナーリード１２０，１２ｏ・・・の先端に図示しな
いがンディングワイヤを介して電気的接続されている。Currently, FLP types are widely used for rc and I~. FIG. 1 is a plan view showing the state of an FLP type IC during the manufacturing process, FIG. 2 is a sectional view taken along line AA' in FIG. In these figures, reference numeral 11 denotes a resin sealing part in which a semiconductor element 1o is housed, and the semiconductor element 10 is located at the tips of inner leads 120, 12o... of a lead frame 12 within the resin sealing part (not shown). electrically connected via a landing wire.

この樹脂封止部１ノはりフリート１２．に支持されリー
ドフレーム１２のフレームｍ　Ｊ　２２　ニ固定されて
でおり、樹脂封止部１１の側面からはアクタ−リード１
２３　、１２３−゛が引き出されている。This resin-sealed portion 1 has a beam fleet 12. The frame mJ22 of the lead frame 12 is supported by and fixed to the frame mJ22 of the lead frame 12, and the actor lead 1 is visible from the side of the resin sealing part 11.
23, 123-'' are drawn out.

ところで、一般に半導体装置では出荷前にエージングテ
スト（Ａｇｉｎｇ　Ｔｓａｔ　）が行なわれ、製品とし
ての合否が判定されるが、上記のようなＦＬＰ型の装置
に対しては次のようにしてテストが行なわれている。Incidentally, semiconductor devices are generally subjected to an aging test (Aging Tsat) before shipping to determine whether the product is acceptable or not, but the FLP type device described above is tested in the following manner. ing.

すなわち第２図の断面図に示すように底部にいわゆるボ
コンピン２０の配列されたＦＬＰ用ＩＣソケットに樹脂
封止部１１をリードフレームＵごと載せ、図示矢印方向
から絶縁性の善をかぶせアウターリード１２３をポコン
ビン２０の接点に接触せしめて外部の検査装置とのテス
ト信号の授受を行なう。That is, as shown in the cross-sectional view of FIG. 2, the resin sealing part 11 is placed together with the lead frame U on an FLP IC socket on which so-called bocon pins 20 are arranged at the bottom, and the outer leads 123 are covered with an insulating material from the direction of the arrow shown in the figure. is brought into contact with the contact point of the pocombin bin 20 to exchange test signals with an external inspection device.

〔背景技術の問題点〕[Problems with background technology]

しかしながら上記のようなエージングテスト方法ではＦ
ＬＰ用ＩＣソケットの構造が複雑なため、アウターリー
ド１２３が曲がってし１うことが度々生じていた。However, with the above aging test method, F
Because the structure of the LP IC socket is complicated, the outer lead 123 often bends.

しかも被検査半導体装置とＦＴ、Ｐ用ＩＣソケットとの
着脱に時間がかかり、着脱の自動化も容易に行なえず、
人間の手による作業を行なう必要があるため、極めて作
業性の悪いものであった。Moreover, it takes time to attach and detach the semiconductor device under test to the FT and P IC sockets, and it is not easy to automate the attachment and detachment.
Since the work had to be done manually, it was extremely difficult to work with.

また、従来のピンコンタクト方式によるソケットでは、
アウターリード１２３との接点がアウターリード１２３
の裏面にのみ１点しか取れない。このため、例えばアウ
タ−リード１２３裏面に樹脂パリ等があると半導体素子
との電気的接続が得られず、正確な検査が行なえない。In addition, with conventional pin contact type sockets,
The contact point with the outer lead 123 is the outer lead 123
You can only score one point on the back of the . For this reason, for example, if there are resin particles on the back surface of the outer lead 123, electrical connection with the semiconductor element cannot be obtained, and accurate inspection cannot be performed.

加えて、半導体装置のリード数及び形状が異なるとＩＣ
ソケットも替える必要があり、コストも高くつく。In addition, if the number and shape of leads of semiconductor devices differ, IC
The socket also needs to be replaced, which is expensive.

〔発明の目的〕[Purpose of the invention]

本発明は−１−記のような点に鑑みてなされたもので、
半導体装置の正確で作業性の良い検査を可能とするリー
ドフレームを提供することを目的とする。The present invention has been made in view of the points mentioned in -1-,
An object of the present invention is to provide a lead frame that enables accurate and workable inspection of semiconductor devices.

〔発明の概要〕[Summary of the invention]

すなわち本発明によるリードフレームは、樹脂封止部内
においで半導体素子と電気的接続される複数のインナー
リードと、このインナーリードの先に延長して設けられ
た複数のアウターリードと、このアウターリードよりさ
らに延長して設けられ上記アウターリード間の間隔よシ
も互いの間隔が広い複数の延長リードと、この複数の延
長リードに連架するように設けられた樹脂製の補助フレ
ームとを備えたもので、半導体装置の出荷前の電気的検
査を」二記延長リードを介して行なうように１７だもの
である。In other words, the lead frame according to the present invention includes a plurality of inner leads that are electrically connected to a semiconductor element within a resin sealing part, a plurality of outer leads extending beyond the inner leads, and a plurality of outer leads extending from the outer leads. A device comprising a plurality of extension leads which are further extended and have a wider interval than the distance between the outer leads, and a resin auxiliary frame which is provided so as to be connected to the plurality of extension leads. 17 so that the electrical inspection of the semiconductor device before shipment is carried out via the extension lead 2.

〔発明の実施例〕[Embodiments of the invention]

以下図面を参照して本発明の一実施例につき説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第３図において、樹脂封止部１ノはりフリート１２．に
よってリードフレーム１２のフレーム部１２２に固定さ
れ、その内部において従来と同様に半導体素子が複数の
インナーリードに電気的接続されている。なお、樹脂封
止部１ノの内部は従来と同様であるので説明は省略する
。In FIG. 3, the beam fleet 12 of the resin sealing portion 1 is shown. is fixed to the frame portion 122 of the lead frame 12, and inside the semiconductor element is electrically connected to a plurality of inner leads as in the conventional case. Note that the interior of the resin sealing portion 1 is the same as the conventional one, so a description thereof will be omitted.

そして、上記樹脂封止部１ノの側面からは」二記複数の
インナーリードのそれぞれに対応して所定のリード長の
アウターリード１２３，１２３・・・が引き出きれてい
る。そして、このアウターリード１２３．１２３　・・
・のさらに先にはアウターリード”　ａ　ｒ　１２３　
・・・の延長した延長リード１２４．１２４・・・が設
けられている。これらの延長リード１２４．１２４・・
・の隣接するリード間の間隔Ｗ１は、インナーリード１
２３．１２３・・５− の隣接するリード間の間隔Ｗ２よシも広い。そ１〜でこ
れらの延長リード１２４．１２４・・・には樹脂製の補
助フレーム３０が連架するように設けられ互いに固定さ
れている。さらにこの補助フレーム３０は補助リフリー
ド１２ｔｘｌ　２５・・・によりフレーム部１２２に固
定されている。Outer leads 123, 123, . . . each having a predetermined lead length are pulled out from the side surface of the resin sealing portion 1, corresponding to each of the plurality of inner leads. And this outer lead 123.123...
・Further ahead is the outer lead” a r 123
Extension leads 124, 124, and so on are provided. These extension leads 124.124...
The distance W1 between adjacent leads is inner lead 1.
The interval W2 between adjacent leads of 23.123...5- is also wider. The extension leads 124, 124, . . . are provided with an auxiliary frame 30 made of resin so as to be connected and fixed to each other. Furthermore, this auxiliary frame 30 is fixed to the frame portion 122 by auxiliary releads 12txl 25, . . . .

以上のようなリードフレームを有する半導体装置ではエ
ーシングテスト時に、第４図に示すように補助フレーム
３０から先の延長リード１２４．１２４　を曲げ、延長
リード１２４．１２４をコンタクタ−４０で挟み、半導
体素子と外部の試験装置との間でテスト信号の授受を行
う。In a semiconductor device having a lead frame as described above, during an aging test, the extension leads 124 and 124 from the auxiliary frame 30 are bent as shown in FIG. Test signals are exchanged between the element and external test equipment.

そして、所定のエージングテストが終了した後、合格し
た半導体装置の延長リード１２４　。After the predetermined aging test is completed, the extension lead 124 of the semiconductor device that has passed the test.

１２４を図の破線ａの部分で切り落とし、通常の形状の
？′ＬＰ型ｒｃの製品とする。124 is cut off at the broken line a in the figure, and the normal shape of ? 'LP type rc product.

第３図に示すような延長リード１２４，１２４・・・を
有するリードフレーム旦には次のような長所がある。A lead frame having extension leads 124, 124, etc. as shown in FIG. 3 has the following advantages.

まず、アウターリード１２３．１２３・・・の変６− 形の恐れなく、エージングテスト等の各種の取り扱いが
可能である。First, various types of handling such as aging tests can be performed without fear of the outer leads 123, 123, etc. becoming deformed.

加えて、延長リード１２４，１２４・・・間の間隔Ｗ、
の方がアウターリード”　３　＋　１２３　・・・間の
間隔Ｗ２よりも広いため、エージングテスト時における
リードの接触事故をも防止できる。In addition, the distance W between the extension leads 124, 124...
is wider than the interval W2 between the outer leads ``3 + 123'', so it is possible to prevent lead contact accidents during aging tests.

また、相対向する延長リード１２４，１２４・・・の幅
Ｗ３　（第３図参照）を樹脂封止部１ノの形状および大
きさに拘ず一定に規格化すれば、半導体装置の種類が異
なっても同一の試験用ＩＣソケットを共用できるため、
検査ラインの合理化を図ることができる。Furthermore, if the width W3 (see Fig. 3) of the opposing extension leads 124, 124, etc. is standardized to be constant regardless of the shape and size of the resin sealing part 1, the types of semiconductor devices can be different. Because the same test IC socket can be shared even if
The inspection line can be rationalized.

さらに、延長リード”　４　１１２４　・・・を折り曲
げることができるため、従来のような着脱が煩雑でリー
ドとの接触点が１点１〜かないＦＬＰ用ＩＣソケットを
用いなくともよく、例えばアウターリード”　４　＋　
１２４・・・を挟むような面接触するコンタクタ−を用
いてエージングテストを行うことが可能である。これに
より、アウターリード１２４，１２４・・・と外部の検
査装置との接続性の信頼性を向上できる。さらにこの外
部装置との接続を、ＤＩＰ型Ｉ型用Ｃ用ソケットて使用
されている上方から多数のリードを差し込む形式のソケ
ットにより行なえば、従来のものに比較して極めて簡便
にかつ信頼性良くエージングテストを行なえ、検査ライ
ンの自動化も可能となる。Furthermore, since the extension lead "4 1124 ..." can be bent, there is no need to use the conventional FLP IC socket, which is complicated to attach and detach and has only one contact point with the lead, for example, the outer lead " 4 +
It is possible to perform an aging test using contactors that make surface contact such as sandwiching 124.... Thereby, the reliability of connectivity between the outer leads 124, 124, . . . and an external inspection device can be improved. Furthermore, if the connection with this external device is made using a socket in which multiple leads are inserted from above, which is used as a DIP type I type C socket, it is extremely simple and reliable compared to conventional ones. Aging tests can be performed and inspection lines can be automated.

甘た、補助フレーム３０は半導体素子のモールド工程に
おいて樹脂封止部１ノと同時に形成すれはよいため、製
造工程の煩雑化を招くこともない。Furthermore, since the auxiliary frame 30 can be formed at the same time as the resin sealing part 1 in the semiconductor element molding process, the manufacturing process does not become complicated.

なお、補助フレーム３０の形状は第３図および第４図に
示すようなものばかりでなく、例えば、補助フレーム３
０が補助リフリード１２５゜１２５・・・により支えら
れるのではなくリードフレームｊ２のフレーム部１２２
に直接固定するようになっていてもよいし、フレーム部
１２２との固定状態が不安定とならない範囲で補助フレ
ーム３００１部に切れ目が入っていているようなもので
もかまわない。Note that the shape of the auxiliary frame 30 is not limited to that shown in FIGS. 3 and 4;
0 is not supported by the auxiliary relead 125°125... but by the frame portion 122 of the lead frame j2.
The auxiliary frame 3001 may be directly fixed to the auxiliary frame 3001, or the auxiliary frame 3001 may have a cut in the auxiliary frame 3001 as long as the state of fixation to the frame portion 122 is not unstable.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明によれば、半導体装置の正確で作業
性の良い検査を可能とするリードフレームを提供するこ
とができる。As described above, according to the present invention, it is possible to provide a lead frame that enables accurate and easy-to-work inspection of semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図および第２図はそれぞれ従来のリードフレームを
説明する平面図および断面図、第３図および第４図はそ
れぞれ本発明の一実施例に係るリードフレームを説明す
る平面図および断面図である。 １１・・・樹脂封止部、１２・・・リードフレーム、１
２ｏ、１２ｏ−・・・・・インナーリード、１２１１１
２、・・・リフリード、１２３　．１２３　・・・・・
・アウターリード、　１２４＋１２４　・・・・・・延
長リード、１２５．１２．・・・・・・補助リフリード
、３ｏ・・・補助フレーム。 出願人代理人　弁理士　鈴　江　武　彦９− 第　１− 坦 Ｍ２ワ1 and 2 are a plan view and a sectional view, respectively, illustrating a conventional lead frame, and FIGS. 3 and 4 are a plan view and a sectional view, respectively, illustrating a lead frame according to an embodiment of the present invention. be. 11...Resin sealing part, 12...Lead frame, 1
2o, 12o-・・・Inner lead, 12111
2,...refried, 123. 123...
・Outer lead, 124+124 ...Extension lead, 125.12. ...Auxiliary re-read, 3o...Auxiliary frame. Applicant's agent Patent attorney Takehiko Suzue 9- No. 1- Tan M2 Wa

Claims (1)

【特許請求の範囲】[Claims] 樹脂封止形半導体装置の樹脂封止部内Ｖこ収納される複
数のインナーリードと、樹脂封止部の外へ上記インナー
リードから引き出される複数のアウターリードと、これ
らのアウターリードよりさらに延在して設けられ隣接す
るアウターリードの間隔よりも互いの間隔が広くなるよ
うに配列された複数の延長リードと、これらの延長リー
ドに連架するように設けられた樹脂製の補助フレームと
を具備することを特徴とするリードフレーム。A plurality of inner leads housed in a resin sealing part of a resin sealing type semiconductor device, a plurality of outer leads drawn out from the inner leads outside the resin sealing part, and a plurality of outer leads extending further from these outer leads. A plurality of extension leads are arranged such that the distance between them is wider than the space between adjacent outer leads, and an auxiliary frame made of resin is provided so as to be connected to these extension leads. A lead frame characterized by:
JP2098584A 1984-02-08 1984-02-08 Lead frame Pending JPS60165748A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2098584A JPS60165748A (en) 1984-02-08 1984-02-08 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2098584A JPS60165748A (en) 1984-02-08 1984-02-08 Lead frame

Publications (1)

Publication Number Publication Date
JPS60165748A true JPS60165748A (en) 1985-08-28

Family

ID=12042439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2098584A Pending JPS60165748A (en) 1984-02-08 1984-02-08 Lead frame

Country Status (1)

Country Link
JP (1) JPS60165748A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1988008203A1 (en) * 1987-04-17 1988-10-20 Xoc Devices, Inc. Packaging system for stacking integrated circuits
US4843695A (en) * 1987-07-16 1989-07-04 Digital Equipment Corporation Method of assembling tab bonded semiconductor chip package
EP0331814A2 (en) * 1987-12-28 1989-09-13 Siemens Aktiengesellschaft Lead frame for semiconductor device
US4899207A (en) * 1986-08-27 1990-02-06 Digital Equipment Corporation Outer lead tape automated bonding
US4953005A (en) * 1987-04-17 1990-08-28 Xoc Devices, Inc. Packaging system for stacking integrated circuits
US4979663A (en) * 1986-08-27 1990-12-25 Digital Equipment Corporation Outer lead tape automated bonding system
JPH0669410A (en) * 1992-08-17 1994-03-11 Nec Yamagata Ltd Manufacture of semiconductor device
JPH07169902A (en) * 1993-12-16 1995-07-04 Nec Corp Semiconductor device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4899207A (en) * 1986-08-27 1990-02-06 Digital Equipment Corporation Outer lead tape automated bonding
US4979663A (en) * 1986-08-27 1990-12-25 Digital Equipment Corporation Outer lead tape automated bonding system
WO1988008203A1 (en) * 1987-04-17 1988-10-20 Xoc Devices, Inc. Packaging system for stacking integrated circuits
US4862249A (en) * 1987-04-17 1989-08-29 Xoc Devices, Inc. Packaging system for stacking integrated circuits
US4953005A (en) * 1987-04-17 1990-08-28 Xoc Devices, Inc. Packaging system for stacking integrated circuits
US4843695A (en) * 1987-07-16 1989-07-04 Digital Equipment Corporation Method of assembling tab bonded semiconductor chip package
EP0331814A2 (en) * 1987-12-28 1989-09-13 Siemens Aktiengesellschaft Lead frame for semiconductor device
JPH0669410A (en) * 1992-08-17 1994-03-11 Nec Yamagata Ltd Manufacture of semiconductor device
JPH07169902A (en) * 1993-12-16 1995-07-04 Nec Corp Semiconductor device

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