JPS60160170A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPS60160170A JPS60160170A JP1542684A JP1542684A JPS60160170A JP S60160170 A JPS60160170 A JP S60160170A JP 1542684 A JP1542684 A JP 1542684A JP 1542684 A JP1542684 A JP 1542684A JP S60160170 A JPS60160170 A JP S60160170A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- thin film
- film transistor
- layer
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 16
- 239000010408 film Substances 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 230000005669 field effect Effects 0.000 claims description 3
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000003475 lamination Methods 0.000 abstract 1
- 239000011521 glass Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 239000011159 matrix material Substances 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000005533 two-dimensional electron gas Effects 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000002689 soil Substances 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Liquid Crystal (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、オン電流が大きくとn、動作速度の速い薄膜
トランジスタの実現に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to realizing a thin film transistor with a large on-current and a high operating speed.
近年、ガラスなどの絶縁性基板上に形成できる薄膜トラ
ンジスタの開発が各所で盛んである。絶縁性基板上に、
薄膜トランジスタからなるスイッチ素子をプレイ状に設
けたアクティブマトリクヌ型の液晶、エレクトロクロミ
ック、エレクトロルミネッセンスなどの表示装置は、画
素間のクロ7トークが無く、高速動作が可能なので77
画像などの表示を可能にする。薄膜トランジスタに用い
る半導体膜としては、プラズマOVD法などによって、
ガラスなどの基板上に低温で大面積かつ安価に形成でき
る水素化非晶質シリコン膜やフッ素化非晶質シリコン膜
などが有望とさnている。In recent years, development of thin film transistors that can be formed on insulating substrates such as glass has been active in various places. on an insulating substrate,
Display devices such as active matrix liquid crystal, electrochromic, and electroluminescent display devices in which switch elements made of thin film transistors are arranged in a play pattern are capable of high-speed operation without any black talk between pixels.77
Enables display of images, etc. Semiconductor films used in thin film transistors are made by plasma OVD method, etc.
Hydrogenated amorphous silicon films and fluorinated amorphous silicon films, which can be formed at low temperatures, over large areas, and at low cost, on substrates such as glass are promising.
しかし、一方とnら非晶質シ’)17Mで形成した薄膜
トランジスタで得らnる電界効果移動度は〜0.11a
l/V、sなo−c、xOV程Ktv動作’R圧で10
″″Iム以上の電流を得られるトランジスタの実現は困
難である。この為、動作周波数が数10KH2以上の回
路を非晶質シリコンのトランジスタで実現するのは困難
とさnていた。非晶質シリコン薄膜トランジスタは、ア
クティブマトリクヌ盤表示装置の画素毎のスイッチトラ
ンジスタとしては充分な動作速度を有するものの、数M
Hz以上の動作周波数を要求される、TV画像表示用の
周辺回路の適用には不充分な動作速度である。従来の方
法では、この種の周辺回路拡単結晶シリコン上に形成し
たMO日l0を用い、表示装置との間を数百ケ所の端子
で接続して了りテイプマトリクヌ型表示装置を駆動して
い喪。それ故、従来の了りテイプマトリクヌ型表示装置
は
(1)回路接続の費用が安価にできないC)周辺回路の
部分をコ/ノ(クトにできない(3)実装後の信頼性が
劣る
などの欠点を持っていた。However, the field effect mobility obtained with a thin film transistor formed of 17M amorphous material is ~0.11a.
l/V, s o-c, xOV, Ktv operation 'R pressure 10
It is difficult to realize a transistor that can obtain a current greater than ``Im''. For this reason, it has been difficult to realize a circuit with an operating frequency of several tens of KH2 or higher using amorphous silicon transistors. Although amorphous silicon thin film transistors have sufficient operating speed as switch transistors for each pixel in active matrix display devices,
This operating speed is insufficient for application to peripheral circuits for TV image display, which require an operating frequency of Hz or higher. In the conventional method, this type of peripheral circuit is formed on expanded monocrystalline silicon, and is connected to the display device through several hundred terminals, thereby driving a tape matrix display device. . Therefore, conventional tape matrix type display devices have disadvantages such as (1) the cost of circuit connection cannot be made low, C) peripheral circuits cannot be isolated, and (3) reliability after mounting is poor. I had.
非晶質シリコン薄膜トランジスタは、ガラス基板上に形
成した、光などのセンサーとしても応用It期待されて
いるが、この場合にも周辺回路との接続の問題は表示装
置の事情と同様である。Amorphous silicon thin film transistors are also expected to be used as sensors for light and the like formed on glass substrates, but in this case as well, the problem of connection with peripheral circuits is similar to that of display devices.
本発明の目的は、動作速度の速い薄膜トランジスタを実
現することにより、上記のごとき従来の欠点を無くして
、同一絶縁性基板上に、表示装置あるいは、センサーと
七わらの周辺回路を同時に設ける手段を提供することで
ある。An object of the present invention is to eliminate the above-mentioned conventional drawbacks by realizing a thin film transistor with high operating speed, and to provide a means for simultaneously providing a display device or a sensor and peripheral circuits on the same insulating substrate. It is to provide.
以下実施例に基づいて、図面により本発明を説明する。The present invention will be described below with reference to the drawings based on examples.
第1図(ロ))は、本発明の電界効果型の薄膜トランジ
スタのチャンネル領域の断面での、フラットバンド状態
のバンド構造を示す図でおる。第1図(α)で、1はゲ
ート電極金属、2はゲート絶縁膜、3は禁制帯巾”Is
厚さ150A以下のn型にドープさnた第一の半導体層
、4は3と同じ禁制帯巾EIで、厚さtoooZ以上の
、不純物のドープ量が3よ)も少い第二の半導体層でお
る。E(’l5IIlv1はそれぞn第一の半導体層3
の伝導帯端、価電子帯端のエネルギー。B6. 、I!
iv@はそnぞれ第二の半導体層の、伝導帯端、価電子
帯端のエネルギーである。If!toはゲート電極1の
フエルミレベ、11/、Byは半導体層3.4に共通り
、*7:r−ルミレベルである。1のゲート電極金属の
材料の一例と1−ては、ツバツタ法、真空蒸着法などで
形成さnるアルミニウム、クロム、モリブデン等が用い
らt″L1厚さは通常500〜3000ムである。2の
ゲート絶縁膜は%ツバツタ法、真空蒸着法、プラズマO
VD法などで形成さnる、二酸化シリコン、窒化シリコ
ン等が用いられ、厚さは通常500〜3000ムである
。本発明の薄膜トランジスタはガラスなどの単結晶では
ない絶縁性基板上に形成されるので、3および40半導
体膜として妹、プラズマav’n法、光G’VD法など
で、500℃以下の基板上に形成できる、非晶質あるい
は微結晶化半導体膜が用いられる。特に非晶質シリコン
線プラズマOVD法、光ovp法などで形成すると、禁
制帯内の局在準位密度が10”/d LV以下の良好な
半導体膜が得られることが知らnているので本発明に用
いる半導体膜として適している。微結晶または非晶質シ
リコンは、リン、ボロン等の不純物をドープすることに
より%型にもPfflにも導電の型を変光らnることが
知られている。更に)/ドープO膜は真性に近い牛導体
の性質が得らnることも知らnている。FIG. 1(B) is a diagram showing a band structure in a flat band state in a cross section of a channel region of a field effect thin film transistor of the present invention. In Figure 1 (α), 1 is the gate electrode metal, 2 is the gate insulating film, and 3 is the forbidden band width "Is".
A first semiconductor layer doped to n-type with a thickness of 150A or less, 4 is the same forbidden band EI as 3, and a second semiconductor with a thickness of tooZ or more and a small amount of impurity doping (3). It's layered. E('l5IIlv1 is n first semiconductor layer 3
Energy at the conduction band edge and valence band edge. B6. , I!
iv@ is the energy of the conduction band edge and the valence band edge of the second semiconductor layer, respectively. If! to is the lumi level of the gate electrode 1, 11/, By is common to the semiconductor layer 3.4, and *7 is the r-luminium level. An example of the gate electrode metal material (1) is aluminum, chromium, molybdenum, etc., which are formed by a spitting method, a vacuum evaporation method, etc., and the thickness thereof is usually 500 to 3000 μm. The gate insulating film in step 2 was made using the %Tsubatsuta method, vacuum evaporation method, and plasma O.
Silicon dioxide, silicon nitride, or the like, which is formed by a VD method or the like, is used, and the thickness is usually 500 to 3000 μm. Since the thin film transistor of the present invention is formed on an insulating substrate that is not a single crystal such as glass, it is possible to form a 3 and 40 semiconductor film on a substrate at 500° C. or lower using a plasma AV'N method, a photoG'VD method, etc. An amorphous or microcrystalline semiconductor film that can be formed is used. In particular, it is known that when formed by amorphous silicon line plasma OVD method, optical OVP method, etc., a good semiconductor film with a localized level density in the forbidden band of 10"/d LV or less can be obtained. It is suitable as a semiconductor film used in the invention.It is known that microcrystalline or amorphous silicon can change its conductivity type to % type or Pffl by doping it with impurities such as phosphorus or boron. Furthermore, it is known that the doped O film has properties close to that of an intrinsic conductor.
次に、本発明の薄膜トランジスタの動作について説明す
る。第1図(6)は、第1図(C)の薄膜トランジスタ
のゲート電極に正電圧を加えてオン状態としたときのバ
ンド図を示す。半導体層3の伝導帯に、誘起された電子
は、厚さxsoffi以下の非常に薄い領域に閉じ込め
らnる。この為、半導体層3の厚さ方向の電子の運動は
量子化さn、半導体層3の伝導帯の電子は二次元ε子ガ
スとして振るまり。二次元電子ガスの状態密度は、伝導
帯端ではOで、−足のエネルギーΔEだけ上の所から有
限の0で無い値をとり、二次元電子ガス化していない場
合と比べ大きな自由電子警度を得る。更に、非晶質物質
中の伝導帯を流nる電子は伝導体からのエネルギー差が
大きな程、不規則な原子配列によるポテンシャルから受
ける影響が小さくなり大きなモビリティ()10 ai
/ V 、 Bee)を有する。こうして、電子濃度
とモビリティ−が大きな第1図φ)のトランジスタは大
きな電流を流せるので高速で動作する。室温付近で二次
元電子ガスが得らnる条件は、第1図0)で△E十Δに
、がQ、3s”l以上で、半導体層3の厚さが1so′
i−以下と薄い場合である。以上の説明のごとく本発明
による、チャンネル部の構造を持つ薄膜トランジスタは
、ゲート電圧の印加により、チャンネルのコンダクタン
スを制御でき、かつ大きなオン電流が流せ、高速で動作
する。以下具体的な構造で本発明の実施例を示す。Next, the operation of the thin film transistor of the present invention will be explained. FIG. 1(6) shows a band diagram when a positive voltage is applied to the gate electrode of the thin film transistor of FIG. 1(C) to turn it on. Electrons induced in the conduction band of the semiconductor layer 3 are confined in a very thin region having a thickness of less than xsoffi. Therefore, the movement of electrons in the thickness direction of the semiconductor layer 3 is quantized, and the electrons in the conduction band of the semiconductor layer 3 behave as a two-dimensional epsilon gas. The density of states of the two-dimensional electron gas is O at the conduction band edge, and takes a finite non-zero value from the point above the negative energy ΔE, and has a large free electron density compared to the case where it is not converted into a two-dimensional electron gas. get. Furthermore, the larger the energy difference from the conductor for electrons flowing through the conduction band in an amorphous material, the less the influence from the potential due to irregular atomic arrangement will be, and the greater the mobility ()10 ai
/V, Bee). In this way, the transistor φ) in FIG. 1, which has a large electron concentration and mobility, can flow a large current and therefore operates at high speed. The conditions for obtaining a two-dimensional electron gas near room temperature are as shown in Figure 1 (0), △E + Δ, Q, 3s''l or more, and the thickness of the semiconductor layer 3 is 1so'
This is the case where it is as thin as i- or less. As described above, the thin film transistor having the structure of the channel portion according to the present invention can control the conductance of the channel by applying a gate voltage, can flow a large on-current, and operates at high speed. Examples of the present invention will be shown below with specific structures.
第2図は、本発明の薄膜トランジスタの一実施例のチャ
/ネル部の断面の構造を示す図である。FIG. 2 is a diagram showing a cross-sectional structure of a channel portion of an embodiment of a thin film transistor of the present invention.
第2図で5はガラスなどの絶縁性基板、6はアルミニウ
ム、クロム等のゲート電極、7は二酸化シリコン、チツ
化シリコン等よりなるゲート絶縁膜、8はn型にドープ
さnた非晶質シリコン等よりなる厚さ150A以下の第
1の半導体層、9.10はそnぞ牡ソー、ス、ドレイン
接触の為のn十非晶質シリコ/層、ii 、 12はそ
オLぞれソース、ドレイン電極、13は不純物をドープ
していない第2の、厚さ100OA以上の非晶質シリコ
/層、14は保護用絶縁層で、二酸化シリコン、チツ化
シリコン等よりなる。第1及び第2非晶質シリコン層は
プラズマOVD法、光OVD法彦どで形成することがで
き、水素、フッ素等を含んでいても良い。また非晶質で
なく、微結晶化シリコン(プラズマOVD法等で形成し
た〕を第1及び第2の半導体層としても良い。In Figure 2, 5 is an insulating substrate such as glass, 6 is a gate electrode made of aluminum, chromium, etc., 7 is a gate insulating film made of silicon dioxide, silicon nitride, etc., and 8 is an amorphous material doped with n-type. A first semiconductor layer made of silicon or the like and having a thickness of 150A or less, 9.10, 100 amorphous silicon/layers for source, drain and source contacts, ii and 12, respectively. The source and drain electrodes 13 are a second non-doped amorphous silicon layer with a thickness of 100 OA or more, and 14 is a protective insulating layer made of silicon dioxide, silicon nitride, or the like. The first and second amorphous silicon layers can be formed by plasma OVD, optical OVD, or the like, and may contain hydrogen, fluorine, or the like. Moreover, instead of amorphous, microcrystalline silicon (formed by plasma OVD method or the like) may be used as the first and second semiconductor layers.
第3図は、本発明の薄膜トランジスタの他の実施例の断
面構造を示す図である。第3図で15はガラスなどの絶
縁性基板、16はゲート電極、17はゲート絶縁膜、1
8は非晶質シリコンよりなる厚さ150A以下(り第1
の半導体層、1.9.20はそrt−t’nソーソード
レイン電極、21は厚さ1000五以上のノンドープ又
はP型の非晶質シリコン層、nは保護用絶縁層である。FIG. 3 is a diagram showing a cross-sectional structure of another embodiment of the thin film transistor of the present invention. In FIG. 3, 15 is an insulating substrate such as glass, 16 is a gate electrode, 17 is a gate insulating film, 1
8 is made of amorphous silicon and has a thickness of 150A or less (the first
1.9.20 is an rt-t'n source drain electrode, 21 is a non-doped or P-type amorphous silicon layer with a thickness of 1000 mm or more, and n is a protective insulating layer.
本実施例では、ソース、ドレインが、半導体層18と絶
縁層17の界面に形成さnるチャンネルと同じ平面上に
あるので、ソース。In this embodiment, the source and the drain are on the same plane as the channel formed at the interface between the semiconductor layer 18 and the insulating layer 17;
ドレイン部で、第3図の場合には現わnる、第20半導
体層の抵抗を除くことができ、より高性能のトランジス
タを実現できる。半導体層21がP型の場合は、第1図
(−で、ΔECがより大きな場合として考えることがで
きる。In the drain part, the resistance of the 20th semiconductor layer, which appears in the case of FIG. 3, can be eliminated, and a transistor with higher performance can be realized. When the semiconductor layer 21 is of P type, it can be considered as the case in FIG. 1 (-) where ΔEC is larger.
以上に記した本発明の薄膜トランジスタは、ガラスなど
の絶縁性基板上に形成でき、高速の動作が可能なので、
同一基板上に表示部と駆動回路を形成した、回路接続が
安価で、コンパクト、信頼性の高いアクティブマトリク
ヌ型表示装置や、同一基板上にセンサーと駆動回路を有
するデバイスの実現を可能にした。The thin film transistor of the present invention described above can be formed on an insulating substrate such as glass and can operate at high speed.
It has made it possible to create active matrix display devices that have a display section and drive circuit on the same substrate, and which are compact and highly reliable with inexpensive circuit connections, as well as devices that have sensors and drive circuits on the same substrate. .
第1図(α)、第1図(6)は本発明の実施例のバンド
構造を示す図、第2図、第3図は本発明の実施例、の断
面構造を示す図である。
10.ゲート電極、21.ゲート絶縁層、3゜40.半
導体層、50.ガラス基板、61.ゲート電極、70.
ゲート絶縁膜、80.半導体層、g、1o、、n土層、
110.ソース電極、128.ドレイン電極、13.、
半導体層s 14−−絶縁層、150.ガラス基板、1
60.ゲート電極、170.ゲート絶縁層、18 、
、 n土層、190.ソース電極、加、。ドレイ/電極
、21 、 、半導体層、乙1.絶縁層。 以上
第1図(a)
第1図(ip)
lどFIG. 1(α) and FIG. 1(6) are diagrams showing the band structure of the embodiment of the present invention, and FIGS. 2 and 3 are diagrams showing the cross-sectional structure of the embodiment of the present invention. 10. Gate electrode, 21. Gate insulating layer, 3°40. semiconductor layer, 50. Glass substrate, 61. gate electrode, 70.
Gate insulating film, 80. semiconductor layer, g, 1o,, n soil layer,
110. source electrode, 128. Drain electrode, 13. ,
Semiconductor layer s 14--insulating layer, 150. glass substrate, 1
60. gate electrode, 170. gate insulating layer, 18;
, n soil layer, 190. Source electrode, addition. Dray/electrode, 21, , semiconductor layer, B1. insulation layer. Figure 1 (a) Figure 1 (ip) l etc.
Claims (3)
極、ドレイン電極よりなり、半導体層は、厚さ150A
J9J下の不純物をドープした第一の半導体層と、不純
物濃度が上記第一の半導体層よりも少いかまたは逆の尊
電型の厚さ100OA以上の第二の半導体層が積層さn
ていることを特徴とする、絶縁性基板上に形成さnた、
電界効果型の薄膜トランジスタ。(1) Consists of a gate electrode, gate insulating film, semiconductor layer, source electrode, and drain electrode, and the semiconductor layer has a thickness of 150A.
A first semiconductor layer doped with impurities under J9J and a second semiconductor layer having a thickness of 100 OA or more and having an impurity concentration lower than or opposite to that of the first semiconductor layer are laminated.
formed on an insulating substrate, characterized by
Field effect thin film transistor.
コンであることを特徴とする特許請求の範囲第一項記載
の薄膜トランジスタ。(2) The thin film transistor according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are made of amorphous silicon.
リコンであることを特徴とする特許請求の範囲第一項記
載の薄膜トランジスタ。(3) The thin film transistor according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are made of microcrystalline silicon.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP1542684A JPS60160170A (en) | 1984-01-31 | 1984-01-31 | Thin film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1542684A JPS60160170A (en) | 1984-01-31 | 1984-01-31 | Thin film transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60160170A true JPS60160170A (en) | 1985-08-21 |
Family
ID=11888445
Family Applications (1)
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---|---|---|---|
JP1542684A Pending JPS60160170A (en) | 1984-01-31 | 1984-01-31 | Thin film transistor |
Country Status (1)
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