JPS60147992A - Memory circuit - Google Patents

Abstract

PURPOSE:To save a time required for charging an input line and decoding and to shorten an overall operation time by operating in parallel decoding of address data and data output from a memory section. CONSTITUTION:When an address selection signal 31 is at high level, the data memory section 20 outputs memory data of an address designated by an address decoder 11, while an address decoder 12 charges an input line and decoding. When the signal 31 goes to low level, the memory section 20 outputs memory data designated by the decoder 12, while the decoder 11 inputs next address data and decodes.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to the above circuit, and more particularly to a read-only stacking circuit.

(Prior art) Conventionally, a read-only hoisting circuit (hereinafter referred to as OM) is
The address expressed in base numbers is decoded, and information on the address pointed to as a result is outputted as t-.

FIG. 1 is a block diagram of 12 parts of a conventional OMf.

The address decoder IO inputs address data, decodes it, and sends a decode signal to the first data record section 20 to output the data stored at the designated address.

FIG. 2 is a waveform diagram for explaining the operation of the ROM shown in FIG. 1.

Assume that address data is input to the address decoder at time a. It is assumed that charging of the input line of the address decoder starts from this point and charging is completed at one point. When charging is completed, it starts decoding the address data and outputting the decoded signal. Assume that the output of the decoded signal is completed at time C. It is assumed that data starts to be output from the data stacking section 20 from the time point d, and reading is completed at a time point d. If this output is latched, the operation ends, but if not, the same operation is repeated.

This reading method has the disadvantage that each time a different address is read out, charging of the input line begins, which increases the time required to complete reading.

(Objective of the Invention) An object of the present invention is to provide a memory circuit that can eliminate the above-mentioned drawbacks and shorten the overall operating time.

(Structure of the Invention) A memory circuit of the present invention includes a plurality of address decoders that input address data and determine the address of recorded information, and a single address decoder that receives all output signals from the plurality of address decoders. The address selection circuit selects only the output signal of the address selection circuit, and the data storage section receives the output signal of the address selection circuit and outputs the information stored at the selected address.

(Example) Next, embodiments of the present invention will be described using the drawings.

FIG. 3 is a block diagram of one embodiment of the present invention.

In this embodiment, address data A and Bl are respectively input and recorded.
l, l2, and an address selection circuit 30 which inputs the output signals from these two address levers and selects only the output signal from one address decoder, and inputs and selects the output signal of the address selection circuit 3o. and a data record section 2o that outputs the information stored at the specified address.

The data generator 2o has n addresses from 1 to nt, and has n input terminals tOW. The output terminal of the address selection circuit W&30 is connected to each of the n input terminals. Different address data A and B are input to address decoders 11 and 12, respectively. The address selection circuit @30 selects either address data A or address data B under the control of the address selection signal 31.

FIG. 4 is a waveform diagram for explaining the operation of the embodiment shown in FIG. 3.

@ when the address selection signal 31 is high level.

The data release unit 20 outputs the address specified by the address decoder 1"1, and during this time, the address decoder 1"1 charges the address decoder (a→bJ) and decodes (starts from point 1). Is going.

When the address selection signal 31 becomes low level, the data storage section 20 outputs the storage data specified by the address decoder 12, and during this period, the address decoder 11
performs all the operations of inputting and decoding the next address data.

Repeat this.

In this way, by operating the decoding of address data and the data output from the data recording section in parallel, the time required for charging and decoding the input line can be saved, and the overall operating time can be extremely shortened.

(Advantageous Effect 2 of the Invention As explained in detail above, 5) According to the present invention, the time required to read the data written in the data memory primary part is shortened, and the memory circuit operates at high speed as a whole. is obtained.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the main parts of a conventional ROM, Figure 2 is a waveform diagram for explaining the operation of the ROM shown in Figure 2, and Figure 3 is a waveform diagram for explaining the operation of the ROM shown in Figure 2.
The figure is a block diagram of one embodiment of the present invention, and FIG. 4 is a waveform diagram for explaining the operation of the embodiment shown in FIG. 10.11.12 Address decoder, 20
... Data record (model section, 30 ... Address selection circuit, 31 ... Address selection circuit. Agent: Susumu Uchihara, patent attorney.)

Claims (1)

[Claims] a plurality of address decoders that input address data and determine all addresses of the starting information; an address selection circuit that selects only the output signals from the address decoders of the input rake from among the output signals from the plurality of address decoders; 1. A stacking circuit comprising: a first data record section inputting an output signal of an address selection circuit and outputting information stored at a selected address.