JPS60134435A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To upgrade the general-purpose properties of a semiconductor IC by a method wherein, when static RAMs are disposed in a matrix type and the static RAMs are used as the semiconductor IC in a master slice system, the IC is made to have a ROM function, by which information are fixed, by giving a reference potential to the input part or output part of the information storage part of each RAM through each switching element. CONSTITUTION:The gate of a P-channel MISFET element QP1 and the gate of an N- channel MOSFET elemen QN1 are mutually connected and the drain of the element QP1 and the source of the element QN1 are mutually connected. Also, the source of the element QP1 is connected to a reference voltage terminal VDD, the drain of the element QN1 is connected to a reference voltage terminal VSS, and a first inverter circuit is constituted of these elements. Moreover, a second inverter circuit is constituted of a P- channel MOSFET element QP2 and an N-channel MOSFET element QN2 in such a way that the abovementioned first inverter circuit has been constituted of the element QP1 and the element QN1. An N-channel element QN3 connected to a data line DL is connect ed to the connecting point of the drains and sources of these elements, and at the same time, the same element QN4 as the element QN3 is also connected to the connecting point of the gates of the elements.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device, and particularly relates to a random access memory [hereinafter referred to as below] that adopts a master slice method.

RAM (Random Access Memory
)] The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device equipped with the following.

[Background technology]

For example, semiconductor integrated circuit devices for computers need to be designed in small quantities and in a wide variety of products within a short period of time, so the so-called master slice method is adopted as a design method.

As a result, many logical functions can be extracted from the semiconductor integrated circuit device by changing only the wiring pattern forming step, which is the final manufacturing step of the manufacturing process, without changing its basic design.

First, a semiconductor integrated circuit device employing the master slice method is required to have not only a logic function but also a memory function. Therefore.

A semiconductor integrated circuit device that has both of these functions has been proposed (2.
0M0S gate array with bit RAM on 3). this is,
Insulated gate field effect transistors of different conductivity types (M
ISFET), i.e.

Complementary part MISFET [hereinafter -0M I S (Oom
-plementa, ry MISFET)]
Basic cells consisting of are arranged regularly, and it has a random logic section from which a logical function can be extracted, and a RAM section provided exclusively for extracting a memory function.

However, as a result of the inventor's study on such technology, the RAM provided exclusively for configuring the storage function
The section has only patterns that can constitute RAM, so part or all of it can be used as read-only memory [
Below, ROM (ReadQnly Memory)
The conclusion was that it cannot be used as

At present, there is a significant demand for semiconductor integrated circuit devices having logic functions as well as RAM and RoM (ROM) &' It is estimated that it will be necessary to make a basic design for a plurality of semiconductor integrated circuit devices.

[Purpose of the invention]

An object of the present invention is to provide a technique that can improve the versatility of a semiconductor integrated circuit device.

Another object of the present invention is to provide a technique that allows a semiconductor integrated circuit device equipped with a RAM section to have a ROM function.

The foregoing and other objects and novel features of the present invention are accomplished by the description of the present specification and the accompanying drawings.

It will become clear.

[Summary of the invention]

A brief summary of five representative inventions among the inventions disclosed in this application is as follows.

In other words, a static RAM (hereinafter referred to as a static RAM) is a static RAM (hereinafter referred to as
In a semiconductor integrated circuit device equipped with S RAM (Static RAM), an input section or an output section of an information storage section via a switching element of the memory cell is connected to a predetermined reference potential through a wiring pattern forming process. RO with fixed memory cell information
Due to the ability to provide the M function, SRAM
An object of the present invention is to improve the versatility of a semiconductor integrated circuit device equipped with a semiconductor integrated circuit device.

〔Example〕

Hereinafter, the configuration of the present invention will be described in detail together with examples.

This embodiment uses an SRAMv that adopts the master slice method.
An explanation will be given using the semiconductor integrated circuit device provided.

FIG. 1 is a schematic diagram of a semiconductor integrated circuit device equipped with an SRAM for explaining the present invention in detail.

In all the figures, parts having the same functions are given the same symbols, and repeated explanations will be omitted.

In FIG. 1, reference numeral 1 denotes a semiconductor integrated circuit device employing a master slice method, and is equipped with a logic function and a memory function. Reference numeral 2 denotes an n-type semiconductor substrate made of silicon single crystal, and is used to constitute the semiconductor integrated circuit device 1. Reference numeral 3 denotes a plurality of external terminals (ponding pads) arranged around the outer periphery of the semiconductor integrated circuit device 1, which are used to exchange signals and the like with external devices. Reference numeral 4 designates a plurality of input/output buffer circuits provided between the external terminal 3 and an internal circuit to be described later, and is for controlling the signal level transmitted between them. 5 is the central part of the semiconductor integrated circuit device 1;
That is, they are a plurality of basic cells arranged in a random logic section, which will be described later, and are used to configure a logic function. This basic cell 5 is composed of 0M15, and its basic design is such that it can constitute a two-man power NAND gate circuit or a three-man power NAND gate circuit. A plurality of basic cells 5 are regularly arranged in a row direction to constitute a basic cell column, and a plurality of basic cell columns are regularly arranged in a column direction to constitute a random logic section. Reference numeral 6 denotes a wiring area provided between the basic cell columns, and is mainly used for providing wiring for electrically connecting logic circuits constituted by the basic cells 5. Reference numeral 7 denotes a RAM unit provided exclusively in a predetermined part of the semiconductor integrated circuit device 10, and is used to configure a storage function. In this RAM section 7, a plurality of memory cells provided in a pattern capable of forming an SRAMv are arranged in rows and columns, and the wiring pattern forming step Kj is the final forming step of the manufacturing process of the semiconductor integrated circuit device f1. Therefore, part or all of it can be configured as a ROM.

Next, a case will be specifically described in which the information of the memory cells that can configure the SRAM is fixed and the memory cells of the ROM are configured.

FIG. 2 is an equivalent circuit diagram showing one memory cell that can constitute an SRAM for explaining the present invention in detail, and FIG. 3 is a plan view of one memory cell showing its specific configuration. It is. Note that in FIG. 3, in order to make the drawing easier to see, the interlayer insulating film that should be removed between each conductive layer is not shown.

In Figure 2, DL and DL are data lines, WL is a terminal connected to a word line, ■DD is a ■DD reference voltage terminal, and v
ss is a V88 reference voltage terminal. QNIIQN2 is an n-channel M whose one end is connected to the reference voltage terminal v88.
I S FET-Qpt, Qpi are p-channel MISFETs with one end connected to the reference voltage terminal VDD, and each other end connected to MISFETQNl.
and M18FETQ, , an inverter circuit l, and M
VS is formed with an inverter circuit (2) made up of ISFETQN2 and MI5FETQP2. These two inverter circuits 1. II constitutes a flip-flop, and constitutes an information storage section of a memory cell that can constitute an SRAM.

QN3 is an n-channel Ml 5FET with one end connected to the data line DL and the other end connected to the output part of the inverter circuit I and the input part of the inverter circuit ■, and is used as a switching element and has a memory cell configuration. It is for the purpose of QN4 is an n-channel MISFET with one end connected to the data line DL and the other end connected to the input part of the inverter circuit I and the output part of the inverter circuit ■.
It is used as a switching element and is used to configure a memory kill. In general, these constitute memory cells that can constitute SRAM. 8
is a connection line whose one end is connected to the reference voltage terminal vDDK and whose other end is the output of the inverter circuit (2) and connected to the input of the inverter circuit H.

This is for configuring SRAM memory cells and ROM memory cells. Through this connection line 8, the data line DL can read the DD reference potential from the reference voltage terminal vDD via the MISFETQNa, and the data line DL can read the DD reference potential from the reference voltage terminal vDD via the MISFETQN4 and
The v811 reference potential can be read out from the reference potential terminal vss through MISFET QN2, which is in the "ON" state. Also, the other end of the connection line 8 is connected to the input part of the inverter circuit I, which is the input part of the inverter circuit I. If connected to the output part, the data line DL will be in the ON state and read out the V88 reference potential through the MlSFETQNS and the VDD reference potential through the M1SFETQN, respectively. I can do it.

In FIG. 3, a specific configuration will be explained.

The two are p-type well regions (p-well) provided in a predetermined royal surface portion of the semiconductor substrate 20, and are n-channel Ml.
This is for configuring a 5FET. 2B is an n-type well region provided on a predetermined main surface portion of the semiconductor substrate 20, and is used to configure a p-channel MISFET. A field insulating film 9 is provided on the main surface of the well regions 2A and 2B between the semiconductor elements, and is used to electrically isolate them. IOA is MI8FET
Q...

QPI and MI 5FETQN2. It is a wiring provided in the Q, 2 formation area by the first conductive layer in the manufacturing process, and is mainly used for 5 °C, MISFETQN, QN.
2t Q,, Q,2 is for forming the gate electrode. IOB is M I SF E TQNa.

This is a wiring provided in the QN4 formation region by the first conductive layer, and is connected to the word line WL and MI8FETQ, 3.
The gate electrode is formed in the Q□ formation region. The wiring 10A and IOB are made of polycrystalline silicon, for example.

11 is M I S F E T Q, , engineering, QN2. Q
N3. It is an n+ type semiconductor region provided on the main surface of the well region 28 on both sides of the wirings 10A and 10B in the QN4 formation region, and is used as a source region or a drain region.
This is for configuring the channel MIsFETv.

12 is M I S F E T Qp 1 , Qp 2
This is a p+ type semiconductor region provided on the main surface of the well region 2B on both sides of the wiring 10A in the formation region, and is used as a source region or a drain region, and is used as a p-channel MISFE.
There is also a note about Tameno who does TVM. 13A has one end connected to a predetermined semiconductor region 11 and the other end connected to data lines DL, DL.
This is a wiring provided by the second conductive layer in the manufacturing process, and is used to connect them.

This second conductive layer and the third conductive layer in the manufacturing process described later are formed in the wiring pattern formation process, and semiconductor integrated circuit devices that adopt the master slicing method can be used in various ways just by changing this wiring pattern. It is now possible to extract the logical functions of Reference numeral 13B denotes a wiring provided by the second layer conductor tNII so as to connect predetermined semiconductor elements (MlSFET). 130 is a wiring connected to the reference voltage terminal 88 and provided by the second conductive layer. 13D is a connecting wire (8) whose one end is connected to the output part of the inverter circuit I, which is connected to the input part of the inverter circuit ■, and whose other end is connected to the wiring connected to the reference voltage terminal ■DD, which will be described later. , a second conductive layer.

Therefore, since the connection line BD (81) can be provided only by changing the mask for patterning the second conductive layer t, an SRAM memory cell can be easily configured into a ROM memory cell.

14 is a wiring connected to the reference voltage terminal vDD and provided by the third conductive layer. Further, the wiring 14 may be configured by a p+ type semiconductor region connected to the reference voltage terminal VDD. Oat is a predetermined semiconductor region 11.
12 and a predetermined wiring 13, 01. 023 is a connection portion between the predetermined wiring 13 and the predetermined wiring 14. 023 is a connection portion between the predetermined wiring 13 and the predetermined wiring 14.

Note that this embodiment has been described with reference to a case where it is applied to a semiconductor integrated circuit device that includes a random logic section that constitutes a logic function and a RAM section that constitutes a storage function.
The present invention may also be applied to a semiconductor integrated circuit device having only a section.

〔effect〕

(1) In a semiconductor integrated circuit device equipped with a RAM in which memory cells are arranged in rows and columns, information of the memory cells can be transmitted by connecting a predetermined portion of the memory cell to a predetermined reference potential via a switching element. This fixation makes it possible to configure memory cells in RAMs, especially SRAMs, and VROMs.

By virtue of (2) and (1), it is possible to obtain various different logic functions and storage functions, thereby making it possible to improve the versatility of a semiconductor integrated circuit device equipped with a RAM.

As above, the invention made by the present inventor has been specifically explained based on the examples, but the present invention is not limited to the above-mentioned examples.
[Of course, k can be changed. For example, in a semiconductor integrated circuit device equipped with a dynamic RAM in which a plurality of memory cells arranged in rows and columns are arranged in series with a switching element and a capacitive element serving as an information storage section, Information may be fixed by connecting a predetermined portion to a reference potential.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a semiconductor integrated circuit device equipped with a DRAM for explaining the present invention in detail, and FIG. 2 is a schematic diagram of one memory cell that can be configured as an SRAM'Y for explaining the present invention in detail. FIG. 3 is a plan view of one memory cell showing the specific configuration of FIG. 2. In the figure, 1... semiconductor integrated circuit device, 2... semiconductor substrate, 2A, 2B... well region, 3... external terminal,
4...Human output buffer circuit, Death...Basic cell, 6...
・Wiring area, 7... RAM section, 8 (13D)... Connection line, 9... Field insulating film, IOA, IOB, 1
3A-130.1.4... Wiring, 11.12... Semiconductor region. Q...MISFET, DL, DL...data line, W
L: Word line, vDD, v88: Reference voltage terminal, 0: Connection section. Figure 1

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device equipped with a random access memory having a plurality of memory cells arranged in rows and columns, information recorded in at least one memory cell among the memory cells is fixed. A semiconductor integrated circuit device characterized by comprising means. 2. The memory cell constitutes a static random access memory consisting of a switching element and an information storage part, and a predetermined part of the memory cell via the switching element is connected to a predetermined reference voltage. A semiconductor integrated circuit device according to claim 1, characterized in that: 3. The memory cell is a dynamic random access memory IJ' consisting of a switching element and an information storage section.
2. The semiconductor integrated circuit device according to claim 1, wherein a predetermined portion of the memory cell is connected to a predetermined reference potential via a switching element.