JPS6013191B2 - pitch display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION In music education, one of the important things is to be able to vocalize at the correct pitch (frequency).

For this purpose, a piano is generally used, and the pitch of the speaker is trained using the pitch of the piano as a reference. However, due to reasons such as the difference in timbre between piano and voice, it is difficult to know whether the pitch of the vocalized note deviates from the pitch of the piano, and if so, by how much. In order to be able to vocalize at the correct pitch, it takes a lot of vocal practice, and even then, some children are still unable to vocalize at the correct pitch.In consideration of these points, the present invention has developed a system that allows children to visually determine the pitch of their vocalizations. The idea is to make it visually clear, and at the same time, to make it possible to visually tell the difference between the pitch and the correct pitch.

Note that the pitch display rhombus according to the present invention can be used not only for human vocalizations but also for tuning musical instruments, analyzing noise, etc., but for the sake of simplicity, we will use audio as an example. explain. That is, for example, as shown in FIG.
, C......'' character 11 and the floor name "Do, Shi, Mi...
...The characters 12 are displayed horizontally in two lines, vertical lines 14 are emitted at semitone intervals, and when the user speaks into the microphone, the vertical axis is the time axis. In the past, the pitch of voices was displayed as a birch graph.

Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 2 is a system diagram showing the overall configuration, in which the voice of a speaker is converted into an audio signal by a microphone 1, this audio signal is supplied to a filter circuit 100, and the fundamental wave component of the audio signal is extracted. This fundamental wave component is supplied to the detection circuit 2001, its frequency is detected (frequency discrimination), and this detection signal is uniformly supplied to the conversion circuit 300.

This conversion circuit 300 converts the detection signal from the previous stage into an information signal indicating which octave of the absolute scale the pitch of the fundamental wave component is included in, and which pitch within that octave. Then, the information signal indicating the pitch and the information signal indicating the octave are supplied to the monitor receiver 2 through the storage circuit 400 and the video signal forming circuit 500.

In this case, the storage circuit 400 stores the information signal up to the present time, and stores this together with the information signal at the present time.
This is for supplying it to the next stage and displaying the pitch up to that point as shown in FIG.

Further, the receiver 2 performs vertical and horizontal deflection like an ordinary television receiver, and therefore the memory circuit 40
The storage signal (information signal) from 0 is converted into a video signal for display on the receiver 2 in the forming circuit 500.
Next, let's explain each circuit in detail.

FIG. 3 is a system diagram of a filter circuit 100 that extracts the fundamental wave component of an audio signal. In this figure, 101 is a tracking filter, 102 is an amplifier, and 103 is a rectifier circuit.

The tracking filter 101 has a low-pass cutoff characteristic as shown in FIG. 4, and its cutoff frequency fc is controlled by a signal obtained by rectifying the output signal of the amplifier 102. When it is large, the cutoff frequency fc is low and the output of the amplifier 102 is 4.0, and the cutoff frequency fc is controlled so that it becomes high.
Therefore, the fundamental frequency component of the input signal is extracted at a predetermined level at the output side of the amplifier 102, and the harmonic component is
When the frequency of the fundamental wave increases and is cut off by the filter 101, the output level of the amplifier 102 decreases by 4. As the output level of the filter 101 increases, the cutoff frequency of the filter 101 decreases, and the fundamental wave component of the input signal is always extracted from the amplifier 102 at a constant level.

FIG. 5 is a circuit example showing a specific connection diagram of the filter portions of the filter 101, amplifier 102, and rectifier circuit 103 shown in FIG.
Capacitors 114, 115, field effect transistor 11
6 and 117 constitute a low-pass filter 101, and the operational amplifier 121 constitutes an amplifier 102 whose gain is determined by resistors 122 and 123.

Then, the output signal of the operational amplifier 121 is transmitted to the diode 13.
1. V is supplied to the gates of the field effect transistors 116 and 117 through a rectifier circuit 103 consisting of a resistor 132 and a capacitor 133, thereby changing the impedance value between the sources and drains of the field effect transistors 116 and 117. The cutoff frequency of 101 is controlled. The fundamental wave component extracted in this way has a phase difference with respect to the original signal because a change in phase occurs in the vicinity of the cutoff frequency of the filter 101 when its amplitude changes.

Therefore, in order to remove this phase difference, a logic circuit 105 is provided as shown in FIG. This logic circuit 105
consists of JK flip-flop circuits 106 and 107 having a clock terminal that is triggered by the falling edge of an input signal and a clear terminal that is reset by an input voltage of "0".
In both cases, a potential of "1" is always connected to the J terminal and a potential of "0" is connected to the K terminal. Flippf through 170.

The output terminal of the flip-flop circuit 106 is connected to the clear terminal of the flip-flop circuit 106, and the output terminal of the flip-flop circuit 106 is connected to the clear terminal of the flip-flop circuit 107. Furthermore, the output signal of the amplifier 102 is supplied to the clock terminal of the flip-flop circuit 106 through the waveform shaping circuit 104, and the output signal of the microphone 1 is supplied to the trigger terminal of the flip-flop circuit 107 through the amplifier 108 and the waveform shaping circuit 109. Therefore, when an audio signal Sa as shown in FIG. 6A is obtained from the microphone 1, the amplifier 102 outputs an output signal S as shown in FIG. 6B.
b is extracted and waveform-shaped by the waveform shaping circuits 104 and 109 as shown in A' and B' respectively and supplied to the logic circuit 105, a signal S as shown in FIG. 6C is generated.
c is obtained.

That is, first, at the rising edge of the waveform-shaped signal Sb', the flip-flop circuit 106 is inverted, the clearing of the flip-flop circuit 107 is released, and then, at the falling edge of the waveform-shaped signal Sa', the flip-flop circuit 107 is inverted. , the signal Sc rises, which causes 2
After 0 seconds, the flip-flop circuit 106 is cleared,
Immediately flip through its output. The stop circuit 107 is cleared, and the signal Sc falls to return to its original state. In this way, in this filter circuit 100, a pulse signal Sc having the same frequency and phase as the fundamental wave of the input signal is extracted.

FIG. 7 shows a frequency detection circuit 200 and a conversion circuit 30 that converts the frequency into two information signals of a scale and an octave.
0 is a system diagram.

In the figure, 207 is a counter, and the signal from the filter 100 described above is supplied to this counter 207, and the number of cycles of the input signal is counted.

On the other hand, 201 is, for example, a 320kHz oscillator, and this oscillation pulse is supplied to a 1/8 frequency divider circuit 202 (counter) to form a clock pulse with a 40k ratio.
supplied to

In addition, as described later, the content of the counter 205 is "512".
When the value exceeds 0, the selection circuit 204 is switched to the state shown by the dotted line, and the clock pulse whose frequency has been divided by 1/2 by the frequency dividing circuit 203 is supplied to the counter 205. Further, the contents of the counter 207 are supplied to the decoder 208, and from this the contents of the counter 207 are changed to "2n", that is, "1, 2, 4.
・At 8J, a pulse signal is taken out, while counter 2
The output signal of "256" and the output signal of "512" of 05 are supplied to the OR circuit 211, and the gate circuit 209 is made conductive by this OR output while the content of the counter 205 is "256" or more. The pulse signal from the decoder 208 described above is passed through the gate circuit 209 to a monostable multipipulator 2 with an extremely short inversion time of, for example, 50 S.
1 river is supplied, and the trailing edge of the output pulse of this multipipelator 210 triggers the monostable multipipelator 215, and this output pulse passes through the OR circuit 214 to the frequency divider circuit 202 (1/8 force counter), unta 205.2
07 to trigger these circuits.

Further, 213 is a flip-flop circuit, and this circuit 213 is configured such that the content of the counter 205 is, for example, r528.
is set by a signal taken out through the decoder (AND circuit) 212, and the filter 100
It is reset by a signal from Then, during the period when this flip-flop circuit 213 is set, “1” is set.
” is supplied to the OR circuit 214, and during this period, the frequency dividing circuit 202 and counters 205, 207 are cleared.Furthermore, when the content of the counter 207 becomes “9”, the output signal from the decoder 208 is This signal is taken out and supplied to the OR circuit 214, and the frequency dividing circuit 202 and counters 205 and 207 are cleared.

Therefore, when the pulse signal Sc is obtained from the filter 100, the flip-flop circuit 213 is reset, the clear state of the frequency divider circuit 202 and the counters 205 and 207 is released, and counting is started.

Then, when the content of the counter 205 exceeds "256", the gate circuit 209 enters the conductive state, and when the content of the counter 207 becomes "2n" in this state, the multipipulator 210 is triggered by the output of the decoder 208, and then The multipipulator 215 is triggered, and the frequency dividing circuit 202, counters 205, 20
7 is cleared. Thereafter, counting is restarted from "0" again, and this operation is repeated. In this way, the counter 205 detects the time equivalent to 2n cycles of the input signal, and the counter 207 detects the number of cycles of the input signal required for the above-mentioned detection. Assuming that the detected numerical value is "x", the frequency corresponding to this "x" is 8 when the number of cycles required for detection is 1 cycle, 2 cycles, 4 cycles, and 8 cycles. The values are different depending on the period.

However, in this case, if the time is constant and the number of periods in between is doubled, the frequency is doubled.

On the other hand, when the frequency of the fundamental wave of a signal is doubled, the signal becomes one octave higher than it was in the past. Therefore, when the above-mentioned "x" is an arbitrary number, the corresponding frequencies are 2n times larger than each other, that is, they are intervals of the same pitch name in different octaves, and the counter 205 , this note name is detected. In this case, pitch name detection is 1
The octave is divided into 256 parts and detected as a position signal in units of 256 parts. On the other hand, at counter 207,
The number of periods of the input signal is detected, thereby detecting which octave the input signal is included in.

In addition, in this device, when the content of the counter 205 is "512", the lowest frequency detected is the lowest frequency detected by the counter 207.
In this case, the frequency is 2 x 40 78.2 [HZ], and the highest frequency is when the content of the counter 205 is ``1''.
256'', the counter 207 counts ``8'', and the frequency in this case is 6 x 4 ox [HZ], which is within the frequency range of the fundamental wave of the voice (80 Hz to 1
000HZ).

Therefore, the contents of the counter 205 become "256J,"
Before gate 209 becomes conductive, counter 207
If the content becomes "8", that is, if the counter 207 counts "9", this is clearly a case where blue or harmonics other than human voices have been accidentally detected.

Therefore, in the above-mentioned device, the contents of the counter 207 are "
9'', the decoder 208 detects this, clears the frequency dividing circuit 202 and counters 205 and 207, and repeats the detection. Further, in the case of normal detection, there is a time when the input signal always has a period of 2n while the contents of the counter 205 change from "256" to "512".

However, human speech usually has frequency fluctuations (vibrato) of about 3%. Therefore, for example, if the 2n-1st period pulse is just before the content of the counter 205 reaches "256", the 2n-1st period pulse is
The content of the counter 205 is “512” when the n-th period pulse is generated.
” may not occur by then. Therefore, in the above-mentioned device, the content of the counter 205 exceeds "512" and becomes "16" (as will be described later, in this case, the selection circuit 204 is switched to the output side of the frequency divider 203.
Clearing is not performed until the number reaches "32" (approximately 6% of "512") and counting continues. However, the contents of the counter 205 are “
528'', the input signal is considered non-periodic or unstable and cannot be measured, and is sent to the AND circuit 21.
2 and sets the flip-flop circuit 213, the frequency dividing circuit 202, counter 205.
Clear 07. In this case, even if the input signals are no longer combined, the counter 205 is not cleared and counts up to "528", the flip-flop circuit 213 is set, and the next input signal is supplied to the flip-flop circuit. The frequency dividing circuit 202 and counters 205 and 207 remain in the clear state until the counter 213 is reset. In addition, in normal detection, the contents of the counter 205 are detected as one octave from "256" to "512", but as described above, when the contents of the counter 205 exceeds "512", " 512” to “102”
4" corresponds to one octave.

That is, the frequency change width corresponding to one clock pulse is halved. Therefore, in the above-described device, when the content of the counter 205 exceeds "512", the selection circuit 204 is switched, The clock pulse supplied to the counter 205 is frequency-divided by 1/2. The contents of the lower eight digits of the counter 205 obtained in this way are combined into the register 301.

Further, the contents of the counter 207 are supplied to the encoder 303 through the selection circuit 302, and the output signal of the encoder 303 is supplied to the register 304.

Furthermore, the output signal of the multi-pipulator 210 described above is supplied to the registers 301 and 304 as a write pulse.

Also, while the flip-flop circuit 213 is set, its output signal is sent to the register 300 as a clear signal.
, 304.

In this case, in the selection circuit 302, the counter 20
The output signals of each digit of ``112, 4, and 8'' of 7 are supplied to one of the switching contacts of the changeover switches 311 to 314, and the output signals of ``2, 4, and 8'' are respectively supplied to the lower digit. It is supplied to the other switching contacts of the switches 311 to 313, and the other switching contact of the switch 314 is grounded.

Therefore, when the switches 311 to 314 are switched to the solid line position, the contents of the counter 207 are supplied as is to the encoder 303, and when they are switched to the dotted line position, the contents of the counter 207 are supplied to the encoder 303. /2 and supplied to the encoder 303. Furthermore, this selection circuit 302 is controlled by the output signal "512" of the counter 205, so that the contents of the counter 205 change from "512" to "
528" 1, the contents of Kausota 207 will be 1/1.
2 and is supplied to the encoder 303. The output signal of this encoder 303 is supplied to the register 304, but in this case, as described above, writing to the register 304 is performed when the content of the counter 207 is "2n", so when writing to the register 304, counter 2
Since the content of 07 is one of “2n” (n=0, 1, 2, 3), the value of n at this time is binarized by the encoder 303 and combined into the register 304.

In this case, the contents of the counter 205 range from "512" to "
528, the counter 205 is counting twice as much as it should have been, so at this time, the contents of the counter 207 are transferred to the selection circuit 302.
After reducing the signal to 1/2 at , it is supplied to the register 304 .

In this way, one octave from the counter 205 is 258
The divided note name data and the octave data from the counter 207 are written to the registers 301 and 304. According to this circuit, the octave data and the pitch data are obtained by measuring 2n cycles of the input signal. are taken out separately.

Also, since measurement is always performed by counting 256 pulses or more, when the frequency is high and the period is short, the period required for measurement automatically increases, and the average value is taken out, so the timing of the clock pulse for detection is Errors due to this will be reduced.

Furthermore, the output signal of the flip-flop circuit 213 causes
Since registers 301 and 304 are cleared,
When there is no input signal and there is no sound, the register 301
, 304, unnecessary signals are not extracted. FIG. 8 is a system diagram of an example of the memory circuit 400.

In this figure, 401 is a read-only memory, in which pitch data obtained by dividing one octave into 256 from the register 301, pitch name data obtained by dividing one octave into 12 for each semitone, and pitch data obtained by dividing each semitone into 18, In this case, the error data is converted into
The 8-bit input signal is 1 from (0000) to (1011)
The signal is converted into a 4-bit signal representing the pitch name data of the two lotus types and a 4-bit signal representing the binary coded error data.

Then, the 8-bit output signal from the read-only memory 401 and the 2-bit octave from the register 304 are held in the register 450 according to the output signal of the monomulti 215, and this is stored in the random access memory 40.
V is supplied to 2.

Further, the output signal of the flip-flop circuit 213 is supplied to the reset terminal of the register 450 through an OR circuit 451, and its value is reset to "0" when there is no signal.
On the other hand, 403 is a synchronous board, 404 is a counter, and 403 is a synchronous board.
The vertical synchronization signal V from 03 is applied to the reset terminal of a counter 404, and the horizontal synchronization signal V is applied to the count terminal, in which the counter 404, for each vertical period,
A signal is obtained that increases by 1 in units of horizontal periods.

This signal is supplied to address Satoko of random access memory 402. Further, 405 is a variable frequency oscillator, which generates a pulse signal of, for example, 20 Hz.

This pulse signal is then supplied to a counter 407 through a gate circuit 406, and the counter 407 receives two pulse signals.
A sequentially increasing signal is obtained using a 0HZ pulse signal.
The signal from this counter 407 and the counter 40 described above
4 is supplied to a comparator circuit 408, and when they match, an output signal is supplied to an AND circuit 409. Further, a horizontal synchronization signal from the synchronization board 403 is supplied to an AND circuit 4019, and the AND output is supplied to a write control terminal of the random access memory 402 as a write pulse through an OR circuit 410. Therefore, typically the random access memory 40 is used for each horizontal period.
The contents of 2 are read out in order, and this reading is repeated every vertical period.

On the other hand, when the contents of the counters 404 and 407 match, a signal is taken out from the comparison circuit 408, and this -Atsushi signal is 1
A signal is taken out from the AND circuit 409 during the horizontal synchronization signal period, that is, the horizontal blanking period, and this signal is supplied to the random access memory 402 as a write pulse through the OR circuit 410. The contents of registers 301 and 304,
That is, data obtained by detecting the pitch of the input signal is written to an address determined by the contents of the power counters 404 and 407 of the random access memory 402. Furthermore, each time the contents of the counter 407 are incremented by one for each write, the addresses written to the random access memory 402 are sequentially moved. In this case, as will be described later, for example, the 16 horizontal periods at the top of the screen are used as the display area for note names and scale names, so 16 is set on the counter 407 to prevent data from being written to this area. Preset.

Further, the output signal of the counter 407 is supplied to the decoder 411, and when the number of horizontal scanning lines used for display on the display surface of the display device, which will be described later, reaches 240, the decoder 411
A signal is taken from 11 and applied to the enable terminal of counter 407 to prevent counter 407 from counting further.

Further, the output panel of the filter 100 described above is connected to a retrigger-pull monostable multi-pipelator 412, and the output signal of this multi-pipelator 412 controls the gate circuit 406, and the multi-pipelator 412 is inverted. During this period, gate circuit 406 is rendered conductive.

Therefore, if there is no input signal for the inversion time of the multi-pipe layer 412, for example, one second, the gate circuit 406 becomes non-conductive, the counter 407 stops counting, and writing to the random access memory 402 is disabled. It will no longer be done. Further, when the input signals are combined again, the multipipulator 412 is inverted, the gate circuit 406 becomes conductive, the counter 407 starts counting again, and writing to the random access memory 402 is started again. However, in this case, the contents of the counter 407 at the time when writing is restarted are incremented by the number corresponding to the inversion time of the multipipulator 412 since the last time the signal was supplied with V. and
During this time, data of "0" is written in each address of the random access memory 402 because there is no input signal. Furthermore, the IJ start signal from display control circuit 600 is supplied to the reset terminal of register 450 and the preset terminal of counter 407 through OR circuit 451, and is also supplied to the write control terminal of random access memory 402 through OR circuit 410.

Therefore, while the counter 404 counts one vertical period,
If this restart signal continues to be supplied, "0" is written to each address of the random access memory 402, all data is erased, and data can be written again from address 16 given by the value of the counter 404. Furthermore, in the above example, since the oscillation frequency of the oscillator 405 is set to 20Hz, the contents of the registers 301 and 304 at that time, that is, data regarding the pitch of the input signal, are transferred to the random access memory 402 20 times per second.
However, by varying the frequency of the oscillator 405 using a control signal from the display control circuit 600, the number of times this writing is performed can be changed, and the time interval for detecting the pitch of the input signal can be changed.

In this way, data from registers 301 and 304 is stored in random access memory 402 through register 450. In this circuit, when there is no input signal, the output signal of oscillator 405 is cut off and the counter Since the contents of 407 do not change, "0" data when there is no input signal is repeatedly written to the same address, which prevents unnecessary use of many addresses with such useless data. There is no.

Moreover, in this case, even if there is no input signal, the counter 40 remains
Since the count of 7 continues, the counter 40
Data "0" is written to the address designated by 7, and this darkness becomes a blank, making it clear where the input signal is interrupted. Furthermore, in the circuit described above, the oscillator 405
By changing the oscillation frequency of the input signal, the time interval for writing the pitch of the input signal can be arbitrarily changed.

FIG. 9 is a system diagram of a signal forming circuit 500 that forms a video signal for displaying data stored in the random access memory 402 on the television receiver 2. In this circuit, 621 is a 10-bit counter, the upper two bits are a binary counter representing octave data, and the next four bits are a binary counter representing octave data.
The bits are a 12-decimal counter that displays the note name, and the lower 4 bits are a 16-digit counter that displays the chromatic scale divided into 16 equal-tempered scales, which corresponds to the output of the random access memory 402. There is.

After the address of the random access memory 402 is incremented according to the horizontal sync pulse and its output is changed, the monostable multipipulator 522 is triggered at the trailing edge of the horizontal sync pulse;
The output of the random access memory 402 is written to the counter 521 in parallel. Further, 523 is a 2-bit counter to which, for example, a pulse from a pulse oscillator 524 having a repetition frequency of z is supplied as a clock signal, and the monostaple multipipulator 52
Coupler 5 is triggered by the output signal from monostaple multipipulator 525, which is triggered by the trailing edge of the signal from Coupler 5.
23 is cleared.

Furthermore, for example, a changeover switch 526, 5 that can be switched to three stages
27, 528, and 529, which are interlocked with each other, and their fixed contacts are denoted by symbols a, b, and c in order from the left terminal in the figure, and the movable bushing point is denoted by d, respectively. The lower bit signal of the counter 523 is sent to the switch 52
7 contacts b. c, the upper bit signal is supplied to contact c of switch 526, and contacts a and b of switch 526 are supplied with V, respectively.
and contact a of switch 527 have output 1 from power supply 530.
is given, and the outputs obtained at contacts d of switches 526 and 527 are connected to a ground circuit 531, respectively.

When the AND output is 1, the oscillation of the oscillator 524 is stopped, and when the AND output is 0, the AND output is supplied to the oscillator 524 as a control signal so that oscillation occurs. Furthermore, in this example, the lowest bit signal of the counter 521 is used for inconvenience, and the higher bit signal is used as the contact a of the switch 526.
Then, the upper bit signal is sent to contact a of switch 528.
．． b, respectively, and a signal 0 is supplied to contact c of switch 528 and contacts b and c of switch 529,
The signals obtained at the contacts d of the switches 528 and 529 are supplied to the comparator circuit 501 together with the upper 7 bits.

In addition, the above-mentioned mono staple multivibrator 522
and 525 constitute a pulse delay circuit. When the contacts d of the switches 526 to 529 are switched to the contacts a, the AND circuit 531 is supplied with the input 1, so the AND output is also 1, and therefore the oscillator 524 does not oscillate. , counter 521
and 523 are not counted up.

On the other hand, the output of the counter 521 is the lowest bit signal (20
The upper 9-bit signals excluding the output from the terminal of Contact d of switches 526 to 529
is switched to contact b, AND circuit 531
The signal 1 from the switch 526 and the lower bit signal of the counter 523 are supplied from the switch 527 as inputs, respectively.

Therefore, the output of the counter 523 is "0r" (or "lr"), the output of the AND circuit 531 is 1, and the oscillator 524 has stopped oscillating, but the output of the random access memory 402 is changed by the horizontal synchronization pulse, and then After that output is written to the counter 521 based on the output from the monostable multivibrator 522, the counter 523 is set to "0" based on the output pulse from the monostable multivibrator 525. The oscillator 524 generates one pulse, and the counter 52
As soon as the output of 3 becomes "01", the oscillator 524 stops oscillating. That is, when the switches 526 to 529 are switched to contact b, one pulse is obtained from the oscillator 624 after writing to the counter 521, this is also supplied to the counter 521, and its contents are read as one pulse. count up. In other words, 1 is added to the value of random access memory 402. In this state, the upper 8 bits of the counter 521 are supplied to the comparison circuit 501 as they are, and the second lowest bit signal is supplied to the comparison circuit 501 as 0.

Next, when the switches 526 to 529 are respectively switched to contact c, the counter 6 is activated by the output pulse from the monostable multipipulator 525 as described above.
23 is reset, the oscillator 524 starts oscillating, and the counter 523 advances to "01", "1", and the next "11".
When this happens, the output of the AND circuit 531 becomes 1, and the oscillation of the oscillator 524 stops.

That is, after resetting the counter 523, in other words, after writing to the counter 521, three pulses are obtained from the oscillator 524, so the counter 521 is counted up by three more. In other words, 3 is added to the value of random access memory 402. In this state, the upper 7 bit signals of the counter 521 are supplied to the comparison circuit 501 as they are, and the second and third bit signals from the lower order are each set to 0. The reason for the above configuration will be described below.

Now, for example, let's write a code with a frequency slightly lower than 440 days 2.
00000000". That is, when the lower 8 bits output of the random access memory 402 is "0000000," it is assumed that a tone slightly lower than 440 days 2 has been input. Specifically, the codes "00000000" and "000" are input.
It is assumed that the intermediate point after 0000r is 440 days 2. Below A# is “00010000'', B
is "0010000'', C is "00110000''...
..., the corresponding sign increases as the pitch rises. The following table shows the relationship between the lower 8 bits of the signal obtained from the random access memory 402 and the frequency of the input signal.
The intermediate value after 1000r corresponds to the pitch name C, and “
The intermediate value between 0100000r and 0100000r corresponds to the pitch name C#, which is a semitone higher than that value.

Therefore, if the counter 521 were to obtain the output as shown in the table, the chromatic scale would be further divided into 16 parts and displayed. However, in the example of FIG. 9, the lowest bit signal is not used, and the selector switch 528,
In the switching state of contact a of 529, only the lowest bit signal is ignored, and all other bit signals except this are supplied to the comparator circuit 501, so in this state, the signals shown in M to T in the table The chromatic scale will be divided into eight parts and displayed. In addition, in the switching state of contact b of switches 528 and 529, the lower 2-bit signals are ignored, and other bit signals except these 2-bit signals are supplied to the comparison circuit 501, so in this state, U-X in the table is As shown, the chromatic scale is divided into four parts and displayed.

In the switching state of contact c of the table or switches 528 and 529, the lower three bits are ignored, so in this case, the chromatic scale is divided into two and displayed as shown in Y and Z in the table. It turns out.

By the way, as mentioned above, "00110000" and "001
If we keep choosing the pitch name C between 1000r and 8.
There is no problem in the case of split display, but in the case of 4-split display and 2-split display, the position of this pitch name C becomes uneven.

In other words, in the case of 4-split display, the output state of the group indicated by the symbol U corresponds to the pitch name C in the output state of "00110" in the upper 6 bits, but to be more precise, the position of this C is "0011", which is indicated by the center or symbol C,
Although it should be somewhere between "0001" and "0011001", it is actually between "00110000'1" and "00110001".Similarly, in the case of two-split display, the center of group Y is indicated by the symbol C2. “
It must be between 0011001r and "0011010bi".As is clear from this, in the case of 4-split display, "1" should not be added to the output of the counter 521 in the case of 8-split display, and in the case of 2-split display In this case, it is sufficient to add "3" to the output of the counter 521 in the case of 8-split display.However, according to the circuit shown in FIG. 9 described above,
The oscillator 524, the counter 523, and the AND circuit 531 make it possible to reliably achieve the above-mentioned purpose.

Moreover, this addition operation is performed because the repetition frequency of the clock signal of the oscillator 525 is selected to be a high value, such as OMHz, and the pulse duration of the monostable multipipe layers 522 and 525 is selected to be, for example, 20 seconds. This is done during the horizontal planking period and is not affected by the display. Returning to Figure 9 again, 5
01' is a comparison circuit, and a data signal read out sequentially in a horizontal period from the counter 521 described above is supplied to one input terminal of this comparison circuit 501.

Further, 502 is a counter, which is composed of, for example, 10 bits, of which the lower 4 bits are a binary counter of 16 ships, and the next 4 bits are (0000) to (1011).
) is configured as a hexadecimal counter and a binary counter whose upper two bits are in quaternary notation, respectively, and these are connected in series.

Further, 503 is a variable frequency oscillator, and this excavator 503
At this time, a clock pulse of, for example, about 7.68M is formed, which is phase-locked by the horizontal synchronization signal from the synchronization board 403.

This clock pulse is then supplied to a counter 502, and this counter 502 is preset from an initial value using a horizontal synchronizing signal. A horizontal position signal divided by Mobe is formed. Note that the lower 4 bits of this position signal are binary codes,
The next 4 bits are a hexadecimal code from (0000) to (1011), and the upper 2 bits are a binary code. This is a signal in the same format as the data signal from the random access memory 402 described above, that is, the data signal from the counter 521, where the lower 4 bits are error data, the next 4 bits are pitch name data for each semitone, and the upper 2 bits are the data signal for each semitone. It supports octave data. This position signal is transmitted to the comparator circuit 50.
1 and is compared with the data signal from the counter 521, and a signal is taken out when the data signal is larger or when they match. This signal is supplied to the adder circuit 504, where it is combined with the planking pulse, synchronization pulse, etc. from the synchronization board 403, and this composite signal is supplied to the monitor receiver 2. In this way, the color of the scanning line is changed from the scanning start position of the horizontal scanning line on the screen 10 until the data signal and the position signal match.

However, in this case, the unit of position signal is a value obtained by dividing the scan into 384, and if the count of the upper counter of the counter 502 exceeds 2, the color of the scanning line changes over the entire interval, and no more can be displayed. It's gone.

On the other hand, the data signal from the counter 521 can take on that value until the upper two bits reach 4. Therefore, for the above purpose, by presetting a predetermined value in the counter 502, the display can be shifted. That is, 505 is an up/down counter for setting a preset value, and a clock pulse of, for example, 3Hz from an oscillator 506 is applied to a gate circuit 507.
, 508 to the up input terminal and down input terminal of the counter 505, and the control signal from the display control circuit 600 arbitrarily turns on the gate circuit 507 or 508, so that the counter 505 receives a desired value. Set.

When the counter 502 is reset, this value is preset in the counter 502. Note that this counter 505
, a hexadecimal counter 552 and a quaternary counter 553 are connected in series, each forming a preset value corresponding to the counter 502.

Therefore, when the clock pulses from the oscillator 503 are combined with this preset counter 502, the data signal and position signal will match earlier by the preset value in the comparator circuit 501, and the entire display will be displayed. is shifted toward the scanning start position.

Note that when one clock pulse from the oscillator 506 is supplied to the up input terminal of the counter 505, the content of the hexadecimal counter 552 of the counter 505 increases by "IJ".

Therefore, when the contents of counter 505 are preset in counter 502, the display is shifted by one semitone toward the scanning start position. Further, when 12 clock pulses are supplied to the up input terminal of the counter 505, the counter 506
The contents of the quaternary counter are incremented by "1" and the display is shifted by one octave toward the scanning start position. Furthermore, in this circuit, the oscillation frequency of the oscillator 503 is varied by a signal from the display control circuit 600. By doing this, for example, when the frequency of the oscillator 503 becomes high, the counter 502 counts faster, and the time until the signals match in the comparison circuit 501 becomes shorter.

On the other hand, since the scanning speed of the horizontal scanning line is constant,
The part where the scanning line changes color on the screen 10 becomes shorter,
As a result, the display content is reduced, and the display range can be expanded by displaying two or more octaves, for example. Similarly, by lowering the frequency of the oscillator 503, the display is enlarged and minute changes can be made clearer. Further below,
A configuration for displaying blue names "A, B, C..." and floor names "C, SI, Mi..." on the screen 10 of the receiver 2 will be described.

In this case, note names and scale names are displayed in two rows over 16 horizontal scanning periods at the top of the screen.
Furthermore, pitch names correspond to frequencies, and for example, when the display is shifted as described above, the letters are also shifted at the same time, whereas scale names can be freely moved by transposition, modulation, etc. Therefore, in this circuit, the counter 512
and an up/down counter 513 are provided.

Further, gate circuits 514 and 51 controlled by the display control circuit 60 in the same manner as the gate circuits 507 and 508 described above.
5 is provided, the clock pulse from the oscillator 506 is taken out through gate circuits 514 and 515, and the taken out clock pulse and gate circuits 507 and 50 are provided.
The clock pulse from 8 is supplied to counter 513 through OR circuits 516 and 517, and this counter 51
3 is preset in the counter 512. However, the lower 4 bits of the counter 612 are preset to "0000". Therefore,
In this counter 513, gate circuits 507, 50
8 is made conductive and the display data is shifted, this counter 513 also counts, and the preset value for the counter 512 is changed, and when the gate circuits 514 and 515 are made conductive, In this case, only the counter 513 counts independently, and only the preset value for the counter 512 is changed. Note that the counters 5 1 3 are hexadecimal counters, and a preset value is supplied to the hexadecimal counter 532 of the counter 512.
will be provided. The contents of the hexadecimal counter of counter 512 and the contents of the hexadecimal counter of counter 502 are selected by selection circuit 509 and supplied to a character selection terminal of character generator 510. This character generator 510 configures characters with dots in a matrix of, for example, 8 rows and 8 columns, and depending on the signal supplied to the character selection terminal, the pitch name "A, B, C..." or the scale name. A character signal of "do, shi, mi..." is formed, and this character signal is generated by the lower three bits 0 to 7 of the horizontal period count output from the counter 404.
Each horizontal scan is repeated and taken out in order. In this circuit, when the same signal as the 4 bits of note name data when the sound "A" is recorded in the random access memory 402 from the counter 502, the character generator 51 outputs "A". The character signals of "B", "C", etc. are taken out below. Furthermore, in this circuit, the character signals are binary decimal signals for both note names and scale names.

Therefore, at the same time as the selection circuit 509 is switched, the character generator 510 is controlled, and the counter 50
When the signal from the counter 512 is supplied, a character signal of the pitch name is generated, and when the signal from the counter 512 is supplied, a character signal of the scale name is generated. The control of the character generator 510 and the switching of the selection circuit 509 are performed by the horizontal period counter 404.
That is, the contents of the counter 404 are supplied to the decoder 518, and the decoded output is supplied to the selection circuit 509 and the character generator 510, and for the first eight horizontal scanning periods, the contents of the counter 502 are supplied to the character generator. The contents of the counter 512 are sent to the character generator 510 during the 8 horizontal scanning periods from 9 to 16 to form the character signal of the pitch name. .

Note that, from this character signal, one horizontal scan of each character is extracted in parallel. Therefore, this parallel signal is sent to the decoder 519.
The shift register 5 is controlled by the pulse signal for each semitone from
11, and this shift register 511 is loaded into the oscillator 5.
It is driven by the horizontal position signal from 03 so that the signals are taken out serially in the horizontal scanning direction. Furthermore, 520 is a gate circuit which is rendered conductive only during the first 16 horizontal scanning periods of the screen 10 by a control signal from the decoder 518.

A signal from the shift register 511 is then supplied to the adder circuit 504 through this gate circuit 520. In this way, note names and scale names are displayed in two lines within the range of one horizontal scanning line at the top of the screen 10, but according to this circuit, the gate circuits 507 and 508 are in the conductive state. When the display of data on the screen 10 is shifted, the letters of the pitch name and scale name are also shifted at the same time.

Furthermore, when the gate circuits 514 and 515 are set to the conductive state, only the characters of the scale name move, and for example, when transposition, modulation, etc. are performed, the scale name can be displayed in accordance with the tone. can.

Further, a pulse signal for each semitone from the decoder 519 is supplied to the adding circuit 604.

Therefore, a vertical line is formed on the screen 10 to indicate the position of each semitone. Furthermore, when the oscillation frequency of the oscillator 503 is changed as described above, the counting speed of the counter 502 and the counting speed of the counter 512 can also be changed. The letters and vertical lines between semitones are also enlarged or reduced at the same time.

In this way, in the device of the present invention, an interval table with vertical lines attached at semitone intervals is displayed on the television screen 10 along with letters of pitch names and scale names, and the intervals of the user's voice are shown here in the Hayabusa style. If the pitch is off, you can see it at a glance, and even if the user changes the pitch and pronounces it at the correct pitch, the length of the birch graph will change according to the change in pitch. This makes it very easy to vocalize at the correct pitch, and it has a noticeable effect when used in music education.

Furthermore, according to the present invention, a tracking filter is used as a filter circuit when extracting the fundamental frequency component, and the cutoff frequency is changed using the output signal as a control signal, so that the fundamental frequency component is always at a constant level. Furthermore, the output signal of the filter is compared with the input signal, and the winding crossover point of the input signal immediately after the wide crossover point of the output signal is extracted, so that the phase shift between the input signal and the output signal can be It is possible to extract the exact fundamental wave.

In addition, when detecting the frequency value, the time for 2n cycles of the input signal is detected, and the number of cycles (2n) of the input signal required for detection is measured, and from this number of cycles, the input signal is In addition to detecting which octave it belongs to, we also detect which pitch within that octave from the above-mentioned time, so the octave data and pitch data of the input signal are extracted separately, making subsequent processing easier. Become.

In addition, the storage circuit repeatedly counts the horizontal synchronization signal and uses it as an address signal, for example, 2
Since the oscillation signals of the 0Hz oscillator are counted and writing is performed when they match, data is written on the screen in order starting from the upper scanning line at intervals of, for example, i'2, and then Since the oscillation frequency of this oscillator can be changed arbitrarily, the data writing interval can be changed arbitrarily. Furthermore, a gate circuit is provided on the output side of the oscillator, and this gate circuit is in a non-conducting state when there is no input signal.
When there is no input signal, the write address does not change, and the addresses of the random access memory are not wasted.

Furthermore, since this control signal is taken out through a monostable multipipulator, when the input signal disappears, "0" data is recorded for a predetermined period, making the break in the input signal clear.

Furthermore, according to the present invention, pitches are displayed, and characters for pitch names and scale names are displayed, and when the display range is moved, the display of these characters also moves at the same time, making it easier to read the display. becomes easier. Furthermore, since only the letters of the scale name can be moved separately, it is possible to cope with modulation or transposition.

Furthermore, since the displayed content can be enlarged or reduced, it is convenient for reading a wider range of display or minute changes. Furthermore, according to the present invention, by switching the switches 526 to 529, it is possible to select an 8-split display, a 4-split display, or a 2-split display within the chromatic scale. Therefore, for example, when practicing vocalization, beginners can roughly understand the pitch with the 2-split display. By knowing this, you can master the basics, and for professionals, you can continue practicing by using the 8-split display to understand fine changes in pitch. It has the characteristic that it can be used according to the purpose.

In the above description, the contents of the random access memory 402 are stored in the counter 521, and then the oscillator 524, the counter 523, etc. are used to count up according to the precision switching, but the synchronization shown in FIG. The oscillation frequency of the oscillator 201 as a counter may be changed according to the precision switching.

That is, when displaying a chromatic scale divided into four parts, the oscillator 201? The oscillation frequency is changed by the proportion of the unit pitch (2▽in-1)
)xlooo% = 0.36%, you will get a higher measurement value, and if the same machine is displayed, the frequency of the oscillation device 201 will be increased by 3 tones. good. Chi (2
▽Light - 1) xloo%3 If you raise the length by 1.089%, you will get a higher measurement value. In this case, the oscillator 524, counter 523, switches 526, 527, etc. shown in FIG. 9 are not required.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of pitch display according to the present invention, Fig. 2 is a system diagram showing the overall configuration, Fig. 3 is a system diagram of a filter circuit, and Figs. 4 and 6 are for explanation. Figure, 6th
The figure is a connection diagram of an example of a tracking filter, Figure 7 is a system diagram of an example of a frequency detection circuit, Figure 8 is a system diagram of an example of a storage circuit, and Figure 9 is a system diagram of an example of a video signal forming circuit. . 1 is a microphone, 100 is a filter, 200 is a frequency detection circuit, 30 is a frequency conversion circuit, 400 is a memory circuit, 50
0 is a video signal forming circuit, 600 is a control circuit, and 2 is a monitor receiver. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9

Claims (1)

[Claims] 1 a detection circuit that detects the frequency of the fundamental wave of the input signal;
A conversion circuit that converts this frequency into octave data and pitch data, a storage circuit that stores these data, a video signal formation circuit that forms a data display signal based on these data, and a data display signal that is stored in the storage circuit. and display accuracy changing means for changing the accuracy of the display when data is formed into a display signal, and displaying the pitch on the screen of a monitor receiver based on the pitch display signal. Display device.