JPS60129841A - Interruption control circuit - Google Patents

Abstract

PURPOSE:To make separately a saving area at every interruption level by providing a stack pointer, a register and a sequence circuit for controlling them. CONSTITUTION:A register 33 is provided for saving a stack pointer 31, a new stack pointer is stored from a main storage device 1 and a stack is provided newly. Thereafter, by saving an instruction counter IC3 and a status register STR4, including the stack pointer, too, the stack can be separated at every interruption level, saving positions of the registers such as the IC3, the STR4, etc. related to the interrupting operation and the registers which are not related directly to the interruption, such as a general register GR5, etc. can be discriminated, and switching of a task in an operating system, etc. is controlled easily.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an interrupt control circuit for a computer.

Conventional configurations and their problems In recent years, as the integration density of integrated circuits has increased, there has been a particularly noticeable trend towards higher functionality and higher performance of microcomputers.
Improving the performance of interrupt control circuits has also become important.

A conventional interrupt control circuit will be explained below with reference to the drawings.

FIG. 1 shows a conventional interrupt control circuit. In FIG. 1, 1 is the main memory, 2 is a stack pointer that stores addresses for accessing the stack area provided on the main memory, 3 is an instruction counter (hereinafter referred to as IC), and 4 is a status register (hereinafter referred to as IC). 5 is a general-purpose register (hereinafter referred to as GR), 6 is a sequential circuit that is activated by receiving the interrupt signal 7 and executes interrupt control, and 8 is the address signal 9 output from the sequential circuit 6 and the above. A multiplexer selects the address signal 1o output from the stack pointer 2 and generates an address signal 11 for the main memory device 1; 12 is a data bus; and 12 is a data bus connected to the IC.

Buffer the contents of STR and GR respectively at 13°14.1
5 to the main storage device 1.

The operation of the interrupt control circuit configured as described above will be explained below. First, when the interrupt signal 7 is input to the sequential circuit 6, the sequential circuit 6 controls the multiplexer 8 with the signal 16 in order to store the contents of IC3, 5TR4, and GR5 in the stack area provided on the main memory 1. and outputs the contents of stack pointer 2 to main memory 1 as an address. First, the buffer 13 is controlled by the control signal 5ELB.
, the contents of the IC are output to the data bus 12, and the value of the IC is stored in the main memory 1.

Next, the sequential circuit 6 outputs a count control signal 17 to the stack pointer 2, and decrements the value of the stack pointer by one. Stack pointer 2 with contents decremented by 1
The contents of are given to the main memory device 1 as an address signal through the multiplexer 8. At this time, the buffer 14 is selected by the control signal 5ELC, and the contents of 5TR4 are output to the data bus 12 and stored in the storage location indicated by the new contents of the stack pointer 2 on the main memory 1. Next, the sequential circuit 6 outputs the specific address of the main memory 1 from the signal 9, passes it through the multiplexer 8, and gives it to the main memory 1, and transfers the contents of the corresponding memory location on the main memory 1 to the data bus 12. Read and store in IC3. Similarly, the sequential circuit 6 outputs another specific address to the signal 9, reads the new value of STR4 from the main memory 1, and stores it in 5TII (4. In this way, the interrupt control after accepting the interrupt signal 7 is performed. The operation is performed, but before starting the interrupt handling program, the general-purpose register must be saved.Since this general-purpose register saving operation is performed by the program, a higher-level interrupt may occur during the saving operation. may occur.

FIG. 2 shows the state of the stack at this time. In the figure, 2◯ indicates a stack pointer, and 21 indicates the contents of the main memory. Figure 2 shows that an interrupt is accepted at point A, the current IC and STR are saved to the stack on the main memory, and while the general-purpose registers GHQ and GRl are being saved by the interrupt processing program, an interrupt of a higher level is accepted. This shows the state when the IC is evacuated at that time.

In this way, according to the conventional interrupt control circuit, the area for saving the IC and STR at the time of an interrupt and the area for saving registers such as general-purpose registers that are not directly related to the interrupt operation of the computer are common. The drawback is that these are mixed together and cannot be distinguished, and it is not possible to perform tasks such as task switching by manipulating the contents of the IC, STR, and general-purpose registers saved by the operating system, etc. had.

OBJECTS OF THE INVENTION In view of the above drawbacks, it is an object of the present invention to provide an interrupt control circuit that can individually create a save area for each interrupt level. And this is it.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 shows the configuration of an interrupt control circuit in an embodiment of the present invention. In FIG. 3, 1 is a main memory device, and 3 is an IC.

4 is an STR, 5 is a GR, 7 is an interrupt signal, 8 is a multiplexer, 13, 14, and 15 are buffers controlled by a sequential circuit 3o, which will be described later, and 12 is a data bus, which is the same as the configuration shown in FIG. be. 31 is a stack pointer that stores an address for accessing a stack area provided on the main memory device 1, and can store data in the data node 12'' by a storage signal 32; The output of pointer 31 is sent to signal 34
03o is a register that stores data under the control of 11il, and its output is output to the data bus 12 via the kunofa 35. 03o starts operation by accepting the interrupt signal 7, and controls the buffers 13, 14, 15, and 35. Signals 5ETA, 5ETB, 5ETC, 5ETD, stack pointer 31 count control signal 17. Storage signal 32 of stack pointer 31. This is a sequential circuit that outputs a signal 9 indicating a specific address on the main memory device 1, etc.

The operation of the interrupt control circuit configured as described above will be explained below.

When the interrupt signal 7 is received by the sequential circuit 30, the sequential circuit 30 stores the contents of the stack pointer 31 in the register 33 under the control of the signal 34.

Next, output a specific address on the main memory device 1 to the signal 9,
The main memory device 1 is accessed via the multiplexer, the contents are read out from the corresponding memory location onto the data bus 12, and stored on the stack pointer 31 under the control of the storage signal 32. From this, the sequential circuit 3° switches the multiplexer 8 to the stack pointer 31 side by the signal 16, outputs the contents of the stack pointer 31 on the address signal 11, accesses the main memory 1, and first selects the buffer 35 by the 5ELA signal. The contents of the register 33 are then written to the corresponding storage location via the data bus 12. After this write operation is completed, a count control signal 1 is sent to the stack pointer 31.
γ is output, its contents are decreased by 1, the buffer 13 is selected by the 5ELB signal, and the IC is written to the corresponding storage location in the same manner. Similar operations are repeated for STR. Thereafter, the operation of reading new values into ICa and 5TR4 from the main memory 1 is the same as in the conventional example.

When these operations are completed, the interrupt processing program is started and the general-purpose register 6 is first saved. At this time, if a new high-level interrupt is accepted, the stack on the main memory 1 will be saved. The state is shown in FIG.

In FIG. 4, 41 is a stack pointer, and 42 is the contents of the stack on the main memory 1. An interrupt occurs at point A in the figure, the stack pointer, IC, STR, etc. at that time are saved, and the interrupt processing program transfers the general-purpose registers, and GRo and GRl are saved. If a new high-level interrupt occurs at point B at this time, a new stack is created to save the IC, STR, etc. at that time, and they are saved to a storage location different from the previous save area.

As described above, according to this embodiment, the register 33 is provided to save the stack pointer 31, the new stack pointer is stored from the main memory, and after a new stack is created, the IC and STR including the stack pointer are saved. According to
Separating the stack for each interrupt level creates seven,
It becomes possible to identify the save locations of registers such as ICs and STRs related to interrupt operations and registers such as GR that are not directly related to interrupts, making it easier to control task switching in the operating system and the like.

Effects of the Invention By providing a stack pointer, a register, and a sequential circuit for controlling these, the interrupt control circuit of the present invention can create separate save areas for each interrupt level, and its practical effects are as follows. big.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional interrupt control circuit, FIG. 2 is a state diagram showing the state of the stack when an interrupt operation is performed in the conventional interrupt control circuit, and FIG. 3 is a block diagram showing a stack state in an embodiment of the present invention. A block diagram showing the interrupt control circuit,
FIG. 4 is a state diagram showing the state of the stack during interrupt operation in the same embodiment. 31...Stack pointer, 3o...Sequential circuit, 33...Register. Name of agent: Patent attorney Toshio Nakao, 1 person, 1 person, Akira 1
Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] By receiving the stack pointer, register, and interrupt signal, the contents of the stack pointer are transferred to the register, the value corresponding to the interrupt signal is transferred from main memory to the stack pointer, and the contents of the stack pointer are transferred to the stack pointer. An interrupt control circuit comprising: a sequential circuit that controls storing the contents of the register at a storage location on main memory shown in FIG.