JPS60129688A - Main clock distribution system - Google Patents

Abstract

PURPOSE:To attain to economically enhance reliability by monitoring the clock apparatus of a sub-apparatus while also enabling the periodic monitor thereof, by connecting a main apparatus and the sub-apparatus by a control bus and performing the confirmation of time setting and normality at every clock distribution at a scheduled time. CONSTITUTION:The main clock apparatus (MCLK) of a main apparatus (MDV) always displays time to a main control apparatus (MCTL) while MCTL sends out a command frame (COM), to which the information of the present time is inputted, to sub-apparatuses (SDV0-N) at every determined time through a control bus (BUS) to store the sent-out time information. Further, the sub-control apparatus (CTL) of the sub-apparatus has a function, which receives COM from MCTL to interpret the time information and performs the time setting of a sub- clock apparatus (CLK), and a function, which inputs the reading time of CLK directly before time setting to a response frame (RES) to COM to perform editing and transmits the same to the main apparatus through BUS. MCTL extracts the time information received through BUS and compares the same with the stored time information and, when difference is constant or more, outputs the same to a display apparatus.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a system for distributing time from a highly accurate master clock of a master device to clocks of slave devices.

(b), Technical background The distribution of the master clock is such that when the clocks of slave devices (hereinafter abbreviated as slave clocks) do not update their own time, the master clock sends the steps to each slave clock at the same time. The time was updated by a signal, and if it was possible to update the time by itself, the time was set by periodically sending a time adjustment signal all at once, or by manual operation.

(C), Prior Art and Problems In the conventional method of automatically updating and adjusting the time as described above, the normality of the slave clock is not confirmed and separate confirmation work is required. It was hoped that this would be done automatically, including on the standby side of the loading equipment.

(d) 9 Purpose of the invention The purpose is □.

(e) 1 Structure of the Invention The purpose of this invention is to connect a slave device having a clock device that can update its own time to a master device having a high-precision master clock through a control bus, and The current time information of the master clock is sent to each device, and the slave device that receives the time information immediately adjusts the time of the slave device's clock to match the time according to the time information, and also adjusts the time just before the adjustment. This is achieved by a master clock distribution method characterized in that time information based on time is sent back to the master device, and the master device determines the normality of the clocks of the slave devices.

(f) 4 Embodiments of the Invention An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is an explanatory diagram of the main part of the embodiment, and FIG. 2 is an information frame of the control bus. In the figure, MDV is the main unit, 5DVO,...
・N is slave device, BUS is control bus, MCTL is main control unit, CTL is control unit, MCL K is main clock unit, CLK is forward clock unit, COM is command frame, RES is response frame, FS is flag sequence, AD is the address part.

C is a control section, I is an information section, and Fe2 is a frame inspection sequence. In this embodiment, the main device MDV and the slave device 5DVO are used.

...N are connected by a control bus BUS, and the transmission control procedure is a well-known high-level data link control procedure (
(hereinafter abbreviated as HDLC) is adopted, and the main device MDV is the primary station (control station), the slave device 5DVO,...
- This is an example in which control communication is performed by a command from the primary station and a response from the secondary station in response to a command from the primary station in the normal response mode with N as the secondary station (dependent station). The command and response information frames are shown in FIG.

The main device MDV is a main controller M as a part related to the present invention.
The main clock device MCLK is highly accurate and is always connected to the main control device MCTL.
The main controller MC'I'
L edits the command frame COM containing the current time information at predetermined times as the primary station according to HD I-C, sends it to the secondary station via the control bus BUS, and inserts it into the sent command frame COM. The time information is stored, the response frame RES from the secondary station is received via the bus BUS, the time information is extracted, the time information is compared with the stored time information, and if the difference is greater than a certain value, the display device etc. (not shown).

The slave devices 5DVO, . . . , N have a forward clock device CLK and a slave control device CTL as parts related to the present invention. The slave control device CTL can read the command frame C from the main control device MCTL of the main device, which is the primary station, and is addressed to its own device.
A function that receives OM via the bus BUS, interprets the time information, and adjusts the time of the forward clock device CLK, and a response frame RES for the command frame COM contains information on the read time of the backward clock device CLK immediately before the time adjustment. It has a function to edit the data and send it to the main device, which is the primary station, via the bus BIJS.

At every predetermined time, the main controller MCTL controls all slave devices 5.
The clock distribution operation is started for DVO, . First slave 5DV
against o. A command frame COM is prepared. The information section I of the command frame CQM includes the main clock device MCL.
The current time information of K is entered in the address field AD.
DVO address information is entered, and information indicating that it is a command is entered in the control section C. Flag sequence FS indicates the beginning and end of a frame, and frame inspection sequence F [Yes]
S is for error control and is prepared according to HDLC. Once the preparation is complete, the command frame COM is immediately sent to the control bus BLIS.

The slave devices SDV and 9 slave control devices CTL receive the command frame COM, identify it as a command for their own device using the address section AD and the control section C, receive this command, and use the time information in the information section Immediately adjust the time of the slave clock device CLK, and in order to make a response, put the previous time of the previous clock device CLK in the information field ■ and enter the address information of the slave device 5DVO, which is the own device, in the address field AD. Information indicating that the response ends in one frame is put in the control unit C, and the flag sequence FS and frame check sequence FC3 prepare a response frame RES in the same manner as in the case of the command frame 00M described above and send it to the control bus BUS. do.

The main control device MCTL of the main device MDV immediately receives the response frame RES from the slave device 5DVO, and the information section
The time information is extracted and compared with the time stored at the time of sending the command, and the normality of the forward clock device CLK of the slave device 5DVO is determined based on the difference.If it is above a certain value, the display device, etc. (not shown) to take maintenance action.

When the clock distribution to the slave device 5DVO is completed by the above operation, the main controller MCTL of the main device MDV
Start clock distribution to I. The master controller MCTL sends a command containing the current time to the slave device 5DV1 in the same way as for the slave device 5DVO, and in response to this command, the slave controller CTL of the slave device 5DVI adjusts the time of the forward clock device CLK. The main controller MCTL receives this response and determines the normality of the forward clock device CLK. below,
Sequential slave devices 5DV2, 3 . . . . By repeating the same operation to N, the normality of the forward clock device CLK of all slave devices is confirmed and time distribution is performed. The above-mentioned clock distribution operation is performed for all the above-mentioned slave devices at regular time intervals.

Modifications of the above embodiment will be shown below.

The transmission control procedure is not limited to HDLC, but is compatible with the HAS used.The main device can specify and command each slave device individually, and the slave device that receives the command immediately sends a response to the master device. Anything that can be returned can be applied.

In the embodiment described above, the clock was periodically distributed to all the slave devices, but it is also possible to distribute the clock cyclically to each slave device at fixed time intervals. It is also possible to combine with commands and responses other than clock distribution; for example, by adding information indicating the state to be monitored by the follower device to the response of clock distribution, it can also be used for monitoring conditions other than clocks. The response frame RES will be long in this case.

(gl. Effects of the Invention According to the present invention, it is not only possible to monitor the clock device of the slave device by setting the time and checking the normality every time the clock is distributed at regular intervals, but also to monitor the clock device of the slave device at regular intervals. It is also possible to do this at different times, and reliability can be improved economically.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the main part of the embodiment, and FIG. 2 is an information frame of the control bus. In the figure, MDV...main device, 5DVO,...N...slave device, BUS...control bus, MCTL...main control unit, CTL...control unit, MCLK...main Clock device, CLK... Time clock device. COM...command frame, RES...response frame, FS...flag sequence, AD...
Address section, C...control section, ■...information section, Fe2
...frame inspection sequence.

Claims (1)

[Claims] A slave device that has a clock device that can update its own time and a main device that has a high-precision master clock are connected via a control bus, and the master device informs each slave device about the current state of the master clock at regular intervals. The slave device that receives the time information immediately adjusts the time of the slave device's clock to match the time according to the time information, and returns the time information according to the time immediately before adjustment to the main device, A master clock distribution method characterized in that the master device determines the normality of the clock of the slave device.