JPS60125573A - Timing pulse generator - Google Patents

Abstract

PURPOSE:To improve the efficiency of IC test by giving an initial value, a variation, and timing information of the number of variances to generate a timing signal corresponding to the number of variances and testing the access time of a memory IC or the like in a high speed. CONSTITUTION:When a phase control circuit 21 is started by a timing switching signal 12, a register 26 is reset, and a multiplexer 24 selects the output of an initial value register 23, and therefore, an ALU (arithmetic logic unit) 25 operates the value in the initial value register 23 and the value in the register 26 in accordance with contents of an ALU register 30. This operation result is stored in the register 26. Meanwhile, the multiplexer 24 selects the value in a variation register 27 by the circuit 21. Therefore, the ALU25 adds the value in the register 23 and the value in the register 27, and the result is stored in the register 26. The number of generated phase signals 14 is determined by the value in a variance number register 28. Consequently, the initial value, the variation, and the number of variances are given to generate the timing signal correspolding to the number of variances.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a timing pulse generator, and particularly to a timing pulse generator suitable for testing and inspecting semiconductor devices.

[Background of the invention]

Timing pulse generators for IC testers generally consist of a rate generator (or period generator) that determines the test period, and a plurality of 7-axis generators that generate signals at arbitrary phases with respect to the test period. generator (still called a delay generator).

An example of a conventional timing pulse generator will be explained using the block diagram of FIG. Here, the explanation will be given assuming that there is only one phase generator, but this does not limit the explanation of the timing pulse generator.

The test cycle signal 112 and the phase signal 14 perform real-time control of the timing by an external timing selection signal 10 in order to change the timing in real time.

The timing selection signal 10 is taken into the timing register 7 by the test period signal 11, and the late memory 6 in which test period information is written and the phase memory 16 in which phase signal information is written are accessed.
Test period information and phase signal information are read. According to the information, the timing pulse generator outputs a test period signal 11° phase signal 14.

Rate generator 9, which is the part that creates the test cycle
consists of a rate counter 2 that determines the test cycle based on the oscillation cycle of the oscillator 1, that is, an integer multiple of the basic clock, and a variable delay circuit that delays the output of the rate counter 2 in order to improve the resolution of the test cycle beyond the basic tarok cycle. 3
Since the resolution has been increased using the variable delay circuit 3, the delay adder 5 performs an addition operation of the delay amount of the variable delay circuit 3 set in the previous test cycle and a set value that is less than the cycle of the basic clock of the current test cycle. The oscillator 1 supplies a basic clock having the same phase as the test periodic signal 11 to the rate register 4 that holds the calculation results and the phase generator 15 that creates the phase signal 14.
and a variable delay circuit 8 that delays the output of the circuit.

The phase generator 15A uses a phase counter 18 to count the basic clock, that is, the phase clock 13 synchronized with the test periodic signal 11, and generates a coincidence output at the time when it coincides with the value of the phase register 17. In this state, the setting resolution of the phase generator 15A is determined by the period of the phase clock 13, that is, the basic period of the oscillator 1, so the resolution is improved by the variable delay circuit 19 and the phase signal 14 is output.

That is, the phase generator 15 has a function of outputting an arbitrarily set phase pulse once during one test period according to timing information written in the phase memory 16 in advance.

On the other hand, memory ICs are the test targets of IC testers.

When testing logic ICs, there is a selection test to determine whether or not they can operate at a frequency defined by the standard or a delay time from a clock. This means that if the test target is a memory IC, it is classified into grades based on access time, and if it is a logic IC, it is classified by operating frequency. Also, at the development stage of such ICs and LSIs,
It is required to accurately measure the delay time of the element.

When testing a device under test by measuring time in this way, the IC tester compares the expected value data with the timing of the judgment strobe signal to determine whether it is good or bad. Therefore, in order to accurately measure time, change the timing of the strobe signal every test cycle, detect the point where the judgment result changes from fail to pass, or from pass to fail, and measure the time. It is necessary to do this.

The timing of this strobe signal is created by a timing generator, and the strobe signal timing settings must be written in advance into a high-speed memory within the timing pulse generator. However, high-speed memory is expensive and
Since large-capacity high-speed memory has not been realized, conventional -I
With the C tester, the number of levels that can be set for timing is 16.
It is about the level. Therefore, in order to perform accurate time measurement, the CPU must write the 16-level timing settings to the high-speed memory, start up the tester's high-speed section, and compare the judgments using the 16-level timing settings. The CPU repeatedly writes the timing setting data to the high-speed memory.
I tried to make accurate time measurements. Therefore, the time during which the tester's high-speed section is operating, that is, the IC under test, is measured.

The time taken by the host CPU to rewrite the setting data of the tester's high-speed section is longer than the time taken by the IC tester, which significantly reduces the throughput of the IC tester.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to provide a timing pulse generator that can generate a wide range of timing signals according to various desired timing information for testing and inspection of semiconductor devices. It is about providing.

[Summary of the invention]

A timing pulse generator according to the present invention counts phase clocks synchronized with a test synchronization signal sent to the outside from a rate generator, and according to a timing switching signal based on a timing selection signal given from the outside and the test synchronization signal, In a timing pulse generator equipped with a phase generator that delays the above counting result by a desired value and sends out a phase signal based on the delay, the initial value, change width, and number of changes of the phase signal to be generated and sent are stored. means for calculating the timing information of the phase signal from the stored value of the initial value/change width; and means for calculating the number of generation and transmission of the phase signals based on the stored value of the change width and the calculation result of the timing information. The phase generator is provided with means for controlling according to the phase change.

In short, in order to increase the number of timing settings without increasing the capacity of the high-speed memory within the timing pulse generator, the initial value of the timing settings.

A memory or a register for storing the change width and the number of changes is provided, and an arithmetic means for calculating the timing setting value from this value is provided, and timing signals whose phases differ by the change width from the initial value are generated by the number of changes. It is intended to be controlled.

[Embodiments of the invention]

FIG. 2 is a phase generator block diagram of an embodiment of the timing pulse generator according to the present invention, and relates to a phase generator that creates a phase signal that increases or decreases the timing setting value by a desired time every test cycle. This is explained below. The late generator is assumed to be the same as that shown in FIG. 1 described above.

Here, 10 is a timing selection signal, 11 is a test period signal, 12 is a timing switching signal, 13 is a phase clock, 14 is a phase signal, 15 is a phase generator,
16 is a phase memory, 17 is a phase register, 18
is a phase counter, 19 is a variable delay circuit, 20 is a multiplexer, 21 is a phase control circuit, 22 is an R8 flip-flop, 23 is an initial value register, 24 is a multiplexer, 25 is an arithmetic unit (ALU), 26 is a register, 27 is a Change width register, 28 is change number register, 2
9 is a change number counter, and 30 is an ALU register.

The phase generator 15 outputs a phase signal 14 at a time set by a phase counter 18 that counts the phase clock 13 synchronized with the test periodic signal 11 and a variable delay circuit 19 that delays its output.

The setting value is the phase register 17 or register 26.
is selected by multiplexer 20 and loaded into phase counter 18 and variable delay circuit 19. Here, if the multiplexer 20 selects the 7 aids register 17, like the conventional timing pulse generator,
A phase signal is output according to timing information stored in the phase memory 16 in advance.

Next, a case will be described in which the multiplexer 20 selects the output of the register 26 via the phase control circuit 21JS flip-flop 22 in response to the timing switching signal 12.

The phase control circuit 21 is controlled by the timing switching signal 12.
When activated, the register 26 is reset and the multiplexer 24 selects the output of the initial value register 23, so the ALU 25 adds or subtracts the value of the initial value register 23 and the value of the register 26 according to the ALU register 30. Do this. Here, for convenience of explanation, it is assumed that the ALU 25 performs an addition operation. The result of this calculation is stored in the register 26 using the phase signal 14. multiplexer 20
Since the output of the register 26 is selected, the phase counter 18 . The variable delay circuit 19 includes an initial value register 23.
is set, and a phase signal 14 delayed by the value of the initial value register 23 with respect to the test cycle signal 11 is output.

On the other hand, the multiplexer 24 selects the value of the change width register 27 by the phase control circuit 21. Therefore, the ALU 25 adds the value of the initial value register 23 stored in the register 26 and the value of the change width register 27. The calculation result is stored in the register 26,
The value is phase counter 18. Since the phase signal 14 is loaded into the variable delay circuit 19, the test period signal 11
It is output after the time when the values in the initial value register 23 and the change width register 27 are added. Thereafter, this operation is repeated, so if the value of the initial value register 23 and the value of the Td1 change width register are Δt, the phase signal 14 changes in each test cycle, as shown in the timing chart of FIG. The signal becomes a signal whose delay amount increases by Δt.

Here, the number of generated phase signals 14 is determined by the value of the change number register 28. That is, the change number register 28
The value of is loaded into the change number counter 29KO-, and after counting the phase signal 14 by the loaded value, the RS flip-flop 22 is reset. Accordingly, the multiplexer 20 selects the phase register 10, so that the mode in which the phase signal 14 changes with a resolution of Δ returns to the normal mode.

When the ALU 25 performs subtraction using the ALU register 30, the phase signal 14 becomes a signal whose delay amount decreases by Δt in each test period, as shown in the timing chart of FIG.

As described above, according to this embodiment, the initial value and the variation range.

By providing the number of changes, it is possible to generate a phase signal whose number of changes differs from the initial value by the amount of change.

〔Effect of the invention〕

As described above in detail, according to the present invention, by providing timing information of the initial value, the width of change, and the number of changes, it is possible to generate a timing signal corresponding to the number of changes. tests, logic IC switching tests, and skew measurements of the IC tester itself can be performed at high speed without rewriting the small capacity high-speed memory in which timing information is written, resulting in a noticeable improvement in the efficiency of IC tests. Effects can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of a conventional timing pulse generator. FIG. 2 is a block diagram of a phase generator of an example of a timing pulse generator according to the present invention. This is the timing chart. 10...Timing selection signal, 11...Test cycle signal, 12...Timing switching signal, 13...Phase clock, 14...Phase signal, 15...Phase generator, 16...Flash AIDS Memory Mi 17.
... Phase register, 18... Phase counter,
19... Variable delay circuit, 20... Multiplexer,
21... Phase control circuit, 22... RS flip-flop, 23... Initial value register, 24... Multiplexer, 25... ALU, 26... Register,
27... Change width register, 28... Change number register, 29... Change number Figure 1 Figure 2

Claims (1)

[Claims] 1. Count the phase clocks synchronized with the test synchronization signal sent externally from the rate generator, and delay the counting result by a desired value according to the timing switching signal based on the timing selection signal given from the outside and the test synchronization signal. A timing pulse generator equipped with a face generator that transmits a phase signal based on the timing pulse generator includes a means for storing an initial value, a width of change, and a number of changes of a phase signal to be generated and transmitted; means for calculating the timing information of the phase signal from the stored value of the variation width; and means for controlling the number of generation and transmission of the phase signals according to the stored value of the variation width and the calculation result of the timing information. , a timing pulse generator configured to be installed in a phase generator.