JPS60123139A - Ciphering device - Google Patents

Abstract

PURPOSE:To attain error correction and ciphering at the same time by replacing two rows and two columns of a generation matrix for an optional number of times in applying the matrix operation between data information and the generation matrix of an error correction code. CONSTITUTION:Data information 30 is fed to a matrix operating circuit 32, where the data information is subject to matrix operation by a matrix from a generation matrix memory 33 of the error correction code and the result is transmitted to a transmission line 13. In the process, two optional rows (a) and two optional columns (b) of the generation matrix G are replaced for an optional number of times under the control of a key control circuit 35. The information as to the key is informed secretly to a recipient from a terminal 36. On the other hand, a check matrix 38 and a bit array converting circuit 41 are controlled by a cipher decoding control circuit 40 based on the key information at the reception side. Furthermore, the signal is outputted from an output terminal 42 as correct information via an error correction circuit 39 and the circuit 41.

Description

Detailed Description of the Invention (Technical Field) The present invention provides a cryptographic system that realizes error correction encoding and encryption using a single encoding, thereby improving transmission efficiency and making equipment more compact and economical. related to conversion equipment.

(Prior Art) Conventionally, encryption and error correction encoding were considered to belong to different technical fields, and each required separate devices.

FIG. 1 shows a conventional embodiment. Data signal to be sent 10
is encrypted by an encrypting device 11, and then a necessary number of check digits having an error detection function are added in an error correction encoding device 12, and then sent to a transmission line 13. For errors received on the transmission path 13, the error correction/decoding device 14 detects the crit state of the check digit and corrects the error, and then the encryption/decoding device 15 decrypts the encryption and restores the original data. The data is passed to the recipient as data IO.

As described above, extra additional digits and processing are required at each stage of error correction and encryption, resulting in a decrease in transmission efficiency and an increase in the size of the device.

(Objective of the Invention) An object of the present invention is to provide an encryption device that eliminates these drawbacks and performs error correction and encryption at the same time.

(Configuration of the Invention) The configuration of the present invention includes a memory that stores a generation matrix of a block code having an error correction encoding function for data information, and means for performing matrix operations on the data information and the generation matrix of the memory. and means for permuting bit arrays of input and output data information of the means for performing matrix operations or exchanging two rows and two columns of the rows and columns of the generation matrix an arbitrary number of times, This is an encryption device characterized by using permutation or exchange of generation matrices as an encryption key.

(Example) Hereinafter, embodiments will be described in detail with reference to the drawings.

FIG. 2 is a system diagram showing one example of application of the present invention.

No. 2 is an encryption device that simultaneously performs error correction encoding, and No. 2 is a decoding device that simultaneously performs error correction decoding. Since the encryption device 20 is used to provide the encryption function as well as the error correction function, it can be directly connected to the transmission path 13, and only one device is required. Similarly, regarding decoding, both error correction and encrypted decoding can be achieved with one device.

FIG. 3 is a block diagram of the first embodiment showing the internal configurations of an encryption device 20 that simultaneously performs error correction and a decryption device 2 that simultaneously performs error correction and decoding.

30 is data information to be sent, 3 is a terminal, 32 is a matrix calculation circuit, 33 is a generation matrix memory, 34 is an output terminal, 35
is a key control circuit, 36 is an output terminal of the key control circuit 35, 37
38 is a syndrome forming circuit, 38 is a parity check matrix, 39 is an error correction circuit, 4o is an encryption/decoding control circuit, 41 is a bit array conversion circuit, and 42 is an output terminal.

The data information i3θ to be sent is added to the matrix operation circuit 32 from the terminal 31 as binary data consisting of bits in the J block (the same applies to k-ary numbers, but for convenience of explanation, they are treated as binary numbers), and is added to the matrix calculation circuit 32 to generate a generation matrix. It is assumed that the generator matrix memory 33 contains a generator matrix G of an arbitrary error correction code, which is subjected to a matrix operation with a matrix in the memory 33 . It is assumed that the pair a of any two rows and the pair of any two columns of this generation matrix are exchanged an arbitrary number of times under the control of the key control circuit 35. Swapping the rows and columns of this generator matrix is used as the encryption key. Information about the key is secretly reported to the recipient in advance from the terminal 36 through the same line or another line, and the recipient knows what rows and columns are being exchanged.

On the receiving side, the n-bit reception program ν that has suffered υ errors due to noise etc. is received, and is subjected to matrix calculations with the parity check matrix old in the nondrome forming circuit 37, resulting in syndrome 1J=
W・I)-IT is detected and the undrom forming circuit 37
The received block V input to the error correction circuit 39 by bypassing
Errors will be corrected. Here, the relationship between the parity check matrix IH and the generation matrix G is GIHT=.

It is determined that In addition, a check matrix (If-
() s is added to s so as not to impede error correction.

Since the row conversion a added to the generation matrix 6 corresponds to converting the bit arrangement within the information data block consisting of bits, on the decoding side, after error correction, the bit arrangement conversion circuit 4 , bit array conversion a corresponding to row conversion on the transmitting side is performed by a signal from the encryption/decryption control circuit 4o.
The correct information is output from the output terminal 42.

As explained in the above embodiments, error correction encoding and cryptographic encoding can be integrally encoded. We have shown a method in which the key to encryption is to exchange rows and columns, both in terms of transmission efficiency and economy, since the increase in data is small and the devices can be integrated. Corresponds to converting an array,
It becomes clear from the operation of the first embodiment that the column conversion corresponds to the conversion of the transmission bit arrangement.

In the second embodiment, instead of converting the rows and columns of the generator matrix, bit arrays of input and output data are performed. FIG. 4 is a block diagram of the transmitting side of the second embodiment, and the receiving side (not shown) is the same as that in FIG. 3. In FIG. 4, 43 is a first bit array conversion circuit for input data;
Reference numeral 44 indicates the output data obtained by performing error correction encoding on the output data of the first bit array conversion circuit 43, 45 indicates the second bit array conversion circuit, and the other code and decoding system circuit configurations are as shown in FIG. It is similar to the one in Figure 3. Data information Ls
The first bit array conversion circuit 43 converts the bit array of o, and the matrix calculation circuit 32 further converts the generator matrix G of the generator matrix memory 33 (without converting the rows and columns as explained in the example of ml). ), the output data 44 of error correction encoding that has been subjected to matrix operations is sent to the second bit array conversion circuit 4.
5, the bit array is converted and sent to the transmission path. In this way, as in the first embodiment, error correction encoding and cryptographically encoded sound can be integrally encoded.

(Effects of the Invention) The present invention has the advantage that since error correction encoding and cryptographic encoding can be integrally encoded, the increase in surplus bits is small and the device can be integrated. Since it is effective in terms of transmission efficiency, device miniaturization, and economicalization, it has a wide range of application to differential transmission system devices around terminals that cause serious problems in terms of peripheral noise and confidentiality. Furthermore, since similar issues exist in mobile communications, useful applications are expected.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram of a conventional embodiment, Figure 2 is a system diagram showing one application example of the present invention, and Figures 3 and 4 are internal configurations of the first and second embodiments. It is a block diagram. 30... Data information, 32... Matrix calculation circuit, 33
...Generation matrix memory, 35...Key control circuit, 37.
...Ndrome formation circuit, 38...Check matrix, 39
...Error correction circuit, 40...Encryption/decryption control circuit, 4
of. 43.45...Bit array conversion circuit. Patent Applicant: Oki Electric Industry Co., Ltd. Case Indication 1982 Patent Application No. 230598 2 Title of Invention Encryption Device 3 Relationship with the person making the amendment case Patent applicant's office (105) Minato-ku, Tokyo Toranomon 1-7-12
Address (105) 1-7-1 Toranomon, Minato-ku, Tokyo
No. 2 No. 6, Contents of amendment (1) "Error correction at the same time" on page 4, line 5 of the specification
The statement has been corrected to read, "Error correction encoding is performed at the same time." (2) In the sixth line of the same page, the phrase "decoding device that simultaneously performs error correction decoding" is corrected to read "encryption and decoding device that simultaneously performs error correction decoding." (3) On the 6th line of the same page, the phrase “(even in k-ary numbers”) was replaced with “(
Correct it by saying, "Even in arbitrary decimal numbers." (4) In the second line of page 5 of the same book, the statement "column 1, row n" is corrected to "column n, row k." (5) On the 6th line of the same page, replace the text "is detected," with "
is calculated and corrected. (6) Correct the drawings “Figure 1” and “Figure 4” as shown in the attached sheet.

Claims (1)

[Claims] a memory that stores a generation matrix of a block code having an error correction encoding function for data information; a means for performing a matrix operation between the data information and the generation matrix of the memory; It has means for permuting the bit array of the output data information or exchanging each of the rows and columns of the generator matrix an arbitrary number of times, and the permutation of the bit array or the exchange of the generator matrix is performed using an encryption key. An encryption device characterized by: