JPS60120450A - Controlling system of buffer memory - Google Patents

Abstract

PURPOSE:To shorten memory access time, by suppressing the movement of one block and sending out only necessary data to a CPU through a bypass when block crossing occurs. CONSTITUTION:Since a data block crosses the block boundary in a buffer memory if a carry signal is detected when the lowest order bit and length of an address set in a buffer memory address register 1 are added to each other at a comparator C5, the carry signal of the comparator 5 is used to control the input gate G of a data section 4 so that the writing operation of the data section 4 can be inhibited and only data required by a CPU can be sent directly to the CPU through a bypass route BPR, when the data block does not exist in a buffer memory but is transferred from a main storage device.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a control method when moving data from a main storage device to a buffer memory in a data processing device having a buffer memory.

(bl Technology background) As data processing devices have become larger and faster in recent years, it has become necessary to speed up the access time to the main storage device.
One way to do this is to place a buffer memory between the main memory and the central processing unit that is faster than the main memory but has a smaller storage capacity. access buffer memory,
If the necessary data does not exist there, transfer the data from main memory to buffer memory (called move-in)
There is a known method for shortening the time required to access the main storage device, which appears to be the main storage device seen from the central processing unit, by controlling the buffer memory to be accessed after the central processing unit has accessed the main storage device.

This buffer memory is composed of a plurality of entries, and consecutive data is moved in and registered in units of blocks between predetermined address boundaries in each entry.

When performing the above move-in, the first transfer unit (for example, 8 bytes) of data required by the central processing unit is usually used.
A method has been adopted to speed up the access time from the perspective of the central processing unit by bypassing the byte and sending it directly to the central processing unit.

On the other hand, if the access request area from the central processing unit to the buffer memory does not exceed the address boundary, the required data is registered on the entry (block) on the buffer memory with a single move-in operation. It can be performed.

However, if the access request area for the buffer memory from the central processing unit exceeds the above address boundary (
There is no established method for buffer memory control (this is called block crossing), and there has been a desire to establish an effective control method.

(C) Prior Art and Problems In a data processing device having a buffer memory, if the access request area to the buffer memory from the central processing unit exceeds the boundary of one block constituting the buffer memory (i.e., the block In the conventional method, the above access request is divided into two accesses for the blocks before and after the block boundary in the buffer memory.
It was processed by performing multiple move-ins.

Therefore, the two blocks before and after the block boundary described above are moved in, and data other than the access area required by the central processing unit is also moved in and replaced, so the central processing unit is not originally required. There was a problem in that access time was delayed due to moving in invalid data.

fd+ OBJECTS OF THE INVENTION In view of the above-mentioned conventional drawbacks, the present invention provides a method that does not slow down the access time for an access request from a central processing unit to a buffer memory even when the request causes block crossing. The purpose is to provide the following.

According to the present invention, in a data processing device having a buffer memory, when the buffer memory is accessed, necessary data is not registered and the address thereof is This is achieved by providing a control method that only bypasses the transferred data from the main memory and does not move it into the buffer memory when the data crosses a block boundary, reducing the access time for the data. In addition to being able to shorten the buffer memory, by suppressing the move-in of invalid data, subsequent buffer memory access is possible, which has the advantage of improving the efficiency of access to the buffer memory.

[fl Embodiments of the Invention To summarize the gist of the present invention, the present invention provides a data processing device having a buffer memory, which accesses the buffer memory and, when necessary data does not exist, moves the data from the main memory. together with the first transfer unit of data required by the central processing unit (e.g.
By focusing on the fact that there is a function to bypass data (8 bytes), when the block crossing occurs, the move-in of the block containing the data is suppressed, and only the necessary data is bypassed to the central processing unit.

Embodiments of the present invention will be described in detail below with reference to the drawings.

Fig. 1 shows a block diagram of an embodiment of the present invention, and Fig. 2 shows a time chart of the P/7 memory access operation when the present invention is implemented, comparing it with the conventional method. This is a diagram shown in .

In FIG. 1, ] is a buffer memory address register (hereinafter referred to as BSAR), and 2 is a buffer memory write data register (hereinafter referred to as BSWDI?).

3 is a tag section (TAG), which contains the data section (DATA) of this buffer memory, the address (upper bit) of the data stored in each entry in 4, and whether the data stored in that entry is valid or invalid. It holds a value (V bit) that indicates the

When this v bit is valid and the upper bits of the address of BSAR1 and the address stored in the tag section (TAG") 3 match in the comparator (C) 5, the desired data is stored in this buffer memory. 4 is a data section (DATA), and each entry stores data starting at a certain block (generally 32 to 64 bytes) boundary. 6 is a select circuit, 7 is the lower pinpoint of BSAR1 (64 high [・
/ block, the lower 6 bits) and the data width (hereinafter referred to as length) are added, and a block crossing is detected using a carry signal. G is a move-in inhibiting gate necessary to implement the present invention.

Now, in order to access the buffer memory from the central processing unit (not shown), when the memory address of the data block is set in BSAR1, the tag section (TAG)
3 and data section (DATA) 4 are accessed, and the BSA
The block indicated by the contents of R1 is the data section (DATA) 4
The comparator (C) 5 checks whether or not it exists.

If a match signal C is obtained by the comparison operation and the V bit is valid (that is, a requestable data block is read from the data section (DATA) 4 and sent to the central processing unit through the select circuit 6. Sent out.

However, if a match signal is not obtained, or even if a match signal is obtained, the data that can be claimed as bit-O is not present in the data section (DATA) 4, so the main storage device (Fig. (not shown), the data of the block will be moved into this buffer memory.

Specifically, the data of the block from the main storage device is temporarily buffered in BSWDR2, and is moved through the gate circuit G to the entry at the address indicated by BSAR1, and is also transferred to the corresponding pin in the tag section (TAG) 3. It operates to set I to "1". Of the data blocks moved in at this time, the first transfer unit byte required by the central processing unit is transferred to the bypass route BP.
R is sent to the central processing unit through the select circuit 6.

The above is a general access operation to the buffer memory, but the operation related to the present invention will be explained below.

First, the adder 7 checks whether the data block requested by the central processing unit has caused block crossing. Specifically, the least significant bit of the address set in BSAR1 and the length are added by comparator (C) 5, and when a carry signal is detected, the data block crosses the block boundary in the buffer memory. Therefore, if the data block does not exist in the buffer memory and is transferred from the main memory, the carry signal of the comparator (C) 5 is in,
Data section (DATA) Control input gate G of 4,
The write operation to the data portion (DATA) 4 is suppressed, and control is performed so that only the data required by the central processing unit is sent directly to the central processing unit through the bypass route 1-BPR described above.

FIG. 2 is a time chart showing the operation when the buffer memory is accessed; (a) shows the case of the conventional system, and (b) shows the case of implementing the present invention.

In the drawing, ■ indicates the process of detecting that the data block is not registered in the buffer memory, ■ indicates access to the main memory for move-in,
■ indicates data transfer from the main memory (D: indicates data transfer unit), and ■ indicates bypass operation.

The data required by the central processing unit is the last 1 transfer unit byte (for example, 8
Bytes) to several transfer units hide.

As is clear from the figure, in (b), when it is detected that the data block is not registered in the buffer memory, the main memory is accessed and three of the blocks that are not required by the central processing unit are transferred. unit byte (e.g.
After moving in 8 bytes) x 3 = 24 bytes), the 1 transfer unit byte (8 bytes) required by the last central processing unit is bypassed, and moving in the 3 transfer unit bytes described above is a completely wasteful operation. It has become.

(B) is the operation when the present invention is implemented, and as is clear from the figure, there is no move-in operation at all, and only the transfer unit hide required by the central processing unit is bypassed, so it is different from the conventional method in (B). It is understood that data required for the central processing unit can be transferred faster by the time required to move in three transfer units compared to the conventional method.

+gl Effects of the Invention As explained in detail above, the buffer memory control method of the present invention detects that data required by the central processing unit is not registered in the buffer memory in a data processing device having a buffer memory. When the data is moved in, its address and data length are checked, and if it exceeds one block in the buffer memory (in other words, block crossing has occurred), the move-in of that one block is inhibited and the data length is checked. Control is performed such that only data (n transfer unit bytes) is bypassed and sent to the central processing unit, so the memory access time from the central processing unit is shortened, and by suppressing the move-in described above, This eliminates the need to wait for buffer memory access, which has the effect of improving the efficiency of buffer memory access.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart showing operations when a buffer memory is accessed. In the drawing, 1 is the buffer memory address register (
BSAR), 2 is the buffer memory write data register (BSWDR), 3 is the tag section (TAG')
. 4 is the data section (DAT8), 5 is the comparator (C), 6
is a select circuit, 7 is an adder that detects block crossing, G is a data section (DATA), and input gate B of 4.
PR represents a bypass route + C represents a coincidence signal from comparator (C) 5, respectively. 1 2)

Claims (1)

[Claims] In a data processing device having a buffer memory, when the buffer memory is accessed, if the necessary data is not registered and the address crosses the block boundary of the buffer memory, the data is accessed from the main memory. 1. A buffer memory control method, characterized in that the transfer data is only bypassed and is controlled so as not to be moved into the buffer memory.