JPS60102689A - Apparatus for performing smooth split screen scrolling - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Cathode ray tube (CRT) display technology typically requires that only 24 to 25 lines of information be displayed on a CRT display device. If you also want to display graphic information, such as a rural scene or a design, the most common prior art uses two memory systems, one for graphics and one for text, but it is possible to store both graphics and text in one bitmap memory. There is also prior art to remember. When CRT display devices are used as L-type output means in data processing systems, it often occurs that a user wishes to view the information content of a document that is longer than, for example, 24 or 25 lines. For example, typical business letters are often over 25 lines long. In such cases, it has become common practice to scroll the document or its contents. That is, first 24
Lines of text are displayed on the CRT, and after a certain amount of time, the superlativeness disappears, and the information jumps upwards on the CRT screen, and in this way the first line, the second line, etc. line, 3rd line, etc. disappear from the top of the screen, and at the same time, 25th line, 26th line, 27th line, etc. are added to the bottom of the screen. Such operations are known as whole-sphere scrolling or single-area scrolling. In prior art systems, the text slowly disappears from the viewer in a "jump" manner from the top of the screen and appears in a "jump" position below the screen area. This "jump" operation occurs because the starting address for successive scan operations changes based on text line values rather than scan line values. The existence of this "jumping" phenomenon is also due to the fact that data bits move from one point to another in memory, and this cannot be accomplished within a single frame without the use of complex and expensive hardware. It is also caused by

The DECVT 100 uses a split-screen smooth flow buffer, but no bitmap memory is used to better perform this operation.

When the document to be displayed has one or more fixed portions and the user wishes to scroll only the scrollable portions, the operation is known as split screen scrolling, as described above with respect to DECVT 100. An example of this is when a business letter is hung on a display and the letterhead and the sender's name and title are displayed as fixed upper portions. For example, Dear Mr. Ja
The main text starting from nam and ending with the closing words may constitute the scrollable portion, and the lower fixed portion includes the company address and! It may consist of a call number, etc.

Although the prior art allows for split screen scrolling of text and graphics, it is not possible to perform split screen scrolling of graphics in a smooth motion. The system of the present invention allows split screen scrolling of both text and graphics to be performed in a smooth manner.

Prior art systems designed to perform smooth split-screen suffles of both graphics and text either require electrical circuitry to supply 240 start address destinations (SADs), or require bitmap The entire contents of the memory must be moved within one vertical synchronization period (which is not economically feasible). The system of the present invention requires at most four SADs and four length values. In the system of the present invention, since the off-screen area of the bitmap memory touches the scrollable area of the bitmap memory, new information to be displayed is added to the off-screen area and the off-screen area of the bitmap memory is added to the off-screen area under the control of the area length value IQ parameter. The button advances the scan into the off-screen area to update this new information.
It can be used by manual operation.

The present invention uses smaller hardware than the prior art to perform the entire smoother split screen scrolling operation. The system of the invention uses a single storage means, a bitmap memory which stores both the text and graphics to be displayed. Thus, the system of the present invention can provide smooth split-screen scrolling with less hardware than systems using two memories.

Such systems involve a number of problems in addressing salient points for graphic display, which are greatly alleviated with the use of a graphics display controller (GDC).

The system of the present invention utilizes the GDC to provide addresses for split-screen scrolling operations using up to four starting addresses and four region length values. Using a 4-address method, such as that implemented by GDC, reduces hardware compared to a system with a core size of 240 addresses. The system of the present invention may also reorganize the bitmap memory to permit changes in the display configuration, ie, changes in the size or position of fixed and scrollable areas. The system of the present invention provides one starting address and one area length value for each fixed area, and two starting addresses and two area length values for scrolling areas. The system is configured to have an off-screen area (a storage area that holds information not normally displayed) adjacent to the scrollable storage area. In a split-screen scrolling operation when scrolling is done upwards, the top visible line (of the scroll area) disappears and the intelligence line immediately below it disappears.
is written to the top row position of the scrollable area. At almost the same time, new information to be written in the bottom row position of the scroll area of the CRT is transferred to the off-screen area of the bitmap memory. The region length value then causes the circuitry to "advance" to scan the immediately adjacent row in the off-screen storage area, and the information in this adjacent row becomes the new information in the bottom row of the scrollable area of the display. added to. In this way, the system scrolls one scrollable area after another. When off-screen storage runs out of space and there is still scrollable information to display, the system must find storage to process such information. The system has a storage area (
(in a scrollable area of bitmap memory) is used for the above purpose. When reusing a scrollable region of bitmap memory in this manner, the system addresses the first row of the scrollable region. This first storage line is loaded with new information that will be added as the bottom line of the scrolling text. Each line of scrollable storage is reused until the scroll operation is completed.

In this way, the information depicted within the scrollable area of the display appears to come from a circulating or wrap-around storage device.

BRIEF DESCRIPTION OF THE DRAWINGS In order that the objects and features of the present invention may be better understood, a detailed description will be given below by way of non-limiting specific examples based on the accompanying drawings.

In FIG. 1, a main computer is connected via a plurality of input-output channels to discrete peripheral devices at various locations, as well as to local input/output devices. The device connected to channel 13 is one of a number of output systems with which main combiner 11 cooperates to provide information to the user.

It should be understood that the channels shown in FIG. 1 include multiple parallel wires that propagate address, data, and command information at various times. channel 3
A microprocessor 15 is connected to the . In a preferred embodiment, the microprocessor 15 is an Intel 8085 device. microprocessor 1
5 is random access memory (RAM) and read-only memory (ROM) c! : includes the main computer 11
It functions as a dedicated slave to facilitate access to data and command information for the display circuitry connected thereto.

As shown in FIG.
A graphic display controller 19 (hereinafter referred to as GDC) is connected to the controller 19 via a company channel 17.

In a preferred specific example, this GDC is NEC #MZC.
Use ROPD 7220. A write clock generator is included within CDC 19 to produce 7 write cycles for each horizontal blank time and 594 write cycles for each vertical blank time. Other clock rates may be used.

A buffer 23 is also connected to the microprocessor 15 via a channel 21 . In a preferred embodiment, the buffer 23 is made of Texas Instruments 74.
S189 and 74LS191 devices are used, but other types of buffers may be used. C
DC 19 receives command and data information signals from microprocessor 15 and sends address information, command information and graphics information to channel 25. channel 25
The upper command signal controls a multiplexer (MUX) 29.

MUXs 27 and 31 are controlled by command signals sent from microbe processor 15 via register 42.

In the preferred embodiment, register 42 is a Texas Instruments 74 LS 273.MUX 27 transfers the text data signal from /ζ' buffer 23 and the graphics data signal from CDC 19 in response to a write clock signal. The buffer 23 is loaded with 16.times.10 bits and one complete character (IOXIO bits) is formed within this bit range. The bit signal from buffer 23 is advanced 16 bits at a time to MUX 27 and from there to bitmap memory 33.

In a preferred embodiment, the bitmap memory is comprised of 64Kx1 dynamic RAM. These RAMs are N
Although MICROD4164-3 manufactured by EC Corporation is used, other types of bitmap memory may also be used. Here, the bitmap memory has 5 bitmaps per scanning line.
It is assumed that the address segment is configured to have 0 address segments.

It should also be understood that the write clock operates at 2 MHz, so that the bitmap memory can receive from seven 16-bit words of buffer 23 in one horizontal blanking period. The information on channel 37 is written to or read from memory when the memory segment on channel 37 is selected by the address information on channel 39. If information is to be written to the memory, a write enable signal must be present on channel 40, as described below.

These write enable signals may or may not be excited depending on the combination of signals present on either channel 47 or 49. When there is text information to be transferred on channel 37, the control information signal on channel 49 is transferred through MUX 31-g so that the correct write enable signal is selectively provided (or masked). Channel 4 to transfer graphic information to channel 37
The control signal on MUX 31 passes through MUX 31 to selectively provide (or mask) the write enable signal. Bitmap memory 33 transfers information signals to CRT 51 via shift register 53.

The bitmap memory 33 is a storage device having storage elements for each pixel position on the CRT display 51. C
RT display device 51 is a standard CRT display device capable of displaying 24 to 25 lines of text and having 10 beam scan lines per line of text. In a preferred embodiment, the CRT display device is VR2 manufactured by Digital Equipment Co., Ltd.
Use 01 or VR240. As mentioned above, there is a storage location in the bitmap memory 33 corresponding to each pixel location or each dot location on the CRT device 51.

The bitmap memory used in the preferred embodiment has sufficient storage to additionally store eight lines of text. In the preferred embodiment, bitmap memory 33 can actually accommodate 32.8 lines of text, but it is assumed here that bitmap memory 33 can store 32 lines of text to be displayed. The information signal read from the bitmap memory 33 is sent to the channel 56 and passed through the shift register 53 to the CRT 5.
Transferred to 1.

Before discussing the operation of the circuitry shown in FIG. 1 in connection with smooth split-screen scrolling,
It will be necessary to explain the characteristics of GDC19 in further detail. G.D.C.
19 may provide four starting addresses and four range length or end of range values as described above. Although the GDC 19 can and does provide graphical display information, it functions primarily as a device for providing address signals in this scrolling operation. The address signal for the information read into bitmap memory 33 is channel 2.
5 and is transferred to the bitmap memory via channel 35, MUX 29, decoder 45 and channel 39. A preferred embodiment uses a Texas Increment 74 LS 253 as decoder 45. Therefore, the picture element information from the microprocessor is transferred to the buffer 23, and from the buffer 23 the MUX 27
When transferred to , it is placed in bitmap memory at a location corresponding to the address signal from GDC 19 as found on line 39 . Bitmap memory 33 is CR
When supplying or reading information to T51, GD
C19 sends an address information signal to channel 39 to select a location in bitmap memory from which the CR
Information for T is read. Although we have stated that GDC 19 may provide four starting addresses and four range length values, not all operations require such four addresses. This will be explained in more detail later. In addition, the GDC device [19 has at least two registers,
One of them is a register for the current address, and the other is a register for the current area length value. The meaning of these two registers will be better understood from the following description.

As previously mentioned, the GDC device 19 generates horizontal and vertical synchronization signals that cause information to be transferred through the system in strict synchronization with the CRT's electron beam. Such horizontal and realignment synchronization signals are transferred via connection 57 to CRT 51, shift register 53, and microprocessor 5. The write signal is sent to buffer 2 via connection 31.
3 and the destination counter 41.

When output from bitmap memory to CRT is completed, G
The Aviles counter in DC 19 is incremented by the tell signal, and the -10,000 range value register is decremented by the horizontal synchronization signal.

In addition, the vertical synchronization signal transferred to the microprocessor 15 is used to increment or decrement the value of the address information in the RAM 18, and such control provides the basis for the new starting address transferred to the GDC 19. .

As previously mentioned, one complete scan line involves 50 addresses in bitmap memory, and one complete line of text involves 500 addresses. Therefore scan 2471
When 0 lines (corresponding to 1 line of text on the CRT) are completed, the starting address changes by 500. As mentioned above, since the horizontal synchronization signal decrements the region length value in the region length value register, if the region length value in the region length value register is equal to zero, the system will display the specified region from the bitmap memory. sense what has happened. Once a given area is displayed, the system provides a new starting address for the next area to be displayed. This new starting address is sent out by GDC device 19ρ, channel 25.35, MUX
29, decoder 45 and channel 39 to the bitmap memory.

The operation of the system can be better understood by considering FIG. 2 with the explanation of FIG. 1 in mind. Assume here that there is a document such as a business letter having a fixed area 59 of two lines. This two-line fixed area 59 (see FIG. 2) may contain the names and titles of other callers on the institution's letterhead, such as Robert Smith, President, etc. Assume that this business letter also has a lower fixed area 61 containing the institution's address and toll-free telephone number. Under such conditions, 4 lines out of 24 text lines that can be used when displaying sentence 1 #65 on the screen are already used by fixed areas 59 and 61. It is assumed that the main text, starting from the recipient's name and address and the @: greeting to the conclusion, consists of approximately 30 lines of text. This text is shown as area 63 in FIG. As mentioned above, the bitmap memory can store 32 lines of text in the preferred embodiment. Also, as a general standard in the industry, C++ displays 24 lines of text.
It is only necessary to provide an RT display device.

The "off-screen" area of bitmap memory may hold information used in various operations related to the display, although the description of the present invention does not include background data in this off-screen storage area.
nd materiml ), i.e., non-intelligent data, is assumed to be loaded.

FIG. 3 shows the bitmap memory used in the preferred embodiment which can store 32 lines of text for display information. However, it should be understood that other memories with different capacities can also be used. Sentence 1″65 (second
When actually storing information representing the information (see figure) in the bitmap memory shown in FIG.
9 will be stored in the first two rows 59A of the bitmap memory. And 20 lines out of 30 lines including the main text 63 of the letter 65 are in the scrollable area 6 of the memory.
7, and the lower fixed part 61 is stored in the last two parts of the memory.
It is stored in row 61A. A memory area 69 between the lower fixed area 61A and the scrollable area 67 is an area for storing off-screen information. When information is stored in the bitmap memory 33 as shown in FIG. 3 and read onto the CRT, the information in the upper fixed area 59A appears in the upper portion of the display screen. The first 20 lines of the letter are then displayed below, and the lower fixed area 61
The information stored in A is displayed on the last two lines of the screen.

Consider now the case where the system operates in a split-screen scrolling manner so that 30 lines of text comprising the body of a letter are displayed as the body scrolls. To perform this operation, K causes the first start address (SADI) to be transferred from the GDC device 19 to the bitmap memory 33 as shown in FIG. At the same time, the region end value (LENI) is stored in the region end value register. It should be noted here that LEN
The value is decremented by the horizontal sync pulse (10% of the text line) so LENl is equal to 20 in the example. When <LENI is decremented to zero as described above, the system senses that the fixed area 59A information has been transferred to bitmap memory, and GDCl 9 transfers the second starting address (SAD2) to bitmap memory.

This second starting address (SAD2) corresponds to the starting point of the first scan line of the third text line 71 as shown in FIG. Since there are 500 addresses for each text line, the value of 5AD2 would be 1,000 in this specific example. At the same time, a second region end value is loaded into the GDC's region end register and is decremented in response to the horizontal sync signal.

Since the second region scan involves 20 lines and each text line involves 10 horizontal synchronization lines, the value of LEN2 (
(see Figure 3) becomes 200. When the LENl value is decremented to zero, the system displays the scrollable area 67.
The GDC detects that 5AD3 is displayed, and transfers the third start address 5AD3 as shown in FIG. 5AD3 is 15,000 in the specific example.

At the same time, the third region end value LEN3 is loaded into the region end register of the GDC. The value of this LEN3 is 20 in this concrete column. When LEN3 is decremented to the opening, the system begins a second full scan of bitmap memory.

At the start of the second full area scan of the bitmap memory, G
The same 5AD1 and LENl that DC19 gave earlier
supply. However, the second starting address transferred when LENI is decremented to zero is SAD 2A.
(see FIG. 3), which corresponds to the second scan line of text line 71. The LEN2A value is the same as the LEN1 value, but scanning will be advanced to the first scan line of the off-screen storage area. In this way, the scrollable area advances one scan line per frame (within one frame), and scrolling is performed in a smooth motion. 5AD2 is at the position of 5AD2B, i.e. text line 7
7, the scrolling would have occurred in a jumping motion one text line at a time. If SAD reaches a value of 5AD2B, the second text line 77 has already moved upwards on the screen and is displayed adjacent to fixed area 59, and the information in text line 71 has disappeared.

The second area end value does not change during this scroll operation portion. When the text line 77 is moved directly below the fixed area 59, the first text line 75 in the off-screen area is effectively moved into the scrollable area. Prior to this, or at about the same time, information from the buffer is read into an off-screen area, specifically text line 75, and later as the last line of the scroll area on the screen, i.e. before this first scroll step, line 73. will be displayed in the position previously occupied. When each LENl value becomes zero, GD
Cl9 supplies 5AD3 and LEN3Y with the same values as before. The system continues this operation and is programmed to sense that the off-screen area has ended when line 79 of text within the off-screen area is displayed as line 28 of the body of the letter. Once this occurs, the system must reuse the portion of memory into which text line 71 was originally loaded. microprocessor 1
5 keeps track of what the starting address is, so when the starting address is 5,000, representing the ninth text line of split-screen scrolling, the behavior of the system changes to the extent that it does. In a scroll operation in which the ninth text line is the first line, the LENZC value is one less than in the fc preceding scroll operation in which the eighth text line is the first line. This is because in a scroll operation in which the ninth text line becomes the first line, the scrollable area becomes smaller by one scanning line when the scanning reaches the fixed area 61A. Therefore, the third starting address is 5
AD3A, which is the same address as 5AD2, which corresponds to the first scan line of text line 71. In this case, the LENaA value is 1. To perform a scroll operation when the 10th text line is the 1st line, use LEN
ZC value is 10 from when scrolling the 9th text line
therefore, the scan does not proceed into the fixed area 6e and the LENBB value is 20, so text lines [71 and 77 of bitmap memory are used.

In this reuse operation, every time the lNa value becomes zero, the fourth starting address 5AD4 is used as shown in FIG.
Note that the end area value LEN4 is used to display fixed area 61A on the screen. If this operation continues for p as described above, the LENZC value will continue to be decremented while the LEN3 (A, B, etc.) value will increase, implementing a wrap-around scrolling operation.

As is clear from the description of the specific example, less information is transmitted from row 71 of the bitmap memory one scan line at a time, but in the first part of the scroll operation, the recipient's name is first displayed on the phosphor screen. displayed above. At the same time that the information from line 77 is transferred and displayed on the third line of the screen, the recipient's name disappears and the recipient's address is displayed on the first line. In the lower part of the letter body, line 73
moves to position 74, and the information in line 75 is available at position 73. Off-screen areas, especially row 75
The information in is mostly packed-ground information, that is, non-intelligent information, so this packed-ground information appears in position N, 73, but immediately after that, when data from buffer 23 is loaded in line 75, this Intelligent information is written to the screen.

The area termination value does not change until all off-screen areas are used. The end region value is then decremented from the initial scroll region value and incremented for the new reused scroll region. The system uses smaller hardware and because new information is added to off-screen areas and the ongoing scan of bitmap memory can proceed into off-screen areas (with respect to said new information). You can perform smooth split screen scrolling operations in a short time.

As mentioned above, the system can also perform reorganization when the size or position of the scrollable area is to be changed.

Although it is easy to see that bitmap memory reorganization could be accomplished under control from the main computer, the main combinator would have to perform all kinds of operations and spend its time reorganizing bitmap memory. It is also necessary to take into account the fact that spending on the combiator leads to a cost on the combiator. Furthermore, bitmap memory reorganization may be a local problem, and in fact information regarding local problems is obtained locally. For example, the main computer may have a CRT like this.
Although many systems may be connected, not all of these systems may desire to reorganize the bitmap memory.

Therefore, the system of the present invention performs bitmap memory reorganization locally.

Assume that the bitmap memory exhibits the configuration shown in FIG. 4 after a split screen scrolling operation. FIG. 4 shows an upper fixed area 81 consisting of eight lines, followed by a scrolling area (SRB') consisting of four lines.
) 83, an off-screen area 85 consisting of 8 lines, and 4
A scroll area (SRA) 87 consisting of lines and a lower fixed area 89 consisting of eight lines are shown. Now suppose the user wants to reorganize the system to allow full screen scrolling and keep the display in the form shown in FIG. In this case, the system operates in a reorganization manner.

When the system operates in the reorganization mode, the 4-row segment (SRB) 83 is located in the off-screen area 85 as shown in FIG.
Move to the first four rows of

This operation is performed during vertical and horizontal blanking periods.

To do this, send the start address from CDC19,
The data may be transferred to the bitmap memory via the UX 29, decoder 45, and channel 39.

This address is for reading, so the information at this address is read and sent to the ratte 93 via the channel 91. Then microprocessor 15
sends the destination address to channel 95 which is then transferred via destination counter 41, channel 43, MUX 29, decoder 45 and channel 39 to bitmap memory.

As a result, the information held in the ratte 93 is transferred to the channel 9
7, channel 35, MUX 27, channel 37, and is returned to bitmap memory 33 and placed at the destination address given by counter 41. In this reorganization mode, the start address register in the GDC 19 is incremented in response to the write signal, and the counter 41 is incremented in response to the write signal, so pixel information is given to the counter 41 starting from the start address. The data is transferred line by line from the bitmap memory until the destination address is returned to. When the LEN value becomes zero, the system senses that a particular segment of memory has been reallocated pursuant to a reorganization operation in a manner similar to that described above.

The meaning of this operation is clear from FIGS. 4 and 5.

This reorganization operation causes the system to display information as shown in FIG. 6, so that 5ADI becomes the first starting address as shown in FIG.

The LENI value is located at the end of the 8th line as shown in Figure 4.

5ADZ value is the beginning of SRA segment, LEN2 value is S
Located at the end of the RA segment.

In addition, the 5ADa value is the first of the SRB segment, I, FN
The ternary value is located at the end of the SRB segment.

However, the starting point of the OS segment is the destination
Note that address DES 1 is given. The system is programmed to perform a reorganization step.

Information from the SRB will therefore be read onto channel 91 during the vertical and horizontal blank times and relocated to the upper portion of the OS segment.

The reorganized state of the bitmap memory after this first step is shown in FIG. When LEN3 in Figure 4 becomes zero, the system moves to 5AD4 and
:End with N4. The bitmap memory after the first step of reorganization takes the form shown in Figure 5.

5AD1, LENI, 5AD2 and LEN2 in the second full area scan are as shown in FIG. Note that destination address 2 (DES2) is also provided and is the first scan line of OS segment 85A in FIG. In this case, SRA segment 87 is read from bitmap memory onto channel 91 and the destination address DES in the bitmap memory is read.
Relocated to position 2. Then 5AD3 and LEN3
, 5AD4 and LEN4 are used to reorganize the bitmap memory as shown in FIG. In FIG. 7, SRA is in the position of SRB in FIG. 4, and SRB is in the position above O8 in FIG. The final step of the reorganization operation is 5
Apply ADI as shown in Fig. 7 and scan LENi as shown in Fig. 7.
This is done by continuing until the value is reached.

The second SAD2 signal is generated as shown in FIG. 7, and at the same time, the destination 3 (I) ES3) signal is generated, so the lower fixed area 89 is transferred from the bitmap memory to channel 9.
1 is read back to the DES 3 address. By this reorganization step, the information from segment 89 is placed in the O8 area 85C of FIG. 7, so that the bitmap memory after the third reorganization step is as shown in FIG.

As is clear from the above description, it is only necessary to obtain four starting addresses and four area length values from the DGC 19 to perform the necessary operations. It is also clear that off-screen areas of bitmap memory are required to perform the operations described above and to perform smooth split screen scrolling operations. In the reorganization scheme, the area to be interchanged or moved must first be moved into an off-screen area. These areas can be stored there and also displayed. In this way, the reorganization is carried out without being noticed by the observer. The off-screen area must be adjacent to the scrollable area so that scanning of the bitmap memory can continue into the off-screen area under the control of the region termination value, the Q parameter, as described above. By advancing the display at a rate of υ1 scan line per frame as described above, split screen scrolling becomes a smooth motion rather than a "jump" type motion that advances one line of text at a time. This smooth scrolling is, of course, one of the objectives of the present invention. Still, since GDC is used to obtain up to A starting addresses and four region ending values, each segment of bitmap memory can be addressed while using hardware economically.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the system of the present invention, FIG. 2 is an explanatory diagram showing the layout of the screen of the display device,
FIG. 3 is an explanatory diagram showing the layout of the bitmap memory, FIG. 4 is an explanatory diagram of the layout of the bitmap memory showing the segments to be reorganized, and FIG. 5 is an explanatory diagram of the layout of the bitmap memory after the first step of reorganization is completed. 6 is an explanatory diagram of an example of the layout of a desired display device screen to be obtained by reorganizing the bitmap memory, FIG. 7 is an explanatory diagram of the layout of the bitmap memory after the second step of reorganization, and FIG. FIG. 2 is an explanatory diagram of the layout of the bitmap memory after the third reorganization step is completed. 11... Main computer, 15... Microprocessor, 19... Graphic display controller, Z
3...Nonotsufa, 27.29.31...Multiplexer, 33...
Bitmap memory, 41... Destination counter, 42...
...Register, 45...Decoder, 51...CRT display device, 53...
Shift register, 65... Document, 59.61... Fixed part, 63... Main text.

Claims (1)

Claims: tn A cathode ray tube display device used to display information from a primary computer source and using bitmap memory to store pixel information to be displayed, comprising:
a circuit for providing smooth split-screen scrolling, the circuit comprising: microprocessor means connected to the main computer; control circuitry connected to the microprocessor means; a first circuit means; 2 circuit means, said microprocessor means receiving instruction data and address data from the main computer, and also receiving a coded text signal, encoding said coded text signal and converting said coded text signal into said coded text signal; The control circuitry is configured to form an array of bit signals defining text characters representing text, the control circuitry having logic circuitry as well as at least one address register and a region length register and receiving command signals from the microprocessor means. and means for storing an address signal, and further configured to increment the address register by 1 and decrement the area length register by 1 in response to each scanning line of the cathode ray tube, and the first circuit Means is connected to the microprocessor means for receiving the bit signal array therefrom and to the bitmap memory for transmitting the bit signals thereto, and the second circuit means is connected to the control circuitry. K is connected to the bitmap memory for receiving address signals therefrom and for transmitting the address signal thereto, thereby causing the control circuitry to operate in one frame and to set the first starting address and subsequent address signals thereto. The address is transmitted to the pit map memory to read pixels in a specific area of the bit map memory one scan line at a time, and this continues until the area length register is decremented to zero; The addressing and reading operations are repeated sequentially with a starting address that differs by one scan line/line from the previous starting address, so that the display corresponding to the initially addressed bitmap memory portion is displayed one scan line at a time. A cathode ray tube display device characterized in that the display disappears at a certain rate, and to the observer's eyes, the display appears to move in the direction of the erased portion. +21 The bitmap memory has a fixed area, a scrollable area, and an off-screen area adjacent to the scrollable area, the specific area is the scrollable area, and the addressing and 2. The cathode ray tube display device according to claim 1, wherein the reading operation continues, and as a result, pixel information is read from the off-screen area. (3) The microprocessor means transmits new information to the off-screen area, and the pixel information read from the hindlimb off-screen area becomes new information. The described cathode ray tube display device. +41 The invention of claim 1, characterized in that said -r microprocessor means has -r only memory, said memory being configured to transmit an array of character defined bit signals in response to receipt of said coded text signal. Range 1
The cathode ray tube display device described in Section 1. (5) said control circuitry is configured and connected to receive a graphics bit signal from said microprocessor means and to transmit said signal through a portion of said first circuitry means; A cathode ray tube display device according to claim 1. (6) the first circuit means comprises a first multiplexer;
6. A cathode ray tube display device as claimed in claim 5, characterized in that said multiplexer is configured to transmit said bit signal array in ml mode and said graphics bit signal in a second mode. (7) The first circuit means includes a buffer, the buffer receiving the bit signal array and holding it until it is time to transfer it to the bitmap memory. The cathode ray tube display device described in . (8) The bitmap memory has a fixed area, a scrollable area, and an off-screen area, and the specific area is the scrollable area. Before reading all the pixel information of the off-screen area according to the value of the area length register! A self-addressing and reading operation is performed, after which a new starting address of the person is applied to the first scan line of the scrollable area, so that at least a portion of the scrollable area of the bitmap memory is scanned a second time. A cathode ray tube display device according to claim 1, characterized in that it is subjected to scanning. (9) said microprocessor means transmit new information to said scrollable area portion that was first scanned, so that new information appears on the cathode ray tube display when said last-mentioned portion is subjected to a second scan; 9. The cathode ray tube display device according to claim 8, characterized in that: