JPS599303Y2 - Time division data reading circuit - Google Patents

Description

[Detailed explanation of the idea] The present invention relates to a time-sharing integrated reading circuit.

Normally, an integrated circuit for clocking divides the oscillation frequency of the built-in crystal oscillation circuit to clock the clock, derives the output as a 4-digit hour/minute segment output, and converts each digit into a 4-bit binary code. It is derived as a time-divided clock output for each digit in synchronization with the input clock signal, and the former is normally used for display and the latter for data.

On the other hand, in order to read time-shared data into a microcomputer that operates according to a program, first detect the input of specific data among the time-shared data that is input to the interface in conjunction with the derivation of a read command signal that occurs at an arbitrary time, and then immediately generate the read command signal. A read pulse is used to store data in a register at an address specified by the program in the CPU, and the register address is changed in preparation for the input of subsequent data. After the manual preparation of the subsequent time-sharing data is completed, a read pulse is generated. A series of programs that read subsequent data into registers at changed addresses must be executed as many times as necessary.

Therefore, the period τ of the read pulse requires a time interval from when data is stored in a register until preparation for storing subsequent data is completed.

Therefore, in order for a microcomputer to directly read the clock signal of the clock integrated circuit which derives the clock data by time division as described above, the time division period must have a constant relationship with the read pulse.

Therefore, in view of the above-mentioned points, the present invention provides a time-division data reading circuit which adjusts the time-division interval to a predetermined range in order to directly read the time-division data generated by the clock integrated circuit as a clock signal to a microcomputer. This is what we would like to propose.

An illustrative embodiment of the present invention will be described below.

This embodiment employs the present invention in a program reservation circuit that connects a clock integrated circuit to input a clock signal to a microcomputer that makes program reservations. Fig. 1 is a schematic block diagram of this embodiment. Figure 1 shows a built-in crystal oscillator which is frequency-divided to keep time, receives a clock pulse T, and derives a time-division 4-digit segment output to display the display panel 2.
4-bit binary data D1-D4 are time-divided in synchronization with the clock pulse T, and digit instruction pulses T1--indicating the digit positions of the derived binary data data D1-D4. A clocking integrated circuit 3 receives the binary data D1 to D4 and the digit instruction pulses T1 to T4, stores the binary data in a register at a specified address, and compares it with the reserved time to make a reservation. A micro-combiner that emits an output to turn on the power when the time arrives and an output to select a reserved channel.

Reference numeral 4 designates a clock generation circuit for driving a clock pulse C which is input to the clock integrated circuit 1 and determines the time division period T. Reference numeral 5 designates a divided pulse R of the CPU driving clock whose period is the same as that of the read pulse. A first counter counts within a period determined by the astable multivibrator 6; 7 is a second counter that similarly counts clocks occurring in a predetermined period determined by the material-stable multivibrator 6; 8 is a direct counter 5, 7; Comparing circuits are shown for controlling the period T of the clock pulse of the clock generating circuit 4 to match the period τ of the read pass/L pass by comparing the counted values of .

In the circuit of this embodiment, when the microcomputer 3 starts executing a program for reading a clock signal, for example, the second
In order to read the 16:58 hour signal as shown in the figure, specify the address of the CPU register and set the hour 4.
Immediately after waiting for the rise of the digit display pulse T1 that occurs when deriving the data in the + digit of "hour" among the digits, the first read pulse is derived, and the binary data D1 to D is stored in the designated register.
The contents of 4 are stored as "1", and the binary data of the negative digit of the next "hour" (D1 to D4) is incremented to the address of the register to be input.Then, the read pulse generated at a constant period τ is used. Run a program that synchronously repeats the same operation as above to store the time in four registers, then transfers and stores the stored contents in consecutive 16-bit registers, and compares it with the reserved time stored in advance. Execute.

In this embodiment, a new time division frequency is input every time a read pulse is generated, and the frequency of the clock generating circuit 4 is controlled so that the above-described reading can be executed smoothly.

That is, the frequency division pulse R and the clock pulse C generated within the period determined by the astable multi-output are counted by the first counter 5 and the second counter 7, and the two counted values are compared by the comparison circuit 8, and the The oscillation frequency of the clock generating circuit 4 is controlled.

Therefore, in this embodiment, the clock C is derived every time a read pulse is generated, and new time-shared data is input every time the microcomputer reads.

Therefore, according to the present invention, there is no need to provide a buffer memory for waiting for time-division signals, and the effect is great.

[Brief explanation of the drawing]

Fig. 1 is a circuit block diagram showing one embodiment of the present invention;
The figure is an explanatory diagram of the same waveform. Explanation of main figure numbers, C...clock, R...divided output, D1-D4...binary digitizer, T1-T4...digit indicating pulse.

Claims (1)

[Scope of utility model registration request] a clocking integrated circuit that derives time-division data in synchronization with a clock derived from a clock generation circuit; a microcomputer that reads the time-division data using read pulses; and a comparator circuit for controlling the oscillation frequency of the clock generation circuit in order to change the contents of the time division data readout circuit.