JPS5992498A - Memory control circuit - Google Patents

Abstract

PURPOSE:To protect the resource on a memory in an effective and assured way with a simple circuit constitution by reading out the application propriety display bit corresponding to the relevant address region after a user gives an access to a main memory and then deciding the validity of the memory access under execution. CONSTITUTION:For a user who is going to use a computer, the information showing the propriety of the access to each block is set to an exclusive bit in an RAM1 corresponding to each block in the form of 0 or 1. Then a byte in the RAM1 is selected by address lines A16-A10 and supplied to a multiplexer 2 as soon as an access is given to a main memory 7. Furthermore a data line showing the application propriety of a block containing the memory access address under execution is selected among 8 data lines supplied to the multiplexer 2 through address lines A12-A10. When the access is incapable to the corresponding exclusive bit in the RAM1, the action on of an acknowledge generating circuit 6 is inhibited. Then the generation of a fault is informed to a CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is based on a simple memory management circuit for protecting in-memory information from unauthorized access.

The memory that has a protection function can be damaged by unauthorized access.
There is a risk that the confidentiality of data may be leaked or data may be destroyed, which will hinder the improvement of system reliability.

An object of the present invention is to provide a management circuit for memory protection that can be easily implemented.

In order to achieve the above object, the present invention divides the main memory into a large number of equally sized areas, and each bit of a RAM separately provided for memory management is assigned a unique specialized function to each of the equally divided areas. The value of each bit is set by O8 to display the availability of each area for each user, and when a user accesses the main memory, the usage availability corresponding to the address area is displayed at the same time. The display bit is also read to determine the validity of the memory access being executed.

FIG. 1 shows an embodiment of the present invention, in which 1 is a RAM for main memory management, 2 is a multiplexer, 3 is a decoder, 4 is a receiver, 5 is a terminal, 6 is an acknowledge generation circuit, and 7 is a main memory. . As shown in FIG. 2, the main memory 7 is logically divided into memory areas of equal size (hereinafter referred to as blocks; in the example shown in FIG. 2, one block is 1 kilobyte KB). Information indicating whether the user who is trying to use the computer at that time can access each block is displayed in the R corresponding to each block.
A, set the unique bit in M1 as 0 or 1,
It is set and b. When accessing the main memory 7, as shown in FIG.
l6~A,. 1 byte in RAMI is selected and input to multiplexer 2. As shown in Figure 1,
Furthermore, address lines A, 12-A,. Among the eight data lines input to the multiplexer 2, one data line indicating the availability of the block containing the memory access address being executed is selected, and is sent to the terminal 5 of the multiplexer 2.
The availability of use (access) is output as binary information, which controls the acknowledge generation circuit 6 in the memory device. R.A.
When the corresponding dedicated bit in MI is set to be inaccessible, the operation of the acknowledge generation circuit B is prohibited and the CPU is notified of the abnormality. In FIG. 2, the j-th bit of the first byte in RAMI indicates whether block M(1) of the main memory 7, which is equally divided into 1 kilobyte (210 bytes to be exact) each, can be used. Here i = 8 to 10j
, 2N-1≧1≧07≧j≧0 As shown in FIG. A+t # A, 8
This is possible only when the RAM 1 is selected via the decoder 3 and the gate of the receiver 4 is opened. In this way, by having each bit of the RAM represent the usability of each block of the main memory, it is possible to restrict the usable memory area for each user program with a changeable button as appropriate.

As described above, according to the present invention, with a simple circuit configuration and operation, memory resources can be effectively and reliably protected and system reliability can be improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram illustrating the concept of memory management according to the present invention. DESCRIPTION OF SYMBOLS 1...RAM, 2...Multiplexer, 3...Decoder, 4...Receiver, 6...Acknowledge generation circuit. 7...Main memory. Sai lc8 Oh 2 side NKB

Claims (1)

[Claims] In order to protect against unauthorized access by users, the main memory is divided into many equal areas (VC), and the values of unique dedicated bits provided for each of these areas are used to control whether or not each area can be used by a specific user. A memory management circuit characterized in that when the p main memory is addressed by a user, the dedicated bit corresponding to the address area is simultaneously read out, and whether access is possible or not is controlled. .