JPS5991739A - Automatic equalizer - Google Patents

Abstract

PURPOSE:To attain ease of miniaturization of the titled circuit and LSI formation, and the automatic equalization with high quality and reliability, by splitting an output amplitude of plural CR primary circuit networks by capacitors, controlling the split ratio and summing each output after the control. CONSTITUTION:An input signal at an input signal terminal 1 is inputted to a negative input terminal of an adder 5 through m-set of circuit networks connected in parallel. One set of circuit network consists of a resistor Ri, three capacitors 2C, four capacitors C, and a switch S or the like controlled by a tap weight coefficient di(i=1-m). The discriminating section 7 discriminates an output of the adder 5 and outputs tap weight coefficients d1-dm. The tap weight coefficient controls the switch S to minimize an output waveform distortion of the discriminating section 7. Since the primary CR circuit network is used in this way, the miniaturization of the circuit and the LSI formation are attained easily, and since the digital control system is used, no problem of nonlinearity exists, and the dynamic range is broad; then an automatic equalizer requiring high equality and high reliability is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic equalizer that automatically equalizes the transmission characteristics of a line by adapting it to the line condition. Shown in Figure 1. In Figure 1, l is a signal input terminal, 2 is a signal output terminal, 3 is a tap delay line, 4 is a tap weighting coefficient, 5 is an adder, and 6 is a weighting coefficient adapted to the signal input and set to an optimal value. The final estimation control section 2 is an identification determination section that judges the output of the adder 5 and outputs the result to the estimation control section 6.

Input signals having waveform distortion propagated through the signal input terminal 1 are added together by an adder 5 via a tapped delay line 3 and a tap weighting coefficient 4, and sent to an identification determination section 7. Estimation control section 6
operates to minimize the waveform distortion of the input signal at the discrimination determination time nT based on the output of the discrimination determination section 7.

Known methods for realizing the tagged delay line 3 include (1) using an all-pass circuit network consisting of L and C, (2) using an active filter, and (2) using a charge transfer device (CCD). (2) The method using an all-pass circuit network made of glue and C and the method (2) using an active filter have the disadvantage that there is a limit to the frequency band that can be realized, and it is still difficult to miniaturize the circuit and integrate it into an LSI. The method (2) using a charge transfer element has the disadvantage that nonlinear distortion due to residual charge transfer is large and a wide dynamic range cannot be achieved.

An analog multiplier is used to realize the tap weighting factor 4. The function of the tap weighting coefficient 4 is to multiply the output of the estimation control section 6 and the output of the tapped delay line 3, and output the multiplication result to the adder 5. Estimation control unit 6, tack 0
Since the output of the delay line 3 is an analog quantity, an analog multiplier is required to multiply the output of the estimation control section 6 and the output of the tag delay line 7. Analog multipliers are nonlinear and have a narrow dynamic range, making it difficult to realize automatic equalizers that require high quality and high reliability.

The present invention provides a tapped delay line that overcomes these drawbacks.

The purpose is to provide an automatic equalizer that does not require analog multipliers.

The present invention is an automatic equalizer characterized by dividing the amplitude of the output of a plurality of C, R primary circuit networks by capacitance, controlling the division, and adding the outputs after each control. An example will be explained.

FIG. 2 is a block diagram showing a first embodiment of the present invention. l
is a signal input terminal, 2 is a signal output terminal, 5 is an adder, 7 is an identification judgment unit, di + ti2+..., dm is a tag weighting coefficient, R, R/2,..., R/m is a resistance, Cl
2C and C' are capacitors, and S is a switch. The switch S has the tap weighting coefficient d r (+ = 1 + 2+...
. , m) via a controller (not shown), but the state of the switch in FIG. 2 is an example. The input signal from the input signal terminal 1 is applied to the negative input terminal of the adder 5 through m circuit networks connected in parallel. Here, the - set of circuitry consists of a resistor R1 + 3 capacitors 2C, 4 capacitors, and a switch S controlled by a tap weighting coefficient di.
(However, l-1, 2,...,
m). The identification determination unit 7 determines the output of the adder 5 and outputs tap weighting coefficients ai, a2°, . . . , dm. The tap weighting coefficients control SW and S so that the waveform distortion of the output of the discrimination determination section 7 is minimized.

Next, the tap weighting coefficient dl r d2 +..., d
Taking dl out of m as an example, explanation will be made according to FIG. Third
The figure consists of a resistor R2, a capacitor 2C, a capacitor C, a switch S, etc. in the path from the signal input terminal l in FIG. 2 to the negative input terminal of the adder 5 via the switch controlled by the tap weighting coefficient dl. RC circuit, adder 5 and capacitor C'
We focused on this and expressed it with an equivalent circuit. In Fig. 3, the input impedance of the adder 5 is sufficiently low, so the capacitance when looking to the right from each point of Plr P2 + P3 has the same value as the capacitance 2C, and the input signal at terminal a is connected to the point P1 at the 9/2 degree point. P2 gives 9/41 points and P3 gives υa//8. Therefore, the equivalent circuit viewed toward the adder 5 from points P4 and P5 can be written as shown in FIG. 3(b). Figure 3(b)
In this case, the output υ8' of the adder 5 is 9'-1(c+'-) x E-, (1)8C. In Figure 3(a), the capacitance seen from point a to the right is the same size as capacitance C, and equation (1)
When C dl-s is positive, FIG. 3(a) can be written as the equivalent circuit shown in FIG. 3(c).

Next, we will use the maximum slope method as an equivalent algorithm for controlling the switch S in FIG.
This will be explained according to the diagram. FIG. 4 is an explanatory diagram of the control system of the switch S. 1 is a signal input terminal, 2 is a signal output terminal, 5 is an adder, 7 is an identification determination section, 8.8' is a code detector that detects the sign of the manually input signal, and 9 is an adder that performs addition of N pieces. 1o is a multiplier, R, R/2, ..., R
//rrl is resistance, C is capacitance, d, 1d2. ...,
dm is a tag weighting coefficient. The circuit group from the signal input terminal 1 to the identification determination section 7 is an equivalent circuit of the circuit group from the signal input terminal I to the identification determination section 7 in FIG.

The algorithm is shown by equation (2).

Here, dl(y+1) is the value of the (ν+1)th weighting coefficient, d, (1/) is the value of the (ν)th weighting coefficient, en
is the error signal, and Plrn is the resistor R/ connected to signal input terminal 1.
1. The output of the R, C circuit consisting of the capacitance C. Δ is an infinitesimal constant + Sgnen\ is the sign of en + SgnP l + n is PI, and the sign of n (where i = 1, 2, . . . , m). The sign detector 8 detects the signs of the outputs Pi, n of the R, C circuits and outputs S
g n P 1. Output n.

The sign detector 8' detects the sign of the error signal en and outputs Sgn
Output n. The above Sgn P l + n and Sg
Since the value of nen is +1 or -1, the formula (2) -
is executed by digital calculation. Adder 9 (Sgn
Add N values of en)·(SgnPi, n). The multiplier 10 performs dinotal multiplication by the addition result and the infinitesimal constant -2Δ.

If the multiplication is performed with m-bit accuracy, d'(v+1) in equation (2) becomes an m-bit desotal quantity. The (ν11)th tap (ν) is corrected by adding the output of the multiplier 10 to the νth tap weighting coefficient d1(ν).
+1) Weighting factors di are determined. By repeating the above calculation, the optimal tap weighting coefficient d1opt is obtained.

The control of the switch S is performed using another algorithm (e.g. Zero
Fareing algorithm) is also applicable.

FIG. 5 shows experimental results showing the effect of the embodiment shown in FIG.

The transmission line is a bare cable, and the transmitted signal has a width of 2.
It is a rising wave of 511 seconds. In FIG. 5, the broken line is the equalizer input signal, and the solid line is the equalizer output signal.

Table 1 shows specifications such as tap weighting coefficients.

Table 1 and FIG. 6 show a second embodiment of the present invention, which is applied to an automatic equalizer having a cyclic configuration, and achieves the same effect as the first embodiment. The second embodiment shown in FIG. 6 replaces the circuit group inserted between the signal input terminal l and the negative input terminal of the adder 5 in FIG. Although it differs from the first embodiment in that it is inserted in between, the tap weighting coefficient control algorithm is the same as in the first embodiment and is expressed by equation (2).

As explained above, according to the present invention, since a primary CR circuit network is used without using a tapped delay line, the circuit can be easily miniaturized and integrated into an LSI, and it is also possible to use a digital control system. Because of this, there are no problems with nonlinearity, and the dynamic and cross-resonance ranges are wide, making it possible to realize an automatic equalizer that is compact, high quality, and highly reliable.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a conventional automatic equalizer, Fig. 2 is a block diagram showing a first embodiment of the present invention, Fig. 3 is an explanatory diagram of tap weighting coefficients, and Fig. 4 is a block diagram of a control system. FIG. 5 is a characteristic diagram showing the response of an isolated ie laser according to the first embodiment, and FIG. 6 is a configuration diagram showing the second embodiment of the present invention. 1...Signal input terminal, 2...Signal output terminal, 3...
Delay line with tap, 4...Tag weighting coefficient, 5...Add n
device, 6... Estimation control unit, 7... Identification determination unit, 8, 8
'...Sign detector, 9...Adder, 10...Multiplier Patent applicant Oki Electric Industry Co., Ltd. Figure 3 (CI) (b) r' (C) 1 Figure 6 procedural amendment (Touge) ■ Indication of the case 1982 Patent Application No. 201099 2 Name of the invention Automatic equalizer 3 Person making the amendment Relationship with the case Patent application Person in charge (
1-7-12-12 Toranomon, Minato-ku, Tokyo 1-7-14 Agent address (105) 1-7-1 Toranomon, Minato-ku, Tokyo
Contents of amendment No. 2, No. 6 (1) In the first line of Part 3 of the specification, the phrase "the division is controlled" is amended to read "the division ratio is controlled." (2) The status of switch 1 is stated in the first line of page 4 of the ministry.
"The number and status of the switches are corrected." (3) On the 17th line of the same page, the phrase "RC circuit" is corrected to "C circuit." (4) On the 19th and 20th lines of the same page, the statement "Because the input impedance of adder 5 is sufficiently low" has been replaced with "Because the negative input terminal of adder 5 is a virtual ground terminal." and correct it. (5) 1 above R, C circuit on page 6, line 15 of the same amount.”
I am referring to it as ``the above C, R circuit''. (6) Correct the drawing in Figure 3(C) by j-'-9 from the attached sheet. Figure 3 (c) 10 construction

Claims (1)

[Claims] An automatic equalizer characterized in that the amplitude of the outputs of a plurality of C and RJ circuit networks is divided by capacitors, the division ratio is controlled, and the outputs after each control are added.