JPS5990131A - Transfer device of direct memory access - Google Patents

Abstract

PURPOSE:To attain the transfer of direct memory access between 16-bit and 8-bit systems by dividing a 16-bit memory into upper and lower places to connect them to buses with switching secured between both buses and connecting an input/output device of 8 bits to one of the two buses. CONSTITUTION:A memory M of 16 bits is divided into high-order and low-order memories HN and LM of 8 bits each. These high-order and low-order memories are connected to high-order buses HBDs 8-15 and low-order buses LBDs 0-7 of 8 bits each via transceivers TRs 2 and 1, respectively. An 8-bit input/output device I/O4 is connected to the LBDs 0-7, and a TR3 connected between memories LM and HM transfers data by the signal sent from a switch control circuit 5 and decides the transfer direction. For instance, the HM part is connected to LBDs 0-7 via TRs 3 and 1 to perform DMA between the HM and LM. Thus the DMA is carried out by a simple device between the 8-bit I/O4 and the 16-bit memory M.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides direct memory access (DM) between a 16-bit main memory in a 16-bit microprocessor system and an input/output device that can only handle 8-bit data.
A) Regarding the transfer device.

Traditional microprocessor systems have 8 data buses.
It is generally made up of 8-bit data, and many control various input/output devices (Ilo), and SI, etc., are designed to handle 8-bit data. When using such a conventional 8-bit LSI to control the 8-bit Ilo connected to the 16-bit data bus, there are the following drawbacks. Since the I10 control LSI handles 8-bit data, it is connected to only 8 bits of the 16-bit data bus. Because of this, Ilo cannot handle the data on the remaining 8-bit data bus, and even if DI'vlA transfer is performed with the main memory, the data bus on the other side of Ilo is not connected. I can't do it.

It is therefore an object of the present invention to provide a DMA transfer device capable of providing all the data sent on a 16-bit data bus to an I10 device connected to only 8 bits of the 16-bit data bus. .

According to the present invention, 16 bits are divided into two sets of 8 bits each.
a switching circuit that interconnects each set of pit data buses;
A DMA transfer device is obtained, which is characterized by comprising a control circuit that controls the circuits to enable or disable the direction in which data is mutually transferred and the operation of the connected circuits.

Next, the present invention will be described in detail with reference to the drawings showing one embodiment of the present invention. In Figure 1, the 16-bit memo 'J
M is divided into two sets of lower and upper 8 bits, and a 16-bit data bus Bus is created by boiling transceiver (TR) 1 and island transceiver 2, respectively.
lower 8 bits) DO~D7 and upper 8 bits D8~
Connected to D15. The transceiver is a circuit that connects two sets of 8-bit data each inside the main memory M to the upper 8 bits or lower 8 bits of the 16-bit data bus Bus.

The MRD signal given from the processor (not shown) is
The signal that gives the timing to output the data in memory M to the data bus, the Mw'r signal gives the timing to write data to the memory, and the DMA signal is the signal that gives the timing to output the data in the memory M to the data bus.
This is a signal instructing DMA (direct memory access) transfer between I/04 and main memory M. The switching control circuit 5 receives signals SLT, which control the transceiver 3;
This circuit controls the connection state of the transceiver 3 using the ENB.

The 8-bit I10 device 4 connects to the 16-bit data bus Bu.
Connected to the lower 8 bits of s.

When the DMA signal is valid, the main memory M determines that the data is to be transferred with Write the data to memory.

During DMA transfer between the 8-bit address bus 104 and the memory M, the switching control circuit 5 uses the address bus AO when MRD is valid (when performing data transfer from the memory M to the memory M).
~Depending on whether AO of An is it On or "1"',
The transfer direction of the transceiver 3 is fully determined, and the 8-bit data buses are interconnected. That is, as shown in FIG. 2, in the switching control circuit 5, if the MRD signal is valid (0) and the address line AO of the address bus is O, the transceiver 3
Disable the switching operation (ENB signal to 1). As a result, the lower 8 bits of memory M are transferred directly to the lower pins of the 16-bit data bus Bus via transceiver 1.
(DO~Dr). The flow of data at this time is shown in FIG. Also, at this time, the content of address line AO is 1.
If so, enable the switching operation of transceiver 3 (ENB signal is O), and transfer the SLT signal from memory M to data bus 13.
Set the welding mode (1) in the us direction. As a result, the upper 8 bits of memory M are transferred to the lower bits of the data bus (D
output to O-D7). The flow of data at this time is explained in the fourth section.
As shown in the figure. Therefore, the lower bits of the data bus) (Do~
Memo IJ to 8-bit input/output device 4 connected to D7)
Data transfer of both the upper and lower 8 bits of M is possible.

Next, the operation during data transfer from the input/output device 4 to the memory M will be explained. At this time, the processor (not shown) enables MA transfer (sets the DMA signal line to 1) as shown in FIG.
to enable (0) the write signal line MWT. If the content of the address line AO is 0, the switching control circuit 5 disables the switching operation of the transceiver 3 (ENB
Let the signal be 1). As a result, data from the input/output device 4 is written to the lower 8 bits of the memory M.

The data flow at this time is shown in FIG. At this time, if the content of the address line AO is 1, the switching control circuit 5 enables the switching operation of the transceiver 3 by setting the ENB signal to 0, and writes the SLT signal from the data bus 13us to the memory 4 direction. Set to mode (0). As a result, data from the input/output device is written to the upper bit side of the memory υM via the transceiver 3. The data flow at this time is shown in FIG. Therefore, the lower bits of the data bus (D
o~D7) Data from the input/output device 4 connected to the memo 1. It becomes possible to write to both the upper bit side and the lower focus side of IM.

As explained above, the present invention has a switching circuit that connects the 8-bit data line of an 8-bit configured input/output device to the upper and lower bits of a 16-bit configured memory, and its control circuit. This has the effect of enabling I) MA transfer between the system and an input/output device with an 8-bit configuration.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a DMA transfer device according to the present invention, FIG. 2 is a diagram showing the states of each signal line when reading from the memory, and FIGS. 3 and 4 are diagrams showing the state of each signal line when reading from the memory. FIG. 5 is a diagram showing the state of each signal line at the time of writing to the memory, and FIGS. 6 and 7 are diagrams showing the data flow at that time. 1.2... Transceiver, 3... Transmitter for data flow switching, 4... 8-bit input/output device, 5... Switching control circuit, M... ...1
6-bit main memory IJ, Bus...16-bit data bus, AO to An...address lines. βαS Figure 1 pθ~p7 Yu3 Ward Figure 5 Yuotsu Figure 9o-D'7 Beach Map

Claims (1)

[Claims] In a 16-bit microprocessor system having a 16-bit main memory and a data bus, a first bus connects the upper 8 bits of the main memory to the upper 8 bits of the data bus, and a first bus connects the upper 8 bits of the main memory to the upper 8 bits of the data bus; means for interconnecting data transfer between the first bus and the second bus; and a control signal from the 16-bit microprocessor. A direct memory access transfer device comprising: means for controlling the connection state and data flow direction of said means.