JPS5984975U

JPS5984975U - Noise reduction circuit for reproduced FM luminance signal

Info

Publication number: JPS5984975U
Application number: JP17970182U
Authority: JP
Inventors: 健古川
Original assignee: 三洋電機株式会社
Priority date: 1982-11-26
Filing date: 1982-11-26
Publication date: 1984-06-08
Also published as: JPH0233434Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は本考案回路の１実施例の回路構成図、第２図は
第１バイパスフイルタ並びに第２バイパスフイルタ及び
トラップ回路の直列回路にそれぞれ再生ＦＭ輝度信号を
付与したときの周波数特性図、第３図は特殊再生時の遅
延線出力点における周波数特性図である。土な図番の説明、１・・・入力部、４・・・第１バイパ
スフイルタ、７・・・直列回路１．８・・・第１スイッ
チ回路、９・・・遅延線、１０・・・第２スイッチ回路
、１１・・・ＦＭ復調回路、１２・−・制御信号付与手
段。FIG. 1 is a circuit configuration diagram of one embodiment of the circuit of the present invention, and FIG. 2 is a frequency characteristic diagram when a reproduced FM luminance signal is applied to a series circuit of a first bypass filter, a second bypass filter, and a trap circuit, respectively. FIG. 3 is a frequency characteristic diagram at the output point of the delay line during special reproduction. Explanation of the diagram numbers, 1... Input section, 4... First bypass filter, 7... Series circuit 1.8... First switch circuit, 9... Delay line, 10... - Second switch circuit, 11... FM demodulation circuit, 12... Control signal providing means.

Claims

[Scope of utility model registration request]

An input section that reproduces a multiplexed signal of an FM luminance signal and a low frequency conversion color signal on a recording medium and outputs a reproduced FM luminance signal, and one that is input by branching the reproduced FM luminance signal from the input section into two. a series circuit including a first bypass filter for inputting the other of the two branches, a second bypass filter for inputting the other of the two branches, and a trap circuit for the low-pass conversion color signal; a first switch circuit having a control signal input terminal that receives the series circuit output at a second input terminal and further selects one of these plane input terminals; a delay line that receives the first switch circuit output; and a delay line that receives the first switch circuit output; a second control signal input terminal for receiving a line output at a first input terminal, receiving a non-delayed output from the first switch circuit output at a second input terminal, and selecting one of the plane input terminals; an FM demodulation circuit that receives the output of the second switch circuit; and an FM demodulation circuit that receives the output of the second switch circuit;
and means for applying a control signal to the control signal input terminal such that both switch circuits output signals from the first input terminal.