JPS5977790A - Key telephone interface device - Google Patents

Abstract

PURPOSE:To increase the transmission amount of data within a specific time and to increase the number of connectable sets and the kind of service by transmitting in parallel an interchanging data between a central processing unit and each interface circuit through a common circuit. CONSTITUTION:Hooking data or button data sent successively from each key telephone set 1 is converted into parallel data by the data circuit 6 of each interface circuit 5. Then when signals (a)-(n) from a timing control signal 9 indicate access to a memory, the data is stored in specific locations in the memory circuit through a bus B. The central processing unit 12 when receiving a signal (p) which indicates access to the memory from the circuit 9 reads the data out of the circuit 8 through the bus B. The central processing unit 12 controls a switch circuit network 10 according to the contents of the read data to connect the voice circuit 3 of the circuit 5 by the circuit network 10, thus increasing the interchange amount of data within a specific time.

Description

[Detailed description of the invention] The present invention relates to key telephone interface devices.

In a key telephone system that controls the mutual connection between a key telephone and a central office line, a key telephone interface device is interposed between the key telephone and the main unit and transmits and receives data between the two.

FIG. 1 is a block diagram showing a conventional key telephone interface device. In the figure, the button telephone interface device is composed of a plurality of interface circuits 2, each interface circuit 2 is connected to a plurality of button telephones 1, and a switch circuit network 10 of the main device and a central processing unit 11 are connected. ing. Each button telephone 1 is connected to an audio circuit 3 and a data circuit 4 of an interface circuit 2 via a pair of audio signal lines and a pair of data signal lines, respectively. The unit audio circuits 31 of the audio circuits 3 are each connected to the audio signal line of one button telephone 1, and supply a constant current to the handset when the button telephone 1 is in use.
Audio signals are exchanged between the switch network 10 and the switch circuit network 10.

The data circuit 4 is connected to the data signal lines of the plurality of button telephones 1, and is connected to each of the button telephones 1 and the central processing unit 1.
Signals d1 to dm are exchanged with the terminals 1 and 1. signal dx-
Of the DM, what is transmitted from the button telephone 1 are the hook data and button data generated in response to the operation of the handset hook and push button on the button telephone 1, and what the button telephone 1 receives is This is display data that instructs the blinking of a lamp or the display on a display unit, and both are serial digital signals (or pulse signals modulated with the digital signals) each having a predetermined number of pits.

FIG. 2 is a time chart showing the timing of signals d1 to dm. The signals d1 to dm are sent and received every cycle T so that the signals do not overlap each other during the time t.

In FIG. 1, the data circuit 4 receives the picking data or button data sequentially sent from each button telephone 1 at the above-mentioned timing, and converts the data (or the demodulated signal thereof) into predetermined bits. The data is converted into parallel data and sent to the central processing unit 11. The central processing unit 11 sequentially scans and decodes the parallel data sent from each interface circuit 2, and according to the decoding results, sends all child control signals to the switch circuit network 10 to perform a connection operation. At the same time, the internal connection state of the switch circuit network 10 is determined. Each button telephone 1 receives a signal indicating
Parallel data indicating display data of is transmitted to each interface circuit 2. The data circuit 4 of the interface circuit 2 receives this parallel data, converts it to serial data (or performs further modulation), and sequentially transmits it to each button telephone 1 at every time t of data exchange between each button telephone 1. The lamp will blink or the display will display.

The conventional button telephone interface device as described above is equipped with a plurality of interface circuits 2 and exchanges data with the central processing unit 11 in parallel transmission. Compared to the case where data conversion is performed directly by serial transmission, a larger amount of data can be exchanged within a predetermined time. However, since all data is exchanged directly between each interface circuit 2 and the central processing unit [11],
1, it takes a lot of time to exchange data while sequentially scanning each interface 2. Therefore, if you further increase the number of key telephones 1 connected to the main device, or increase the number of push buttons and displays on each key telephone 1 and add service functions, the central processing unit 11 will The disadvantage is that it becomes impossible to exchange data.

The purpose of the present invention is to eliminate the above-mentioned drawbacks, and to enable a larger amount of data to be exchanged with a central processing unit than before, thereby making it possible to easily increase the number of connectable key telephones and the types of service functions. An object of the present invention is to provide a button telephone interface device.

The device of the present invention is provided with first serial data indicating the operation of push buttons and hooks from a plurality of button telephones, and a predetermined pit for instructing the operation of the display means of the button telephone from a central processing unit in the main device. a button telephone interface device interposed between the central processing unit and the button telephone to exchange data, and receiving the first serial data; Set this to the specified value.

a first data conversion circuit that converts the first parallel data into second parallel data, and @2 data conversion circuit that receives the first parallel data, converts it into second serial data, and transmits it to the button telephone. a plurality of data conversion means having a plurality of data conversion means, each of which writes the second parallel data and reads the first parallel data in response to an access from the central processing unit; memory means for writing the first parallel data and reading the second parallel data, and a timing signal indicating the timing of access to the memory means of each of the data conversion means and the central processing unit. t-
and timing control means for generating the signal.

Next, the present invention will be described in detail with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention. In the same figure, the button telephone interface device comprises a plurality of interface circuits 5, a memory circuit 8 and a timing control circuit 9. When compared with the device shown in FIG. 1, the portion that transmits and receives data signals is different. That is, the data circuit 6 of each interface circuit 5 converts hooking data or button data (or a signal obtained by decoding the data) sequentially sent from the button telephone 1 into predetermined bits of parallel data in the same manner as in the case of FIG. After conversion, the signal a sent from the timing control circuit 9 to each
-n indicates the timing of accessing the memory, the data is sent through the entire bus B to a predetermined location in the memory in the memory circuit 8 and stored therein. When the signal l sent from the timing control circuit 9 indicates the memory access timing, the central processing unit 12 reads the hooking data and button data stored in the memory circuit 8 via the bus Bi, and uses the contents thereof. Accordingly, the switch circuit network 1° is connected, and display data corresponding to the connection state is generated and stored in a predetermined location of the memory circuit 8 through the entire bus B. Each data circuit 6 receives a signal a sent thereto.
When % n indicates the timing of memory access, the display data stored in a predetermined location of the memory circuit 8 is read out via the bus B, and this is converted into serial data or modulated thereafter). Each button telephone 1 is sequentially sent and displayed.

FIG. 4 is a block diagram showing an example of the configuration of the data circuit 6 in FIG. 3, and FIG. 5 is a time chart illustrating timing signals in FIGS. 3 and 4. In the data circuit 6, a serial/parallel conversion circuit 61 converts the serial data sent from the button telephone 1 into parallel data and stores it in the memory circuit 62. Address data indicating the address of the memory circuit 8 to which this parallel data is to be written is stored in advance in a predetermined location of the memory circuit 620.

When the signal W sent from the timing generation circuit 66 becomes high level (H), the parallel data and address data are read out from the memory circuit 62 and sent to the bus B as a data signal and an address signal, respectively. Signal W is sent to bus B as a write signal for writing and storing data signals in all memory circuits 8. These signals pass through the path B=i to the memory circuit 8 shown in FIG.
The data signal is stored at the location indicated by the address signal. Next, when the signal r becomes H, the parallel-to-serial conversion circuit 65 sends the signal r to the bus B as a read signal indicating the timing of reading data from the memory circuit 8, and also sends the signal r to the bus B as an address signal indicating the read address from the memory circuit 8. is sent to bus B. These signals are sent to the memory circuit 8 shown in FIG. 3 on the bus Bi, and the memory circuit 8 accordingly converts the display data stored in the location indicated by the address signal into parallel and serial data through the entire gun bus B. circuit 65
send to The parallel-to-serial conversion circuit 65 receives this parallel display data, converts it into serial data, and sends it to the selector circuit 63.

When the selector circuit 63 receives the serial data from the receiving circuit 65, it distributes the serial data in a predetermined order and sequentially sends the serial data to each button telephone 1. Note that the signal S is a prohibition signal, that is, a signal that prohibits the operation of the serial/parallel conversion circuit 61 only while the selector circuit 63 is sending out serial data.

Signal a sent from the timing control circuit 9 to each interface circuit 5 and central processing unit 12 in FIG.
.about.n and signal p are arranged such that the times at which they become H do not overlap with each other, thereby preventing a plurality of accesses to the memory circuit 8 from being performed at the same time. For example, as shown in FIG. 5, the signal a is from time A1 to time B.
1, and during this period, signals a to n
All of them except signal a are at low level (L). The timing generation circuit 66 receives the signal a'(i-) and generates a signal W that becomes H between time A1 and time C1, and a signal W that becomes H between time A1 and time C1.
A signal r that becomes H from 1 to time B1 is generated and sent to the memory circuit 62 and the parallel-to-serial conversion circuit 65, respectively. In response, the memory circuit 62 writes data into the memory circuit 8 between time A1 and time C1,
Further, the parallel-to-serial conversion circuit 65 reads data from the memory circuit 8 between time C1 and time B1. Similarly, from time N1 to time P1, only signal n becomes H, indicating the memory access timing of data circuit 6 receiving signal nf, and from time P1 to time A2, signal ? Only "H" indicates the memory access timing of the central processing unit 12. At time A2, the signal a becomes H, and thereafter the timing pattern described above is repeated.

In the embodiment described above, the data exchange between each interface circuit 5 and the central processing unit 12 is performed in parallel transmission via the memory circuit 8, and the central processing unit 12 is transmitted in batch with the memory circuit 8. and perform data conversion. Therefore, the central processing bag fIL12 does not need to sequentially scan each interface circuit 5 as in the conventional case, and it becomes possible to exchange data in a greater number of times than in the conventional case within a predetermined time.

Note that what has been described above is only one example, and the present invention is not limited to this. For example, the data circuit 6 shown in FIG.
is constructed by combining logic circuits, but it is clear that it can be realized by L program control for microprocessor tl instead, and the same effect can be obtained.

As is clear from the above explanation, the present invention has the advantage that the data exchange between each interface circuit and the central processing unit is performed in parallel via a common memory circuit, thereby allowing data exchange between each interface circuit and the central processing unit to be performed in parallel within a predetermined time. It is also possible to convert a large amount of data into cash, and therefore it is possible to realize a button telephone interface device that can easily increase the number of connectable button telephones and the types of service functions.

[Brief explanation of the drawing]

1 and 2 are block diagrams and time charts illustrating a conventional key telephone interface device, respectively, FIGS. 3 and 4, and FIG. 5 are block diagrams illustrating an embodiment of the present invention, and This is a time chart. 1...Button telephone, 2.5...Interface circuit, 3...Audio circuit, 4,6...
...Data circuit, 10...Switch circuit network, 11.12...Central processing unit, 8...
-Memory circuit, 9...timing control circuit. Figure 7 Atsushi 2nd “A S Figure

Claims (1)

[Scope of Claims] A predetermined bit that is given first serial data indicating the operation of a push button and a hook from a plurality of button telephones, and that instructs the operation of a display means of the button telephone from a central processing unit in a main device. A button telephone interface device intervening between the central processing unit and the key telephone and transmitting and receiving data receives the first serial data of mJ and transmits it to a predetermined bit. . a first data conversion circuit that converts the first parallel data into second parallel data, and a second data conversion circuit that receives the first parallel data, converts it into second serial data, and transmits the same to the button telephone. a total of a plurality of data converting means having a plurality of data converting means, and writing of the second parallel data and reading of the first parallel data in response to access from each of the data converting means; a memory means for writing the first parallel data and successively outputting the second parallel data; and timing indicating the timing of access to the memory means of each of the data conversion means and the central processing unit. A button telephone interface device comprising timing control means for generating a signal.