JPS5971092A - Image data processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image data processing device that can freely rotate an image displayed on a CRT using an increment method.

When a drawing or the like is displayed in an interlaced manner on a CRT, there may be cases where it is desired to rotate the display by 90°, 180°, or 270° to make it easier to see, such as when a drawing written horizontally is displayed vertically. The following methods can be considered as methods for rotating the screen.

(1) Rewrite the contents of the refresh memory using software.

(The 21CRT itself is rotated mechanically.

However, the method shown in (1) is not practical because it takes several minutes or more to complete the vertical/horizontal conversion operation. Furthermore, method (2) has many problems because it imposes large restrictions on the structure of the device and also increases the size of the device itself.

The present invention has been made in view of the above points, and includes a first memory that simply converts a serial interlaced video signal into a parallel one and stores it, and a first memory that stores the data in the first memory. A second memory is provided to store data for one screen after rotation by a certain angle, and the output of the second memory is converted back to serial data and taken out, allowing the image displayed on the CRT to be freely displayed. This realizes an image data processing device that can rotate and display images.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a configuration diagram showing an embodiment of the present invention. In the figure, 1 is a buffer circuit that receives a serial interlaced video signal, 2 is a conversion circuit that converts serial data into parallel data, and 5 is a first memory that receives the output of the conversion circuit. The first memory stores data in the form of stacking each line of the CRT display horizontally and vertically for each odd or even line. Figure @2 is a diagram showing a more detailed configuration of the first memory. In the figure, the part surrounded by a thick line is the unit in which data for one line is stored. Four of these units are stacked vertically to form one pro-Ll, which stores data for four lines. Such blocks 1 and 2 are further added together to constitute a first memory. For example, a RAM is used as the memory. The output of the conversion circuit 2 is 1
It is written to the first memory 3 in units of 6 bits. The memory stores data for 8 lines of the screen (for example, 8 x 64 bytes), and is divided into two blocks L of 4 lines each.
+.

It is divided into L2.

4.5 is a rotating means each constituted by a buffer gate. 4 rotates the data taken out from the first memory 3 by tfO° or 180°. 5 is also the first
90° or 270°
Rotate each. Specifically, the outputs of the respective buffer gates intersect to provide a signal at a position corresponding to the rotation angle. 6.7, buffer gates that receive the outputs of the rotating means 4 and 5, 8 an input register that receives the output of the buffer gate 6, and 9 an input register that receives the output of the buffer gate 7. 0 from buffer gate 6
°.

The 90° rotation data signal is sent from buffer gate 7 to Ni 1.
Rotation data signals of 80° and 270° are respectively transmitted.

A second memory 10 receives and stores data from the input registers 8 and 9. Data for one side is stored in this memory. Further, as the memory, for example, a RAM is used like the @10 memory 5. 11 is the second
This is an output buffer that outputs the output of the memory as serial data. The output (2) of the conversion circuit becomes the output of the device of the present invention. The output VQ is applied to a CRT (not shown) and displayed in an interlace format. 12 is an address counter.

20 is a first address conversion means for providing a write or read address to the first memory 3, and a write address generation circuit 21. Read address generation circuit 22.2
3 and a delay element 24. The delay element 24 is for aligning address signals for four lines. 30 is a second address conversion means for providing a write or read address to the second memory 10&C;
Write address generation circuit that provides 7 addresses for 0°! 5
1. A write address generation circuit 52 that provides an address for 90°, a write address generation circuit 33 that provides 7 addresses for 180°, a write address generation circuit 34 that provides an address for 270°, and a read address generation circuit 55. has been done.

40 is an exclusive OR gate (hereinafter simply referred to as an EOR gate) which receives a control signal and an O/E signal for selecting an odd frame or an even frame.

The output of the EOR gate is mixed into the address bus.

When writing the second memo+)+OK data, an identification signal indicating whether the frame is an odd frame or an even frame is required. Furthermore, in order to write data to the second memory 10 that is delayed by 4 lines from the writing to the memory 3 of the cabinet 1, the EO
The load signal input to the R gate 40 is a signal that keeps on at 1'1'' only while the first four lines of the screen are being written to the first memory 3. The operation of the device will be explained below.

Image data (video signals) are sent continuously from the top left to the bottom right of the screen. The image data sent is stored in the first memory 3 in the configuration shown in FIG. FIG. 4 is a diagram showing a conversion table of the address conversion means 20 at this time. In the figure, A is the memory 30 input address, B is the state of the input address at the time of GX writing, and C, D is
Each indicates the state of the input address at the time of reading. Among the 10 bits of the input cuff address, the upper two bits (Part E in Figure C) are bits that select which line (!1 to La) in Figure 2 is to be selected. A with the combination of 2biy)
Can you select any one line from 1 to j4?

Select the position of each line in the depth direction (direction of the arrow in the figure) at position T, 8 bits, and G (section F in the figure). .

The upper two bits of this F part (G part) are the bits that select one of the L1 pro, L2 pro, and L2 pro as described above.

First, the case of writing will be explained. Upper 2 bits of address, tA
B15, AB14 K is address counter 12
The seventh bit C10 and the eighth bit CA702 are given. Hereinafter, AB7 is given the 10th bit of the address counter, CA9, and AB6 is given CA8. AB5 is then given CA5 and allocated accordingly as shown in the table below. CA8 to CA5 [The reason for this is that CA7 and CA6 are placed above 7 dresses. This crossing of the outputs of the address counters is performed by the write address generation circuit 21.

First, all bits of the output counter of the address counter 12 are 0. Therefore, CA7. Since both CA6 is 0, →In! 1 is selected. Line j! , 1 is selected and the addresses ABO-AB5 that select the depth direction between the tails are updated 116th time, All0 to ATT5 are (+1
1111) When it becomes K, CA6 becomes 1 in the next 1 a, ri.
Therefore, CAO to CA5 become 0. Since the memory address AB8 is input to CA6, the 2 bits for selecting a line become (01), and the next line j2 is selected. Thereafter, line 4A and line 4A are selected in the same manner.

During this time, the six depth directions of the memory on the same line are sequentially selected. In this way, when all the addressing methods for T, +pro, and ri are completed, address counter CA8 bit 2 is 1st.
When CA8 becomes 1, L2 pro, ri is selected, and 1 to 1iff is added to the first line of L2 pro, ri.
The first selection continues.

Next, the case of reading will be explained. In the case of reading, reading starts from a block different from the block being written. Therefore, only AB6 bits are present. Since CA8 is 0 at the start of reading, the surface becomes 1 and the L2 block is selected first. When reading, 0°
, 180° and 90°.

The way addresses are given to memory is different in the 270° case.
It comes in c. That is, in the case of 0° and 180°, the memory configuration is the same as when Nf is included;
This is because the configuration is completely different depending on the angle of 0°.

In the case of reading when rotated by 90 degrees or 270 degrees, the shaded area 51 (4 bits, toss 4 bits, g) shown in FIG. 2 is read.

Therefore, the lowest bit of the address counter is set to the upper bits AB9 and AB8 of the address for selecting the group.
) CAT and CAl'l are respectively assigned. S1
Objects with the same depth in the depth direction are read out within K.
Become. After the 81st copy is read out, the 82nd copy is read out, followed by Ss, 84, and so on. In this way, the first
Write to and read from memory 3.

Next, the rotation operations of 90° and 270° will be explained. The rotation operation is performed by the rotation means 5. FIG. 6 is a diagram for explaining the rotation operation. (al indicates the state of data in area S1. If this state is rotated 90 degrees to the left, (b
It becomes like l. The display method used in the present invention is an interlace method. Therefore, when storing the data in the second memory 10, it is necessary to arrange the data in every other column as shown in (c). Furthermore, (b) is 15→0,14
-→1.・If we perform the following five transformations (1, exchanging SB and MSH), we get the result shown in (d). (d) shows the state rotated by 270 degrees from the state of (al). The state shown in (d) is When data is stored in the second memory, it is stored in a form arranged in every other column as shown in (elc). FIG. 8 is a diagram showing the correspondence relationship when data is rotated and stored from the first memory 3 to the second memory.The shaded area S+ (
For example, 4×4 bit capacity) is rotated by 90 degrees and arranged in every other column and stored in the second memo 1J101c.

When the data in the first memory 5 is rotated 900 times.

On C and IIT, it is not enough to rotate the single c 900 times, and it is necessary to move the position on the screen as well. That is, when the CRT image shown in FIG. 7 is rotated 900 degrees, the portion at position T1 in the figure moves to position T2. From the above, in order to rotate the data stored in the first memory and transfer it to the second memory and store it in every other column, it is necessary not only to perform a rotation operation by the rotation means 5 but also to move the data to the storage position 14. I know I need to move it. The second address conversion means 30 and the WOR gate 40 perform such movement of the storage location, that is, conversion of the write address.

FIG. 5 is a diagram showing an address translation table of the address translation means 30. For write operation, from 0° to 270°
It is necessary to perform a different address translation operation for each case. Therefore, as shown in the table, the order of address counters that should be brought to the input address differs in each case. When writing to the second memory 10, it is necessary to write every odd line or every even line, so the odd/even select signal 0/E
6; Input to EOR gate 40. In the case of 180° rotation, 0° is inverted, and in the case of 270° rotation, 90° is inverted, so the O/E inverted signal τ is used instead of the O/E signal. . The details of the write operation are the same as the read operation from the 8g1 memory (see FIG. 4), so a detailed explanation will be omitted.

In short, when an address as shown in FIG. 5 is given from the 7-dress counter 12 to the second memory 10, the address generation circuits 31 to 34 store the data at a position corresponding to a predetermined rotation. C. Give a different order for each case.

- After being stored, all you have to do is read them in order, starting with the address with the smallest address. Therefore, in the case of continuous output, only one address generation circuit 35 is required. FIG. 3 is a diagram showing a specific configuration of the second memory 10. The data for one screen is stored in the memory shown in the figure (1). The stored data is read out in order according to the number order shown in Figure 1. That is, the odd numbered line is 6 first), ■..., and then the even numbered lines are read out as ■', ■', ■', and so on. This is applied to the output VD (ItT) via the output buffer 11 (see FIG. 1) and displayed as a rotated image on the CRT.

In the above explanation, taking as an example the case where the unit of rotation and extraction from the first memory is 4 x 4 bits, 1 bit is 4 bits.
It is not necessary to limit it to ×4 bits, but the same number of bits in the vertical and horizontal directions. It can be any number of bits. In the actual rotation operation, while data Y is being written to the L1 block of the first memory, data is being read from the L2 block I':+ヮ〃 and transferred to the second memory.

As described in detail above, according to the present invention, there is provided a first memory that converts a serial interleaved video signal into a multi-channel video signal and stores the same; A second memory is provided to store data for one screen by rotating it by a certain angle, and the output of the second memory is converted to serial data again and taken out.
An image data processing device capable of freely rotating and displaying an image displayed above can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of the first memory, FIG. 3 is a diagram showing the configuration of the second memory, and FIG. 4 is a diagram showing the configuration of the first memory. Memo〇〇)7. Figure 5 is a diagram showing the address conversion table of @2 memory, Figure 6 is a diagram showing the rotation operation, Figure 7 is a diagram showing the address conversion table of the memory of @2.
The figure shows both sides of the CRT, and Figure 8 shows the first memory and the second memory.
FIG. DESCRIPTION OF SYMBOLS 1... Buffer circuit, 2. Conversion circuit, 3... First memory, 4, 5... Rotating means, 6, 7... Buff gate, 8.9... Input register, 10...Second memory, 11...Output cover, F, 12...7 address counter, 20°50...Address conversion means, 40...EO
R gate. Old man 21 Aday, 3 Liu Atsushi No. 414 sI day

Claims (1)

[Claims] means for converting a serial interlaced video signal into parallel; a first memory for receiving the output of the converting means and storing it horizontally and vertically stacked; a means for extracting data in units of N bits vertically and horizontally from the first memory and rotating the data contained in the unit by an angle of one foot; a second memory for storing data equivalent to one screen upon receiving the output of the rotating means; , a conversion means for converting the output of the second memory into serial data again and outputting the same; a first address conversion means for receiving the output of the address counter and giving a write or read address to the first memory; The image data processing device also includes a second address converting means which receives the output of the address counter and sequentially writes or reads an address for every odd number line or +s (M number lines).