JPS5965356A - Single-chip microcomputer - Google Patents

Abstract

PURPOSE:To increase the storage capacity, by providing a circuit within a program counter to change a program counter to the set value other than (0) with an AND of the signal which sets the program counter at (0) and the address region level setting signal. CONSTITUTION:A set value changing circuit 5 is provided within a program counter 1'. When the resetting signal is fed to a terminal R, the counter 1' is set at (0). Then an AND of the address region level setting signal A and the resetting signal R is supplied to the circuit 5 through an AND circuit 6 to change and set the contents of the counter 1' to the value other than (0). The state signal T1phi and the signal sent from the counter 1' are latched 2 temporarily. Then the external memory access signal is delivered to an address bus 4 via an address buffer 3. Therefore an ROM and an RAM are connected from outside to increase the storage capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a single chip microcomputer, and more particularly to an address initialization circuit thereof.

In conventional single-fist chip microcomputers, when the power is turned on and operation begins, an active level signal is sent to the reset terminal? By inputting only the specified clock pulse width, the L program counter is set to (0000)H, and the instruction code is read from the ROM located at the address. By doing so, the microcomputer starts operating. However, single-chip microcomputers are manufactured with the user's specific program code in the internal ROM masked by the semiconductor supplier, so microcomputers used in certain armware systems do not have the entire program added. The original internal program was created in such a way that it could jump to an external memory address according to the 5 conditions when the above-mentioned need arose, such as when adding functions to the system or when testing the microcomputer's ROM. However, it is often impossible to jump because the above-mentioned need, that is, the request to add functions to microcomputer-embedded equipment, comes from the market performance of the equipment, such as the market response. Also, when performing comprehensive debugging by executing programs using external memory while developing a program for a new device, it is best for the user to use a microcomputer at hand on which the program for another device is masked. It should be efficient. In this case, depending on the program written in the original internal ROM, it may not be possible to jump to the external memory at all.
Special external hardware was required.

FIG. 1 is a block diagram of an example of an address initialization circuit of a conventional microcomputer, and FIG. 3 is a timing diagram of the operation of the address initialization circuit of FIG. 1.

When a high-level reset signal is input to the program counter 1 from the reset terminal 1, the program counter 1 is set to "0" at a certain specified number of clocks. For example, if the specified number of clocks is set to 3, the process starts at the timing shown by a in FIG. 3 and ends at the timing shown by b in FIG. If there is a byte in address space 64, program counter l is set to (0000)H.

After reset, when the T1 state M1・To of machine cycle 1 is reached, the output signal from program counter 1 is T.
□ At the timing of the state signal T0 φ, which is the state clock, that is, at the timing shown by C in FIG. do.

In address space 64, there are 16 address buses (A o - A□5) in hexadecimal bytes. At the place.

In the case of a microcomputer, if the address signal output to the address bus 4 is an address value in the built-in memory space, the address signal is not output to the external terminal, and the address signal is output to the external terminal along with the control signal terminal such as memory read signal M)1. The terminal has high impedance, preventing access to external memory and Ilo. Therefore, depending on the program written in the internal ROM, it may jump to the external memory at all. The drawback was that access required special hardware.

The present invention eliminates the above drawbacks and provides a single-chip microcomputer that can access external memory and Ilo without interrupt processing using external control signals.

The single chip microcomputer of the present invention is
Reset signal? A program counter that receives and resets to zero, an address area level setting signal, and the reset signal? an AND circuit that receives the address area setting signal and outputs an address area setting signal sound; a set value changing circuit that receives the address area setting signal and changes the contents of the program counter to a value other than zero and sets it; and a state signal and an AND circuit that outputs an address area setting signal sound. an address latch circuit that temporarily holds an address signal output from the address latch circuit and outputs an external memory access signal;
The address buffer receives the external memory access signal and outputs the address signal for external memory access to all address buses.

Embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram of one embodiment of the present invention.

This embodiment includes a program counter l' that receives a reset signal and resets it to zero, an AND circuit 6 that receives an address area level setting signal and a reset signal, and outputs an address area setting signal sound, and an AND circuit 6 that outputs an address area setting signal sound. A setting value changing circuit 5 changes the contents of the program counter l' to a value other than zero and sets the contents, and a set value changing circuit 5 temporarily holds the state signal and the address signal output from the program counter l' and outputs an external memory access signal. address latch circuit 3 and external memory access signal? The receiver includes an address buffer 3 and t which output address signals for external memory access to an address bus 4.

Next, the operation of this embodiment will be explained with reference to FIG.

The reset signal enters the program counter l' from the reset terminal and also enters the AND circuit 6 at the same time.

An address area level setting signal is also input to the AND circuit 6 from the terminal A, and the AND circuit 6 generates an address area setting signal from the AND with the reset signal, and sends this signal to the setting value changing circuit 5. By inputting the reset signal, the program counter l' is set to "0" for a certain number of cycles. As in the previous case, in the case of a byte in the address space 64, it is set to (0000)H. When the address area setting signal from the AND circuit 6 enters the setting value changing circuit 5, the setting value changing circuit 5 either leaves the contents of the program counter l unchanged or changes them. Changing it means changing it to the external memory start address. For example, if the internal memory is + bytes, change it to (0040)H. This changing operation is performed within the time period a to b in FIG. Although the clock cycle from a to b is slightly extended, this has almost no effect on system performance. When (0040) H is set, the external terminal and the control signal terminal become low impedance, allowing access to the external memory and Ilo. When the contents of the program counter are not changed and remain at (0000)H, the same operation as in the conventional example shown in FIG. 1 is performed.

Note that the number of terminals A is not limited to one, and a plurality of terminals can be provided, and in that case, the execution start address can also be set to a plurality of numbers.

According to the present invention, as described above in detail.

It is possible to access external memory and Ilo without using interrupt processing by external control signals, and it is possible to start execution of the microcomputer from any address. What storage capacity? The effect is great because a single-chip microcomputer that can be expanded is obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of an address initialization circuit of a conventional microcomputer, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a block diagram of an example of an address initialization circuit of a conventional microcomputer. FIG. 1.1'...Program counter, 2...
...address latch circuit, 3...address/couple, 4...address bus, 5...
Setting value change circuit. 3 Ishi no (?1 Rod 2 Figure a b c Yan 3 Figure

Claims (1)

[Claims] a program counter that receives a reset signal and resets to zero; an AND circuit that receives an address area level setting signal and the reset signal and outputs an address area setting signal; and a program counter that receives the address area setting signal and outputs the address area setting signal. a set value changing circuit that changes and sets the state signal to a value other than zero, and an address latch circuit that temporarily holds the state signal and the address signal output from the program counter and outputs an external memory access signal;
An address buffer that receives the external memory access signal and outputs an address signal for external memory access to the address bus? Features a single chip microcomputer.