JPS5963767A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase mutual conductance, and to accelerate a switching speed remarkably by constituting a conductive layer under a gate electrode by a low impurity concentration layer as an upper layer and a high impurity concentration layer as a lower layer, controlling the depth of the depletion layer of the low concentration layer and bringing the low concentration layer into contact with the high concentration layer. CONSTITUTION:A high concentration impurity conductive layer 12 and a low concentration impurity layer 13 are laminated on a semi-insulating GaAs substrate 1 and grown in an epitaxial manner, and a gate electrode 9 is formed at a predetermined position on the layer 13. A compensating impurity, Such as Cr, V, etc. is implanted deeply to the conductive layers 13 and 12 through ion implantation while using the electrode 9 as a mask, the donor impurity ions in high concentration are injected shallowly to source and drain forming regions by jointly using another mask. These implanted ions are activated through heat treatment, and the conductive layers 13 and 12 except the lower section of the electrode 9 are changed into a semi-insulating region 4 while the N type source region 5 and the drain region 6 are formed to the surface section of the region 4. Accordingly, the depth of the depletion layer of the layer 13 remaining under the electrode 9 is controlled, and the connection of the regions 5 and 6 is turned ON- OFF.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device used as a switching element.

In switching elements using some compound semiconductors such as GaAs (gallium arsenide), metal-semiconductor switching devices take advantage of the high mobility of electrons in the material, and also because it is difficult to form a surface inversion layer. Contact field effect transistors (hereinafter abbreviated as IVIEsFET) are widely used. The switching time of this device is approximately inversely proportional to the value of transconductance and proportional to the dart-to-source capacitance.

By the way, assuming that the threshold value of the device is fixed at a certain value, the impurity concentration distribution in the channel part can be divided into two cases: a case where a high concentration impurity is placed at a shallow position, and a case where a low concentration impurity is placed at a deep position. If so, then it is possible. The above-mentioned mutual conductance is approximately proportional to the impurity concentration, and the P-) to source capacitance #1 is inversely proportional to the square root of the impurity concentration. Therefore, in order to shorten the switching time of the device, it is advantageous to place highly concentrated impurities at a shallow position within the channel.

However, if the impurity concentration in the channel becomes too high, the electron mobility decreases and good rectifying contact characteristics between the dart metal and the half-barrel become difficult to achieve, which actually worsens the device characteristics. .

Therefore, there exists a certain optimum value for the impurity concentration within the channel.

Therefore, the threshold voltage of the device is fixed, and the value of the gate length is also fixed due to lithography constraints! Considering this, there is a limit to the switching speed that can be obtained with a normal Mg5FET.

This barrier was created in view of the above points, and the purpose is to provide a semiconductor device whose switching speed can be increased beyond the conventional limit.

Embodiments of the present invention will be described below with reference to the drawings.

Figure '#J1 is a diagram showing a first embodiment of the present invention.

In this figure, l is a semi-insulating GaAs substrate, on which a conductive layer 2.3 and a semi-insulating region 4 are formed. The conductive layer 2 is a conductive layer having a high concentration of 1ψ donor impurities, and the conductive layer 3 is a low conductivity layer having a low concentration of donor impurities.

These are provided as a 4-conductor layer under the dirt electrode, which will be described later. -4 ton No. 3 is located above the shallow position under the dirt electrode, and the conductive layer is located below it, that is, at a deep position under the r-) electrode. Layer 2 is located. The semi-insulating region 4 is located around these conductive layers 2,3. This semi-insulating region 4
Conductive layers 5 and 6 are formed on both sides of the conductive layer 3 on the surface of the conductive layer 3 .

These conductive layers 5 and 6 are conductive layers serving as source/drain regions, and are made of high conductivity 4 layers having a high concentration of donor impurities.
It is stratified. Then, source/drain electrodes 7 and 8 are formed on this tetraelectric layer 5.6.

On the other hand, a gate electrode 9 is formed on the conductive layer 3.

Incidentally, it is necessary that the position of this gate electrode 9 coincides with the conductive layer 3, 2 with optical precision. Also, Kate Tun 1
The conductive layer 3 at step 9F is formed to be 500 to 1000 angstroms thicker than the conductive layers 5 and 6. Moreover, the boundaries between the conductive layer 3 and the conductive turtle layers 5 and 6 are made sufficiently steep.

Such a device is manufactured, for example, as shown in FIG.

In FIG. 2 (5), reference numeral 1 denotes a semi-insulating GaAs substrate, and first, a high concentration impurity conductive layer 12 and a low concentration impurity conductive layer 13 are grown on the entire surface of the substrate 1 using a vapor phase epitaxial growth method. grow sequentially.

Of course, for this crystal growth, it is also possible to use a molecular beam epitaxial growth method or a liquid phase epitaxial growth method.

Next, in a predetermined position on the low concentration impurity conductive layer 13, as shown in FIG.
13) A gate electrode 9 is formed as shown in FIG.

Then, using this gate electrode 9 as a mask, the conductive layer 13 is
．． A compensating impurity such as chromium (element symbol Cr) or pananum (element symbol V) is deeply implanted into the semiconductor layer 12 by ion implantation, followed by shallow implantation of a donor impurity at a high concentration. In addition,
This donor impurity is implanted only into the source/drain forming regions, so the non-implanted regions around the source/drain forming regions are covered with a mask layer (not shown) like the P-) region.

Thereafter, heat treatment is performed to activate the implanted impurities. Due to this activation, the conductive layer 12.13 in the region other than under the dirt electrode 9 becomes a semi-insulating region 4 as shown in FIG. The underlying conductive layer 12,13 remains as conductive layer 2,3. Also,
On the surface of the semi-insulating region 4, conductive layers 5 and 6 are formed on both sides of the conductive layer 3 by donor impurities. In addition,
During this activation, the gate electrode 9 is coated with a heat-resistant gate electrode material (tungsten (element symbol W)) so that the rectifying contact characteristics between the dirt electrode 9 and the semiconductor do not deteriorate.
etc.) must be used.

Finally, ohmic contact source/drain electrodes 7, 8 are formed on the conductive layers 5, 6 as shown in FIG. 2(2).

In the device shown in FIG. 1 manufactured in this way, in order to produce a normally-off device with a positive threshold voltage, the donor impurity concentration of the conductive layer 3 must be reduced by IX
Assuming 1017cIn73, the thickness of the conductive layer 3 is 2000
It is about 1 angstrom. In this case, the state (P-) voltage is Ov) when the gate potential is equal to the source potential.
All of the conductive layer 3 becomes a depletion layer, and the conductive layers 5 and 6 are electrically separated from the conductive layer 2, and thus the conductive layer 5 and the conductive layer 6 are electrically separated. On the other hand, as the gate is gradually biased positively, the depletion layer in the four-electric layer 3 gradually recedes and becomes only near the surface. Therefore, the conductive layers 5 and 6 and the conductive layer 2 are electrically connected through the conductive layer 3, and the conductive layers 45 and 6 are electrically connected to each other through the conductive layer 3.
are electrically connected. Here, if the donor impurity concentration of the conductive layer 5゜6 and 2 is set high as 1 to 5 X l 018α [3, the value of the on-resistance when the channel becomes conductive is
Compared to normal MESFE'r which does not have the conductive layer 2, it is much lower.

As described above, in the device of the first embodiment, the conductive layers 5 and 6 and the conductive j-2 are
, to turn on and off the connection between the conductive layers 5 and 6.
The value of transconductance is much larger than that of a normal MESFET. On the other hand, the capacitance between the gate and the source hardly increases compared to a normal fvlEsF"ET, so the switching time becomes very fast. Depending on the gate length and the impurity concentration of each conductive layer, Although the performance is different, the switching speed can be several times faster than that of a normal Δ1EsNET.

In the first embodiment, a device having a symmetrical structure on the source side and the drain side has been described. In this device, r-
When the drain voltage is increased with the gate electrode positively biased and the channel conductive, the depletion layer extends from the gate toward the drain, so the drain voltage-current characteristic becomes the normal IV11! SFh; On the other hand, according to the second embodiment of the present invention shown in FIG. 3, the saturation characteristic of the drain voltage-current characteristic becomes weaker and becomes closer to a linear characteristic. That is, in FIG. 3, the edge of the conductive layer 6 serving as the drain region and the edge of the conductive layer 2 overlap with each other via the lower part of the fti layer 3 in a region outside the gate electrode 9. be. According to this structure, the conductive layer 2 and the conductive layer 6 as the drain region are always connected through the conductive layer 3, and therefore,
The saturation characteristics of the drain voltage-current characteristics are weak.
It becomes close to the characteristic of Katsutakata.

As described above, in the semiconductor device of the present invention,
An upper low-concentration impurity conductive layer and a lower high-temperature impurity conductive layer are formed as conductive layers under the r-) electrode, and the depth of the depletion layer of the low-concentration impurity conductive layer is controlled to improve this conductivity. By controlling the electrical connection to the highly concentrated impurity conductive layer through the layer, the mutual electrical connection between the two highly concentrated impurity conductive layers serving as source/drain regions on both sides of the previous W+p low concentration impurity conductive layer can be established. Since the i1 mutual conductance is large, the switching speed can be made extremely high.

[Brief explanation of the drawing]

FIG. 1 (1) is a cross-sectional view showing a first practical example of the semiconductor device of the present invention, FIG. 2 is a cross-sectional view showing a method for manufacturing the device of the first embodiment, and FIG. 2.3, 5.6... conductive layer, 9... goo) 11f pole. Patent applicant Oki Electric Industry Co., Ltd.

Claims (1)

[Claims] r-) forming a low concentration impurity conductive layer in which the depletion layer changes over the entire region or only near the surface depending on the voltage, and f-) forming a conductive layer under the electrode on a high concentration impurity conductive layer thereunder;
By controlling the depth of the depletion layer of the low concentration impurity conductive layer and controlling the electrical connection to the high concentration impurity conductive layer through the other conductive layer, A semiconductor device characterized in that electrical connection between two highly doped conductive layers serving as source/drain regions is controlled.