JPS5961154A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPS5961154A
JPS5961154A JP57171204A JP17120482A JPS5961154A JP S5961154 A JPS5961154 A JP S5961154A JP 57171204 A JP57171204 A JP 57171204A JP 17120482 A JP17120482 A JP 17120482A JP S5961154 A JPS5961154 A JP S5961154A
Authority
JP
Japan
Prior art keywords
semiconductor element
group member
lead frame
chip
thermal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57171204A
Other languages
Japanese (ja)
Inventor
Takumi Miyashita
工 宮下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57171204A priority Critical patent/JPS5961154A/en
Publication of JPS5961154A publication Critical patent/JPS5961154A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To improve a radiation effect, and to reduce the thermal strain of a semiconductor element due to a thermal change by forming a lead frame by a copper group member, setting up a metallic plate consisting of an iron group member on at least element loading side of a die stage for the lead frame and fixing the semiconductor element on the metallic plate. CONSTITUTION:The metallic chip 3 consisting of the iron group member such as a 42 alloy is fixed to the die stage 2 of the lead frame 1 formed by the copper group member of high thermal conductivity such as beryllium bronze through spot welding, etc. The semiconductor element 4 is mounted on the chip 3. Terminals for connecting signal lines fitted to the semiconductor element 4 and lead terminals 5 are bonded and connected by wires 6 formed by aluminum or gold and a large number of them are molded and formed at a time with a resin such as epoxy, and the whole is cut and shaped to form the semiconductor device. Heat generated from the semiconductor element 4 is radiated from the die stage 2 consisting of the copper group member such as beryllium bronze of high thermal conductivity through the metallic chip 3. The silicon substrate is not subject to thermal strain because the silicon substrate and a foundation blank forming the semiconductor element 4 have thermal expansion coefficients in approximately the same extent, and the substrate is kept at approximately a fixed temperature by a radiation effect.

Description

【発明の詳細な説明】 （ａ）　　発明の技術分野 本発明はリードフレームを使用する半導体装置に係り、
特に温度変化に対応可能なリードフレーム構造に関する
。DETAILED DESCRIPTION OF THE INVENTION (a) Technical field of the invention The present invention relates to a semiconductor device using a lead frame,
In particular, the present invention relates to a lead frame structure that can cope with temperature changes.

（ｂｌ　　技術の背景 近年半導体素子は微細加工技術の発展に伴い、＾密度集
積化が進み、チップレベルでは勿論のことパッケージレ
ベルでの高密度化もＮ要な胛題さなっている。パッケー
ジ構造として耐熱性？２Ｒ茫板上ｌこ半導体素子をマウ
ントし、基板素材七同−材のセラミック或は金属材のキ
ャップでハーメチックシール構造とする気密封止形があ
る。これに対し量産的で安価な樹脂封止形があり、マイ
コンを始めとする汎用ＬＳＩに広範囲に用いられている
。この方法はプレス成形された多連のリードフレームに
半導体素子を一度にマウントし、ワイヤボンデングで組
込み、エポキシ系又はシリコン系樹脂で多数個一度にモ
ールドした上で個々に切断分離するものでパッシベーシ
ョン技術の向上や樹脂の改善によって前述の気密封止形
からこの樹脂封止形に移行゛しつ５ある。(bl Technology background) In recent years, with the development of microfabrication technology, semiconductor devices have become more densely integrated, and increasing density not only at the chip level but also at the package level has become an important issue.Package structure There is an airtight sealing type in which the semiconductor element is mounted on a heat-resistant 2R board and hermetically sealed with a ceramic or metal cap made of the same substrate material.On the other hand, it is mass-produced and inexpensive. There is a resin-sealed type that is widely used in general-purpose LSIs such as microcomputers.This method mounts semiconductor elements on multiple press-molded lead frames at once, and incorporates them using wire bonding. This is a method in which many pieces are molded at once with epoxy or silicone resin and then cut and separated individually.With improvements in passivation technology and resin, there is a shift from the hermetic sealing type mentioned above to this resin sealing type5. .

（Ｃ１従来技術と問題点 高密度実装が進むにつれて、素子のパワーが上昇するた
めパッケージの放熱構造が問題さなる。(C1 Prior Art and Problems As high-density packaging progresses, the power of elements increases, so the heat dissipation structure of the package becomes a problem.

また一般に、半導体素子は特性上又は信頼性の点から許
される層高許容温度はシリコン半導体では７５〜２００
℃、ゲルマニウム半導体では７５〜１１０℃である。熱
的に定常状態にある装置の熱特性は熱抵抗という値で表
わされる。例えは電力用又は大電流容量の半導体素子は
一種の発熱体をなすから特性変動を防止するための熱抵
抗を小さくする放熱効果を考慮する必要がある。気密封
止形では放熱フィン、放熱スタッドを設けて放熱効果を
高める手段が取れるが、樹脂封止形では素子が樹脂でコ
ーチングされているため放熱処理はとりにくＧ）。Additionally, in general, the allowable layer height temperature for semiconductor devices from the viewpoint of characteristics or reliability is 75 to 200 for silicon semiconductors.
℃, and for germanium semiconductors, it is 75 to 110℃. The thermal characteristics of a device in a thermally steady state are expressed by a value called thermal resistance. For example, since a power or large current capacity semiconductor element constitutes a type of heating element, it is necessary to consider the heat dissipation effect of reducing thermal resistance in order to prevent characteristic fluctuations. In the hermetically sealed type, heat dissipation fins and studs can be installed to increase the heat dissipation effect, but in the resin sealed type, heat dissipation treatment is difficult because the element is coated with resinG).

特にフィールドが温度項境の悪Φ件下で使用される場合
ＬＳＩ等の大容岸−素子、大型素子を用いる場合、下地
ｔｌ制によって即ち素子と素子を数句けるベース材料と
の熱膨張係数差によっては、ヒートサイクル時にシリコ
ン基板に形成される半導体素子が破壊（クラック）され
る不都合がある。In particular, when the field is used under adverse temperature conditions, when large-scale elements such as LSI, and large-sized elements are used, the thermal expansion coefficient of the element and the base material that increases the number of elements is determined by the underlying TL control. Depending on the difference, a semiconductor element formed on a silicon substrate may be destroyed (cracked) during a heat cycle.

（ｄ）　　発明の目的′ 本発明は、上記の欠点に鑑み、放熱効果を高め熱変化に
よる素子の熱歪を減少させる半導体装置の提供を目的と
する。(d) Object of the Invention In view of the above-mentioned drawbacks, the present invention aims to provide a semiconductor device that enhances the heat dissipation effect and reduces thermal distortion of elements due to thermal changes.

（ｅｌ　　発明の構成 上記目的を達成するために本発明はリードフレームのタ
イステージに半導体素子を搭載し、封止する半導体装置
であって、該リードフレームを銅系部材で形成し、その
グイステージの少くとも素子搭載側に鉄系部材でなる金
属板を取イツけ、該金属板上に該半導体素子を固定する
ときによって達せられる。(el) Structure of the Invention In order to achieve the above object, the present invention provides a semiconductor device in which a semiconductor element is mounted on a tie stage of a lead frame and sealed, the lead frame being formed of a copper-based material, and the lead frame being sealed with a tie stage. This can be achieved by installing a metal plate made of iron-based material at least on the element mounting side and fixing the semiconductor element on the metal plate.

（ｆｌ　　発明の実施例 以下、本発明の実施例を図面により詳述する。(fl　Embodiments of the invention Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

第１図は本発明の一実施例である半導体素子の実装構成
を示す斜視図である。図において、ベリリウム青銅等の
熱伝導率の高い銅系部材で形成されるリードフレーム１
のタイステージ２に４２アロイ等の鉄基部材てなる金属
チップ３をスポット溶接又はシーム抵抗溶接等により固
定する。金属チップ３はグイステージ２と同程度の表面
積を有し、−少くとも半導体素子搭載面もしくは両面に
熔接固定する。リードフレーム１はプレス打抜工程て連
続自動加工され、次いで金属チップ３を自動溶接し更に
金属テンプ３上に半導体素子４をマウントする。半導体
素子４に設けた信号線接続用端子とリードフレーム１の
リード端子５をアルミ又は金で形成するワイヤをボンデ
ンク接続しエポキシ等の樹脂で多数個一度にモールド形
成し、更に（υ断整形されて半導体装置を構成する。FIG. 1 is a perspective view showing a mounting configuration of a semiconductor element according to an embodiment of the present invention. In the figure, a lead frame 1 made of a copper-based material with high thermal conductivity such as beryllium bronze.
A metal chip 3 made of an iron base member such as 42 alloy is fixed to the tie stage 2 by spot welding, seam resistance welding, or the like. The metal chip 3 has a surface area comparable to that of the guide stage 2, and is fixed by welding to at least the semiconductor element mounting surface or both surfaces. The lead frame 1 is continuously and automatically processed through a press punching process, then a metal chip 3 is automatically welded, and a semiconductor element 4 is mounted on the metal balance 3. The signal line connection terminals provided on the semiconductor element 4 and the lead terminals 5 of the lead frame 1 are connected by bonding wires made of aluminum or gold, and a large number of them are molded at once with a resin such as epoxy, and then ( to configure a semiconductor device.

第２図は本発明の一実施例である半導体装置を示す断面
図である。グイステージ２の半導体素子４搭載面に金属
チップ３を熔接固定し、その上面に半導体素子４をマウ
ントする。FIG. 2 is a sectional view showing a semiconductor device which is an embodiment of the present invention. A metal chip 3 is welded and fixed to a semiconductor element 4 mounting surface of a stage 2, and a semiconductor element 4 is mounted on the upper surface.

半導体素子４の入出力端子はワイヤ６を介してリード端
子５に接続され外部入出力信号に鮨気的に結合する。こ
のように構成さ］］る半半導体装置でけ半導体素子４の
発熱は金属チップ３を介して熱伝導率の高いへＩＪ　Ｉ
Ｊウム宵銅等の餉系部利てなるクイステージ２により放
熱される。しかも半導体素子４をなすシリコン基板と下
地素利（／１２アロイ等の鉄系部制）は略回程ｔＶの熱
ｌｉｆ！？張係数であるからシリコン基板は熱歪を受け
るこさなく上述の放熱効果により略一定温度に保たれる
。The input/output terminals of the semiconductor element 4 are connected to the lead terminals 5 via wires 6 and are coupled to external input/output signals in a similar manner. In the semi-semiconductor device configured in this way, the heat generated by the semiconductor element 4 is transferred via the metal chip 3 to a device with high thermal conductivity.
Heat is dissipated by the metal stage 2, which is made of a copper plate. Moreover, the silicon substrate and base material (iron-based material such as /12 alloy) forming the semiconductor element 4 have a heat of approximately tV! ? Because of the tensile coefficient, the silicon substrate is not subjected to thermal strain and is kept at a substantially constant temperature by the above-mentioned heat dissipation effect.

放熱効果は、熱伝導率と表面積に比例するからクイステ
ージ２のフレーム部（第１図２３）の表面積を大とする
ことが望ましい。Since the heat dissipation effect is proportional to the thermal conductivity and surface area, it is desirable to increase the surface area of the frame portion of the Quiz stage 2 (FIG. 1 23).

（ｇ）　　発明の効果 以上、詳細に説明したように本発明の半導体装置とする
ことにより、高密度大容量の半導体素子が実装でき、経
済的な樹脂封止形とすることが可能となる優れた効果が
ある。(g) Effects of the Invention As described in detail, the semiconductor device of the present invention has the advantage that high-density, large-capacity semiconductor elements can be mounted, and it can be made into an economical resin-sealed type. It has a positive effect.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例である半導体素子の実装構成
を示す斜視図、第２図は本発明の一実施例である半導体
装置を示す断面図である。 図中、１　リードフレーム、２　グイステージ、３　金
属チップ、４　半導体素子、訃　リード端子、６　ワイ
ヤ、７−半導体装置。FIG. 1 is a perspective view showing a mounting structure of a semiconductor element according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a semiconductor device according to an embodiment of the present invention. In the figure, 1 lead frame, 2 stage, 3 metal chip, 4 semiconductor element, lead terminal, 6 wire, 7 semiconductor device.

Claims (1)

【特許請求の範囲】[Claims] リードフレームのタイステージに半導体素子を搭載し、
封止する半導体装置であって、該リードフレームを銅系
部材で形成し、そのタイステージに少くとも前記半導体
素子搭載側ζζ鉄系部材でなる金属板を数句け、該金属
板上に該半導体素子を固定してなることを特徴とする３
Ｆ導体装置。The semiconductor element is mounted on the tie stage of the lead frame,
In the semiconductor device to be sealed, the lead frame is formed of a copper-based material, and at least several metal plates made of ζζ iron-based material are placed on the tie stage on the semiconductor element mounting side, and the lead frame is formed on the metal plate. 3 characterized by being formed by fixing a semiconductor element
F conductor device.
JP57171204A 1982-09-30 1982-09-30 Semiconductor device Pending JPS5961154A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57171204A JPS5961154A (en) 1982-09-30 1982-09-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57171204A JPS5961154A (en) 1982-09-30 1982-09-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5961154A true JPS5961154A (en) 1984-04-07

Family

ID=15918947

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57171204A Pending JPS5961154A (en) 1982-09-30 1982-09-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5961154A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4599120A (en) * 1985-02-25 1986-07-08 Brush Wellman Inc. Processing of copper alloys
US4953005A (en) * 1987-04-17 1990-08-28 Xoc Devices, Inc. Packaging system for stacking integrated circuits
WO1999044234A1 (en) * 1998-02-27 1999-09-02 Robert Bosch Gmbh Lead frame device and method for producing the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4599120A (en) * 1985-02-25 1986-07-08 Brush Wellman Inc. Processing of copper alloys
US4953005A (en) * 1987-04-17 1990-08-28 Xoc Devices, Inc. Packaging system for stacking integrated circuits
US6528868B1 (en) 1998-02-21 2003-03-04 Robert Bosch Gmbh Lead frame device and method for producing the same
WO1999044234A1 (en) * 1998-02-27 1999-09-02 Robert Bosch Gmbh Lead frame device and method for producing the same
KR100730906B1 (en) * 1998-02-27 2007-06-22 로베르트 보쉬 게엠베하 Lead frame device and method for producing the same
DE19808193B4 (en) * 1998-02-27 2007-11-08 Robert Bosch Gmbh Leadframe device and corresponding manufacturing method

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