JPS5957576A - Picture data compressing circuit - Google Patents

Abstract

PURPOSE:To process a picture having many changing picture elements, by providing some circuits to a variable length coding circuit in a data compressing circuit and providing a function of 2-bit and 1-bit shift so as to decrease the processing time. CONSTITUTION:Mode information of a black-and-white changing picture element discriminated at a mode detecting circuit is inputted as an address for an ROM 31 for variable length code storage and an ROM 22 for code bit length storage. The variable length code is read from the ROM 31 to a signal line 33 and the bit length of the variable length code is outputted from the ROM 22. Further, the variable length code from the signal line 33 is inputted to a shift register 35 through a multiplexer 34. Moreover, a data transfer enable signal 39 from a mode detecting ciruit is inputted to a variable code forming control circuit 40, which controls a counter 37, an FF38, the multiplexer 34, and shift registers 35, 41 and the like. Then, the multiplexer 34 and the registers 35, 41 form a parallel/serial conversion circuit having 1-bit or 2-bit shift function to reduce the processing time.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF THE INVENTION The present invention relates to a 1lfii high speed facsimile (e.g. 1 second
, AX), etc., and relates to an image data compression circuit that can perform high-speed processing especially when the bit length of a variable length code is S long. (2) Prior art and problems For long codes, the compressed data is shifted one bit at a time according to the bit length of each code. create.

An example of a conventional variable length encoding circuit designed based on the above idea is shown in FIG.

In FIG. 1, the arrow 3 shown in English letters represents the flow of data, and the arrow shown with a broken line represents the control signal. Each signal is output from a mode detection circuit located before the variable length encoding circuit.

11 is a variable length encoding circuit OM, 12 is a code bit length storage ROM, t3 is a variable code creation control circuit, 16.23 is a shift register, IFI, 24 is a counter, 26 is a latch, 10, 1 rl, 15, 17, 19,
20.

21 and 22 are signal lines.

The control signal 10 detects black and white change pixels on the reference scanning line and the encoded scan line, and determines the state of the change pixel. The output from the mode detection circuit for determination is broken. In this case, modified read (pass, vertical in Ml method).

Horizontal (including white and black run length?) mode is control signal 1
0 a'. Therefore, the encoding method specification in the MR system will be explained using Figure 2 (al, (bl).

Figure 2 (hl, (1) 45 in l, the shaded area is black pixels, the blank area is white pixel 1, upper 13s reference scanning group (1)
l, ), and the lower side is coded scan green (CI, ). bus,
The vertical and horizontal modes are determined by the relative positions of white and heat change pixels on CL with respect to white and black change pixels on PL. Gozu εB2 Figure fa) Let's start with the bass mode using sound. ao is CI, the reference or origin change pixel above, a
l is a on CL. The first change pixel further to the right, bI is P L, above a (, further right AI) a, and the opposite color r
The first pixel of change, b2, is on the PL, and is the first pixel of change further to the right. a on CL is detected fi
When both bI and b2 force 3 are detected in lJ, it is in bus mode.

In Figure 2 (1)), identical numbers are intended to indicate agreement.

Here, liquefied IT on CL! ] l cumulative "I++" I distance a
Distance VIIta+ between oa+ (4 pixels) and al, a2
12 (L 1 pixel), horizontal mode II
(4, 11).In the MR method, CLJ: is fully encoded at the relative position to the changed pixels S, , b on PL, so in this case, a.

Distance of b, a, b, and b2+ Distance of a2 V+'f=
”2, l) 2 te encoding, the vertical mode V(a,
b. Control signal lO corresponding to vertical and horizontal modes is also OM for variable length code storage.
II and the address of 1tOM 12 for storing the code bit length.

Then, the variable length code corresponding to the control signal 10 and the length of the code y1 are outputted as OMII and 12, respectively.

First, the variable length code creation control circuit 13 generates a variable length code (signal 115) that has a full access time of KX>111.12, in accordance with the data transfer possible (in other words, encoding possible) signal 14 from the mode detection circuit at the previous stage. 'e Shift register 16, sign bit length (signal door 17) t counter 1
8tC1g+- command (control error number 19,
20). When the code bit length loaded into the counter 18 becomes 0 (monitored by the multiplier 21), the counter 8 is counted down.

And shift register for the countdown number】6
By performing the shift, a serial variable length code is output (signal line 22). The shift register 23 works in conjunction with the shift register 6 to take in its output (signal line 22) and shift it. Then, each time the counter 24 reaches a certain value (for example, when performing 8-bit parallel transfer, a value of 8 corresponds), the parallel variable length code data (signal line 25) from the shift 1 register 23 is sent to the latch 26. Performs loading/draining and parallel data transfer with the next stage.

Next, the case of encoding the entire stepped pattern as shown in FIG. 3 will be explained with reference to FIGS. 4 and 5. Figure 3 1dl)X
A portion of the image data is shown using the same groove structure as in Figure 2. FIG. 4 shows a three-part configuration of the image data compression circuit. 1.3.5 is a register for vibe line processing of the image data compression circuit, 2 is a mode detection circuit,
This is the same as the mode detection circuit described in FIG. 4 is a 110M circuit for variable length codes, and 1.4 for storing variable length codes in FIG. Corresponds to UM and code bit length storage IiLOM. Reference numeral 6 denotes an oJ variable-length encoding circuit, which corresponds to the shift register, count, and variable-length code creation control circuit in FIG. FIG. 5 is a diagram showing the operation timing of the three circuits in FIG.
l is the basic clock, FIG. 5 [BL is the mode detection circuit, FIG. Figure 5 (al, ib), tc!, (di
, the time axes are the same, 'I + '2 + 'R are also at the same time, and the shaded part is a cycle to be cleared internally.

At time t of the fifth fbl, the mode detection circuit 2 detects the third
The first changed pixel 2 on CL in the figure is determined to be V u (3), and at the same time as the internal clear (pulse indicated by diagonal lines), it is determined to be VR (3) to the variable length code ROM circuit 4, and the full f control signal is output. . Moreover, at time t in FIG. 5 tc+, the variable length code R
The OM circuit 4 receives a variable length code corresponding to the control signal full input type Vn(3) of the mode detection circuit 2 and a variable length code Biy'.
r length? It is output to the variable length encoding circuit 6. Time t of the fourth cycle following FIG. 5 fbl! Then, the mode detection circuit 2 again determines that the changed pixel is pregnant Vn(3), and the variable length code ILOM circuit 4 operates in the same manner as described above. I apologize for the time t1.
However, here, as shown in FIG.
Is it variable length code ROM times? 64 signals are input and shifted by J bin 1. Assuming that the code of Vn(3) is 7 bits, it takes 7 cycles to complete the entire bisoton 1. In reality, it takes 9 cycles because it requires time for internal clearing and time to fully determine whether data transfer is possible. The mode detection circuit 2 determines the next changed pixel after 4 cycles, but
Because pipeline processing is performed, t13+ in Figure 5
, I ended up having to wait 4 cycles as shown in tdlK.

As mentioned above, in the conventional variable length encoding circuit, the entire data is shifted one bit at a time, especially when the code bit length is long.
It takes time to create the code, and data transfer with the mode detection circuit in the previous stage is delayed. As a result, there is a drawback that the processing of the entire image data compression circuit becomes slow.

(3) Object of the Invention In view of the above-mentioned conventional drawbacks, the object of the present invention is to shift code data by 2 bits in two ways, 1 pino l-4XJ, in a variable length coding circuit in an image data compression circuit. Therefore, it is an object of the present invention to provide an image data compression circuit that can perform efficient high-speed processing while reducing the processing time of a variable length encoding circuit by seven points.

(4) Structure of the Invention The purpose of the invention C is to provide a system in which a variable length code for image data compression is penetrated or read from an ILOM for storing variable length codes and an ILOM for storing variable length codes. Data tray 1
A parallel-to-serial conversion circuit having a bit or two-bit (shifting) function and a counter for controlling the number of shifts of the parallel-to-serial conversion circuit in accordance with the code bit length read from the code bit length storage 1tOM. This is achieved by providing an image data compression circuit.

(5) Examples of the invention EMBODIMENT OF THE INVENTION Hereinafter, an exemplary embodiment of the present invention will be explained in detail with reference to the drawings.

FIG. 6 is an example of a disaster in the variable length encoding circuit according to the present invention. 3 in the i6 diagram, 31 is 1% OM for variable length code storage
, 32 is a ROM for storing code bit length.

34 is a multiplexer, 35.41 is a shift register,
37.42 is the counter, 38.43 is the fill flow ν
40 is a variable length code creation control circuit, 44 is a latch, 3
0,33.36-1.36-2.39 is a signal set.

Here multiplexer 34 and shift register 35.41
This applies to the parallel-to-serial conversion circuit described in the claims. Further, the solid line and the broken line have the same meaning as in FIG. 1, and both signals are outputted from the mode detection circuit in the preceding stage of the variable length encoding circuit.

First, the mode detection circuit in the previous stage determines the mode (bus, vertical, horizontal) information of the two black and white changing pixels. , variable length code storage box 0M31 and code bit length storage tLOffl,
+32 address (signal line 3()).

Corresponding to the MoIJ information, a variable length code (signal line 33) is output from the publication 01'vi3L, and the bit length of the variable length code is output from the ROM:+2 (signal set 34). However, the signal line 33 is described as 4 bits (4 bits), but this is to simplify the explanation of the circuit operation later.
In fact, the MIt code is of the order of 28. The signal set 33 is input to a 7-foot resistor 35 through a multiplexer 34. Incidentally, multiplexer 34F, 1: plays a role of switching the input bit shift data and t.

For example, 4-bit data "0 1 1 Q" is sent to the multiplexer 3 by the variable length code storage box OM31.
A of 4 (fill manually and output from there to the shift register 35. IA, 2A of the multiplexer 34
The input “0” and “1” are directly output to the 2-bit simultaneous shift register 41. 1″ m input to 3A and 4A of multiplexer 34 L to O+l
lT of the multiplexer 34 from the shift register 35 again.
3, 213, and from there two bits are simultaneously output to the shift register 35. As above,
Count 1 to 2 bits at a time.

7″l: The signal group 36 is divided into 36-1 and 36-2,
Signal set 3 (i-11-1: the second or higher bit from the lowest bit of the code bit length expressed in binary number, digit number 2
Bit shift is applied. The signal line 36-2 is connected to the least significant bit of the same code bit length, that is, the odd number is even I! 1. This is a bit representing FF, and is input to the Flinopf D bit (hereinafter referred to as FF) 38.

Next, upon receiving the data transfer enable signal 39 from the mode detection circuit, a command is sent from the variable length code creation control circuit 4o to the shift register 35 to load the entire variable length code and the code bit length into the counter 37 and li'l'' 3B. Calculate the number of times to shift 2 bits from the output of C loaded counter 37, even or odd from the output of Fl" 38 (this will cause the last bit shifted by 7 to be sent by a 2-bit shift or by a 1-bit shift. (The output of the omniscient p1 counter 378 and FF3B becomes 0.) The count + counter type zero shift register 35.41i2-bit shift and l-bit shift are performed. In addition, in the case of 2-bit shift, is there a shift register load function? use.

For example, outputs 3 and 4 of the shift register 35 are input to 1 and 2 through the multiplexer 34 and loaded into the shift register 41, thereby performing a 2-bit shift function in one cycle. However, is the multiplexer 34 a variable length code? )LO
1 except loading from M31 to 7ft register 35
3 (No. i (signal for 2-bit shift) is fully selected.

The shift register 411-i is connected in series with the subsequent stage of the image data compression circuit (the transmission buffer memory or transfer control unit in ψ11 and FA.X) to make data transfer ineffective.
Plays the role of parallel converter Z1. Counter 42 and FF
43, the number of shifts in the shift register 41 is fully turned on, and when the shift register 41 is filled with data, the number of shifts in the shift register 41 is
4 is loaded with the parallel outputs of the shift register 41. Note that the counter 42g and FF43, like the counters 37 and F"F'38, have a 2-bit shift number and a 1-bit R
The role is to count k.

In Figure 5, there is a problem when performing parallel transfer, but if the shift register 4 1 0) 2'i becomes data tag 15 j[q, and then a 2 bintonft command is made I).

In other words, in the case of a code length of 7 bits as in the case of Motosanio, after the first 4-bit parallel transfer, the shift register 41
(/.) 3', 4' are shifted by 2 bits from the shift register 35 and the next data is sent.

The remaining 1 bit is shifted from shift register 35 to 41, resulting in a state in which data is missing in 1'. If a command to shift 2b comes here, the data in 2' will protrude. Therefore, the values of the counter 42 and ■゛A 43 are n-1 (n: parallel transfer focus number,
In this case, if n=4), that is, 3, and the next 2-bit shift is to be performed, the shift is forcibly switched to 1-bit shift. Therefore, counter 37 and F. F38? -t2 Appropriate carry down function S is provided so that a 1-pitch 1' shift can be performed even in the middle of a bit shift.

Above, - variable length encoding circuit? What is the operation timing of the image data compression circuit when all the image data shown in Fig. 3 is processed using The reduced circuit for image data shown in FIG. 7 is the same as the conventional circuit (FIG. 4): mode detection circuit 2, code 11,
Achieved by three circuits: M circuit 4 and variable length encoding circuit 6, and uses by-buf-in processing for data transfer. I am using it. Also, in Figure 7 (except for the point that (J) is 6 cycles, ・T7
As a proof of the figure, Figure 7 is the same as Figure 5. 9s/f of conventional circuit
3 cycle processing is faster for both Kur and 11C.

Furthermore, the present invention is applicable not only to the vertical mode but also to the long Mil. (Modifier) The quality of the synlenx code (j[i has a similar effect.

(7) Effects of the Invention According to the present invention, there are two or more circuits in the variable length encoding circuit in the image data compression circuit. Additional 2-bit and 1-bit shift functions? Processing time by letting it last? Since it can be shortened, images with many changing pixels corresponding to long code bit lengths (in other words, rough images with poor compression ratio)
It is particularly effective for high-speed processing.

[Brief explanation of drawings]

@1 is a diagram of a conventional variable length encoding circuit vil--it is not necessary to explain it, Figure 2 is a diagram for explaining the entire encoding by the M method, and Figure 3 is a diagram explaining conventional circuit 2 and the circuit of the present invention. A 3-dot 4σ checkered pattern was used in one image pattern
Figure 4 shows the success of the three circuits of the image data compression circuit.
FIG. 5 is a diagram for explaining the operation timing of the image data compression circuit (three circuits) when a conventional variable length encoding circuit is used, and FIG. 6 is a diagram for explaining the variable length encoding circuit according to the present invention. Figure 7 shows the operation timing of the δ image data compression circuit using the variable length encoding circuit according to the present invention.
l 2 , 32 is code bit length storage OM, 38.4
3 is a Filinopf Oypu and parallel-to-serial conversion circuit? 16, 23, 35. 41 is a shift register, 1
8, 21, 37, and 42 counters, and 34 is a multiplexer.

Claims (1)

[Claims] Variable length code power for image data compression 5 ROM for storing variable length code penetrated, η for storing code bit length in which the bit length of the variable length code is omitted, OM, and 11 for storing the variable length code ．． A parallel-to-serial converter circuit having a function of shifting 1-bit data read from OM by 1 bit or 2 bits, and a shift number tone of the parallel-to-serial converter circuit;
This image data reduction circuit is characterized by being equipped with a counter for storing the code period length and controlled according to the code period length read from the OM.