JPS595359A - Queuing method of input/output instruction - Google Patents

Abstract

PURPOSE:To shorten a queue-processing time, and to reduce the burden of a CPU, by providing a table for controlling a queue of an input/output instruction on a channel processor side. CONSTITUTION:An input/output instruction is supplied from a central processor CPU to a input/output devices DV connected to the lower order of each channel CH through a channel processor CHP for controlling plural channels CH. A queue control table which can stack plural input/output instruction is provided on the channel processor CHP side. Whenever an input/output instruction is outputted from the central processor CPU, a necessary matter is inputted to the queue control table. When a dequeue request exists, execution of a processing waiting input/output instruction is started from its head by giving access to the queue control table.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for queuing input/output commands issued by a central processing unit to input/output devices.

Technical background The input/output command used for data exchange between the CPU (central processing unit) and 10 (input/output equipment) is issued from the CPU, but this command is issued by the specified I/O The reception will only be accepted if it can be used, so
As the frequency of use of a channel or lb increases, the instruction acceptance probability decreases. If an I/O command is not accepted and is bounced back to the CPU, the CPU must reschedule and reissue the I/O command many times until a channel or 16 becomes available and the request can be accepted. However, this reduces the inherent computing power of the CPU, so generally a queuing method is used in which the instruction is stacked if the channel or LB is in use, and the instruction is executed when the corresponding IO becomes free. .

Conventional technology and problems: The conventional queue stack for input/output instructions has a subchannel corresponding to a device in the main memory, and it is placed in that subchannel, and a pointer is placed in the subchannel. is normal. However, since this method requires accessing the main memory each time, it has the disadvantage that it takes time even if processing is performed on the channel side.

OBJECTS OF THE INVENTION The present invention attempts to shorten the queue processing time by placing the stack necessary for queuing on the channel side.

Structure of the Invention The present invention is a system in which input/output instructions are given from a central processing unit to input/output devices connected to lower levels of each channel through a channel processor that manages a plurality of channels. In a queuing method that temporarily stacks input/output instructions when The system is characterized in that necessary items are imported into the table, and when there is a dequeue request, the table is accessed to start execution of the processing input/output instruction from the beginning. Explain in detail.

Embodiment of the Invention Figure 1 The following figures are diagrams showing an embodiment of the present invention. Figure 1 is a table QCB showing how many input/output instructions from the CPU are stacked on the channel side and in what order. (Q
UEUE CONTROL BLOCK). If there are many queues, a plurality of tables QCB may be provided, and they can be deleted when unnecessary. One QCB has 16 elements #0 to #15
Equipped with Of these, elements #l to #15 are parts that stack queue information regarding 15 input/output instructions;
Element #0 is a part that manages those elements.

If there are multiple QCBs, the #0 element of the first QCB contains information regarding the control of the entire QCB. Element #0 is the QB, QC as shown.

It consists of NQP, BQP, DQP, and QP, and its queuing bit QB has a 16-bit configuration.
5 bits indicate whether or not each of elements #1 to #15 is waiting for dequeue. , the 0th bit corresponds to the #0 element, but this element is Q
Since this is for CB control and no queue is created, it is not used, specifically, it is set to 0. When the input/output command that has been waiting is executed, the inverse data of the mask data M A and S K in the relevant element is ANDed with the queuing bit QB, and the element is dequeued (the corresponding bit of QB is set to 0). ″
), the queue count QC indicates the total number of currently queued instructions (if there are multiple QCBs, the number of queues for all QCBs), and when a new instruction is queued, it is +1, and when it is dequeued, it is -1. . The next QCB pointer NQP has queues in all elements #l to #15, and one
If there is a sixth or subsequent queue, the next table QCB is created, and the address of that QCB is shown. In this way, multiple QCBs are chained. In this case, the back QCB pointer BQP indicates the previous QCB address.These QCB chain pointers NQP and BQP are fixedly set in advance as in the local storage where multiple QCBs are created, which will be described later. QP is a queue pointer that indicates up to which elements are queued, and is not necessarily required when the current QCB number (
QCB number in the order of instruction execution in TJA) and QCB
It consists of the inner queue count QC.

When this queue pointer QP is newly queued, the corresponding element bit of the queuing bit QB turns on (“1”), and as a result, the queue count QC increases.
By being 1, it becomes QP+1. Conversely, DQP is a dequeue pointer indicating up to which element has been dequeued, and is similarly composed of the QCB number and the intra-QCB queue count QC. When this dequeue pointer is newly dequeued, the corresponding element bit of the queuing bit QB is turned off (10''), and as a result, the queue count QC is decremented by 1, resulting in DQP-1. Anything above 0 is for management. This is about element #0.

The configuration of QCB elements #1 to #15 is startup information, 1
6 machine number, CAW, CHP path information, ucW address, and mask data. The startup information is the information when the CPU starts it, and it includes bit 0 (Block multi) of the control register CRO on the CPU side.
plexlng bit) or the EC mode bit in the program status word PSW. The number 10 is the device number specified at startup,
It is also used when trying to connect to another path using CHP (channel processor) path information. UCW address is 1
Indicates the start address of UCW corresponding to machine number 0. This is 16 bits and consists of channel address CIA, control unit address CUA, and device address DVA.

FIG. 2 is an explanatory diagram of the idle loop of the channel processor CHP. As shown in FIG. 5, the CHP is a management and control processor located above a plurality of channels CH, and operates on an independent microprogram. A control unit CU is connected to the lower level of each channel CH, and each device (i/δ) DV is connected to the lower level of each channel CH.
is connected. MS is the main storage. Figure 6 shows the details of the channel processor CHP, where LS is a local strange storing table QCB, etc., and C8 is a second
REG+ is a request register, and A/S is an adder/shifter, which is a control storage containing programs such as the idle loop shown in the figure and queue processing and dequeue processing to be described later.

The program in the channel processor CHP is always running in an idle loop in C8, and constantly monitoring whether there are any requests. As shown in FIG. 2, the idle loop includes functions for determining the presence or absence of CPU activation, the presence or absence of a dequeue request, and the presence or absence of a channel interrupt request, and if there is no request, the program simply passes through these and cycles. C
When the input/output instruction 5iOP is issued from the PU, the CPU0 activation bit in the request register REG+ is turned on, and the C
Since program No. 8 is monitoring this, it immediately starts processing. At this time, the CPU sends the EC mode pit of Psw to bit 0 of control register ORO (
block multiplexing bit)
, 16 machine number (starting machine number), etc. are sent, and these are taken into the X and Y registers. With the activation bit of register REG1 turned on, the CHP fetches the channel address word CAW from the main storage MS, checks the format, and then checks the empty queue.CC
-0 response (the meaning of which will be explained later) releases the connection with the CPU. Thereafter, the table QCB is checked and the activation information is set in the empty element indicated by the queuing bit QB. At this time, both the queue count QC and the queue pointer QP are incremented by 1, and the corresponding element bit of the queuing bit QB is turned on to complete the queue processing. This QCB is created using X, Y registers, adder shifter A
/S and LS work areas are used. 5sop
If it is not a command, processing of the command begins. When processing 10 is completed, when the control unit CU becomes free, or when the channel CH becomes free, the dequeue processing is started, and at the same time the processing is performed, the waiting processing 16 is activated. The channel interrupt handling routine processes the request if there is one, otherwise it passes through.

FIG. 3 is an operational flow of queue processing by the channel processor CHP. However, to simplify the explanation, it is assumed that only one set of table QCB is set. Therefore, the queue count QC is for queue elements #1 to #15.
If the number of commands has reached 15 (QC>15), no new input/output commands can be accepted, so the condition code is set to CC=2. This indicates that the channel is busy and tells the CPU to reissue the instruction. After setting, the connection between CHP and CPU is released (CP
U release). If QC≦14, main storage M
CAW (
channel address word). If the result of the CAW format check is defective (NG), it is set to CC-1 (which indicates a defective program check result), the program check is reported, and the process ends. If it is OK, it is set to CG-0 (which indicates normal reception) and the CPU is released. Next, it is determined whether the queue pointer QP is 0. QP-0
cannot be used as a queue because it points to management element #0.5 At this time, queue pointer QP is set to 1, and queue creation is started from element #1. If QP≠0, the activation information, CAW, etc. shown in FIG. 1 are set in the element indicated by the pointer value.

Next, in order to indicate that the element, for example #4 in FIG. The logical sum of the input bits QB (in this case, including the 0th bit is treated as 16 bits) is taken, and the result is set to QB. QB-QBVMA
SK (QP) is a processing step indicating this. Thereafter, to indicate that the number of queues has increased by one, the queue count QC is incremented by 1, and the queue pointer QPO value is incremented by 1.

FIG. 4 is an operational flowchart of dequeue processing by the channel processor CHP. In this case, the queue count is always Q
The value of C is monitored, and if QC=0, it ends (end
), it is simply expressed as moving to dequeue processing if it is QC#0, but in reality it starts upon receiving activation with a dequeue request, and if the queue is not accumulated (QC=O)
It means to bypass. If the dequeue pointer DQP is 0 when a dequeue request is received, it is set to 1 for the same reason that if QP=0 in FIG. 3, it is set to 1. If the contents of the dequeue pointer DQP are changed within the table QCB, the contents may be destroyed, so the contents are copied to the work area WORK (see FIG. 6) and changed there. DQPW points to the dequeue pointer copied onto the work area WORK. Then, based on the dequeue pointer DQPW on this work area, the queuing bit QB and mask data MASK (DQPW) are checked bit by bit. That is, DQPW has a 16-bit configuration in which only the next processing target remains 1 (5 bits are 0), and this is ANDed with QB one bit at a time.

If the check result is OFF (OFF), there is no queue in the corresponding element, so add 1 to DQPW.

This result is DQP7 (if QP<DQP, it is normal, but if QP2:DQP, so the value of queue pointer QP is greater than or equal to the value of dequeue pointer DQP, it is an error and is handled as an error.On the other hand, the queuing bit QB
If the check result between the bit and the mask data MASK (DQPW) bit is ON, the element information corresponding to that bit is taken out from the table QCB and the corresponding io is activated.

When the startup is completed normally, it is determined whether the dequeue pointer DQPW of the work WORK and the dequeue pointer DQP on the table QCB match. If startup does not end normally, add 1 to pointer DQpw and set QP<DQ.
Determine PW, if Yes, end, if No, OB-MAs
The process returns to the decision block for K (DQPW) and enters the next queue process.

In other words, in this case, starting the next processing target does not go well, so we skip one and start processing the next target, and if this also does not work, we start the next one, and if it does not work until the end, there is no target and it ends. . Startup is completed normally and DQPW=
If it is DQP, pointer DQP on table QCB
The mask data MASK (DQP) is inverted, and the logical product of it and the queue ink hit QB is taken, and the result is written to QB again. Now, the element bit dequeued by the queuing bit QB becomes 0.

If DQPW≠DQP, mask data M in DQPW
Similar processing is performed using ASK (DQPW). Thereafter, the queue count QC is decremented by 1 and the process ends. In this example, when there is a dequeue request, the next queue is processed and the end is reached, but all remaining queues may be processed and the end is reached.

If such a table QCB called a queue control block is provided on the channel processor CHP side (in the local strange LS in the example of FIG. 6), it is not necessary to access the main storage MS each time, so that processing time is shortened. For example, if it takes lμs for one CHP to access an MS once, then in a system with multiple CHPs or CPUs, these combinations must be taken into account. Considering this, 1.1, u S etc., and since it has to be accessed every time, it becomes n times that amount. On the other hand, if the present invention is used, the CHP will have its own L
Since it is only necessary to access within S, the time for one access is shortened to about 80 nS.

Effects of the Invention As described above, according to the present invention, since a table for managing the queue of input/output commands is provided on the channel processor side, the queue processing time is shortened and the load on the CPU is reduced. And since the recent trend is for channel processors to be microcoded and given intelligence, queue processing by channel processors is easy. Furthermore, as in the present invention, if input/output commands are incorporated into a queue table and the connection with the CPU is quickly released, the load on the CPU can be reduced as much as possible and the CPU can fully demonstrate its high performance.

[Brief explanation of the drawing]

1 to 6 are diagrams showing one embodiment of the present invention, in which FIG. 1 is an explanatory diagram of a queue management table (queue control block), FIG. 2 is a flowchart showing an idle loop of a channel processor, and FIG. Figure 3 is a detailed flowchart of queue processing, Figure 4 is a detailed flowchart of dequeue processing, Figure 5 is a schematic block diagram of the entire system, and Figure 6 is a detailed flowchart of queue processing.
The figure is a block diagram of a channel processor. In the figure, CPU is the central processing unit, MS is the main storage, CHP is the channel processor, CH is the channel, and DV
is a device (input/output equipment), C8 is a control storage, LS is a local strange, and QCB is a queue control block (queue management table). Applicant Fujitsu Ltd. Representative Patent Attorney Minoru Aoyagi 3rd figure

Claims (1)

[Claims] A system in which input/output instructions are given from a central processing unit to input/output devices connected to lower levels of each channel through a channel processor that manages multiple channels, and when a specified channel or input/output device is in use, In a queuing method in which instructions are temporarily stacked, a queue management table capable of stacking multiple input/output instructions is provided on the channel processor side, and required information is written to the table each time an input/output instruction is issued from the central processing unit. A method for queuing input/output instructions, characterized in that when there is a request for fetching and dequeuing, the table is accessed to start execution of input/output instructions waiting to be processed from the beginning.