JPS5951624A - Initial set circuit - Google Patents

Abstract

PURPOSE:To reduce the non-initial set time and to attain sure initial setting, by applying an output of an oscillating circuit to a mode set terminal of an integrated circuit by a prescribed time only via a time and level set circuit from the power-on of the integrated circuit. CONSTITUTION:The time/level set circuit comprising an oscillating circuit 41, a tri-state buffer circuit 42, a time constant circuit 43, and a pull-up resistor 44 is provided between an IC power supply Vcc and a mode set terminal 40 of an IC circuit 10. When the power supply Vcc is applied, the circuits 41, 43 are started and after a pulse signal is applied to the terminal 40 for a prescribed time, the terminal 40 is fixed to a level of logical 1 with the resistor 44. The waveform of an input signal to the terminal 40 is shaped at a Schmitt trigger buffer 32, and its output is applied to an in-phase delay circuit 33 delaying it for a prescribed time, an exclusive OR circuit 34 and a mode switching circuit. A power-on reset pulse is generated from the circuit 34 at each pulse and the IC10 is set initially with the pulse.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an initialization circuit that initializes internal circuitry when the power of an integrated circuit is turned on.

Prior art and problems Generally integrated circuits (hereinafter referred to as IC), especially digital I
In C, it is necessary to initialize the inside of the IC (power-on reset) when the power is turned on.

Conventionally, this initial setting is for example IC1 as shown in FIG.
0 is provided with an initial setting dedicated terminal RPi:SET, and the rc power supply voltage VO is connected to this terminal via an external circuit (integrator circuit) 11.
0 is applied so that a voltage waveform with a gradual rise is applied to the initial setting dedicated terminal RESET as shown in FIG. 2, and this voltage waveform and reset detection level 8L are
By comparing the signals inside the C, a seratonolus is generated as shown in FIG. 2, and this is realized by supplying it to the inside of the ICC.

Here, the terminal exclusively for initial setting is literally a terminal exclusively used for this purpose and cannot be used for any other purpose.

Therefore, the present inventor filed an earlier application (Japanese Patent Application No. 57-61328).
No.], such a terminal dedicated to initial settings is not provided.
We proposed an initial setting circuit that can reduce the number of C terminals. This was done by focusing on the fact that some types of ICs have ZIli pins that are fixed at high level (“1”) or low level (“0”) like mode setting terminals, and are shown in Figure 3. As shown in , the terminal 30 is finally connected to “
1" or "0°', and generates a transient signal wave that changes from the opposite level to the fixed level when the power is turned on, and is provided inside the IC and applied to the terminal 60. A waveform shaping circuit 32 that shapes the waveform of a signal, and an output and in-phase delay circuit 36 of this waveform shaping circuit.
The output of the waveform shaping circuit 52 is used as a fixed level signal such as a mode switching signal, and the output of the exclusive OR circuit 34 is used as an initial setting reset pulse. This is what I did.

By the way, the method for performing initial settings as described above is
In contrast to the level reset method, it is generally called the edge reset method, but in this edge reset method, the time T (hereinafter referred to as non-initialization time) from when the power is applied until the initial settings are completed is as short as possible. is desirable. This is because during the non-initialization time, both the internal state and the external output state are unstable, and depending on the intended use of the IC, there is a risk that erroneous output may cause problems with the cinema. For example, when an IC is used as the output buffer 1 of an engine control microcomputer, there is a risk of erroneous ignition of a spark plug or accidental ingestion of gasoline. In order to shorten the non-initialization time with the configuration shown in Figure 3, it is good to set the time constant of the time constant circuit 51 to a small value, but if it is made too small, the reset will not take place due to the influence of the 9-hour rise and fall of the power supply VOO. A situation may arise.

OBJECTS OF THE INVENTION The present invention solves these problems, and its purpose is to provide an initialization circuit that can shorten the non-initialization time and perform initialization reliably.

Structure of the Invention In order to achieve the above object, the initial setting circuit of the present invention has the following features:
The time constant circuit 61 in FIG. 3 is an oscillation circuit, and the output of this oscillation circuit is applied to the terminal 30 for a predetermined time from when the integrated circuit is powered on, and then this terminal is fixed at either a high level or a low level. This is a modification to a time/level setting circuit.The embodiment will be described in detail below.

Embodiment of the Invention FIG. 4 is a block diagram of essential parts showing an embodiment of the invention. Between the IC power supply VCO and the mode setting terminal 40, a time/level setting circuit consisting of an oscillation circuit 41, a dry state NOR circuit 42, a time constant circuit 43, and a pull-up resistor 44 is provided. The oscillation circuit 41 is connected to the IC power supply VO.
It generates a constant cycle pulse signal at the same time as O is turned on, and its output is input to the tri-state buffer 7 circuit 42. The time constant circuit 46 sets its output to "1" for a predetermined period of time after the IC power supply VOa is turned on, and during that time the dry state circuit (horn 1 circuit 42) is enabled.The mode setting terminal 40 is This is for externally setting the operating mode of IC10, and is a 6L "1'" terminal that is required when one IC is used for several types of purposes.
' or "0". Note that a mode setting terminal 4 is provided inside the IC 10 as shown in FIG.
Trigger buffer 1 that shapes the waveform of the 0 input signal
62, an in-phase delay circuit 33 that delays its output by a predetermined time, and an exclusive OR circuit 34 that takes an exclusive OR of this output and the output of the 7-unit trigger back 132. The outputs of 1 and 2 are output to a mode switching circuit (not shown), and exclusive OR circuit 6
The output of No. 4 is supplied to each part within the IC as a reset pulse for initial setting.

FIG. 5 is a diagram showing an example of signal waveforms at various parts when the circuit shown in FIG. 4 is operated. When the IC power supply Voo is turned on, the oscillation circuit 41 and the time constant circuit 45 are activated, and a pulse signal is applied to the mode setting terminal 40 for a predetermined period of time after the power is turned on, and then becomes "1" by the action of the pull-up resistor 44. Fixed. When a pulse signal is applied to the mode setting terminal 40, a power-on reset pulse is generated from the exclusive OR circuit 64 for each pulse, and the IC 10 is thereby initialized. In this case, the IC 10 will be initialized multiple times, but the internal and external states will be established upon initialization by the first valid initialization reset pulse. Therefore, if the oscillation period of the oscillation circuit 41 is, for example, 1 μs, it is possible to initialize it within at least several fi8.

The above embodiment is for the case where the mode setting terminal 40 is fixed to "1", and the mode setting terminal 40 is fixed to "1".
When fixing at O゛', use the sol-up resistor 4 in Figure 4.
4, for example, a pull-down resistor 6 as shown in FIG.
You can use 0. FIG. 7 is a diagram showing an example of the signal waveform of each part when the circuit shown in FIG. .

FIG. 8 is a circuit diagram showing still another embodiment of the present invention, and shows an example in which the configurations of FIGS. 4 and 6 are realized by a combination of inexpensive parts. In the figure, 80 is a transistor, 81 is a resistor, and 82 is a capacitor, which constitute a time constant/gate circuit that controls the time during which the oscillation pulse of the oscillation circuit 41 is applied to the mode setting terminal 40 of the IC 10. Further, 83 is a transistor, 84 and 85 are resistors, which constitute a sofa circuit, and 86 is a mode changeover switch.

When the mode selector switch 86 is set to the mode 1" side, the mode setting terminal 40 is finally fixed to "1" by the pull-up resistor 84, and when the mode switch 86 is set to the mode 0" side,
After a predetermined period of time has elapsed, the mode setting terminal 40 is grounded (“0”) via the transistor 80 which remains on. Note that the configuration is simplified by using the oscillation circuit 41 and the oscillation circuit originally required for generating the master clock of the IC 10.

Effects of the Invention The present invention provides an oscillation circuit and an output of the oscillation circuit when the RC power is turned on, in an initial setting circuit for an integrated circuit having a terminal that fixes the input signal level to either the noise level or the low level. a time/level setting circuit that applies voltage to the terminal for a predetermined period of time and then fixes the terminal at either high level or low level; a waveform shaping circuit that shapes the waveform of the input signal of the terminal; and an output of the waveform shaping circuit. and an exclusive logic 40 circuit that takes the exclusive OR of the output of this delay circuit and the output of the waveform shaping circuit, and sets the output of the waveform shaping circuit to a fixed level output of the terminal, and The output of the logical OR circuit is a power-on reset signal.
Immediately after the power is turned on, a pulse signal is input to the terminal and a reset pulse for initial settings is generated, so it is possible to significantly shorten the non-initialization time, and since the configuration is configured to reset multiple times, the initial settings can be can be done with certainty. Of course, since the initial settings of the integrated circuit can be realized without using dedicated terminals, the number of terminals can be reduced and the terminals can be used efficiently.

[Brief explanation of the drawing]

Figures 1 and 2 are explanatory diagrams of conventional initial setting circuits;
The figure is an explanatory diagram of the configuration of an initial setting circuit according to an earlier invention of the present inventor, FIGS. 4, 6, and 8 are circuit diagrams representing different embodiments of the present invention, and FIG. 5 is an illustration of the fourth embodiment. FIG. 7 is an explanatory diagram of the operation of the circuit shown in FIG. 6. 10 is IC140 is a mode setting module, 41 is an oscillation circuit, 42 c) Rice cheat rough 7 circuit, 43ij:
The time constant circuit 44 is a pull-up resistor. Patent applicant Fujitsu Ten Ltd.

Claims (1)

[Claims] In an initial setting circuit for an integrated circuit having a terminal used with an input signal level fixed at either a high level or a low level, the initial setting circuit includes an oscillation circuit and an output of the oscillation circuit for a predetermined period of time from when the integrated circuit is powered on. a time/level setting circuit that applies an voltage to a terminal and then fixes the terminal at either a high level or a low level; a waveform shaping circuit that shapes the waveform of an input signal to the terminal; and a delay that delays the output of the waveform shaping circuit. circuit, and an exclusive OR circuit that takes an exclusive OR of the output of the delay circuit and the output of the waveform shaping circuit, the output of the waveform shade circuit is set as a fixed level output of the terminal, and the exclusive logic An initial setting circuit characterized in that the output of the sum circuit is used as a reset pulse for initial setting.