JPS5946017U - Push-pull amplifier bias circuit - Google Patents
Push-pull amplifier bias circuitInfo
- Publication number
- JPS5946017U JPS5946017U JP14138282U JP14138282U JPS5946017U JP S5946017 U JPS5946017 U JP S5946017U JP 14138282 U JP14138282 U JP 14138282U JP 14138282 U JP14138282 U JP 14138282U JP S5946017 U JPS5946017 U JP S5946017U
- Authority
- JP
- Japan
- Prior art keywords
- push
- bias circuit
- bias
- pull amplifier
- amplifier bias
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来例、第２図は本考案の一実施例を示す回路
図である。
図中、６及び８はシリコンダイオード、７及び９はゲル
マニウムダイオード、１２． １３． １４及び１５は
トランジスタである。FIG. 1 is a circuit diagram showing a conventional example, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. In the figure, 6 and 8 are silicon diodes, 7 and 9 are germanium diodes, 12. 13. 14 and 15 are transistors.
Claims (1)
互いに導電型の異なる第１及び第２のトランジスタと、
該トランジスタの各ベースにそれぞれ抵抗器を介してＢ
級又はＡＢ級のバイアス電圧を印加する第１のバイアス
回路と、上記各ベースに上記各抵抗器を介して印加され
る入力信号と、上記各トランジスタのベースにそのトラ
ンジスタを導通状態にする入力信号の期間カットオフと
なる方向の第１及び第２のシリコンダイオードを介して
バイアス電流を供給する第２のバイアス電源とを有する
プッシュプル電力増幅器において、上記第１及び第２の
シリコンダイオードにそれぞれ導通方向を合わせてゲル
マニウムダイオードを接続したことを特徴とするプッシ
ュプル増幅器のバイアス回路。first and second transistors having different conductivity types each supplying power to a load via an emitter resistor;
B is connected to each base of the transistor through a resistor.
a first bias circuit that applies a class or AB class bias voltage; an input signal that is applied to each of the bases via the resistors; and an input signal that makes the transistor conductive to the base of each of the transistors. a push-pull power amplifier having a second bias power supply that supplies a bias current through the first and second silicon diodes in a direction that is cut off for a period of . A push-pull amplifier bias circuit characterized by connecting germanium diodes in the same direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14138282U JPS5946017U (en) | 1982-09-17 | 1982-09-17 | Push-pull amplifier bias circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14138282U JPS5946017U (en) | 1982-09-17 | 1982-09-17 | Push-pull amplifier bias circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5946017U true JPS5946017U (en) | 1984-03-27 |
Family
ID=30316227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14138282U Pending JPS5946017U (en) | 1982-09-17 | 1982-09-17 | Push-pull amplifier bias circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5946017U (en) |
-
1982
- 1982-09-17 JP JP14138282U patent/JPS5946017U/en active Pending
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