JPS5943765B2 - semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit equipped with an oscillation circuit, and particularly to an improvement aimed at reducing power consumption.

In integrated circuits such as one-chip microcomputers, the degree of integration has been dramatically increased, and various functions are being integrated on-chip.

Most one-chip microcomputers have a built-in oscillation circuit, and a basic clock signal can be obtained simply by externally connecting a crystal oscillator or passive elements such as resistors and capacitors to external terminals. On the other hand, in a complementary MOS type integrated circuit that can operate with low power consumption, internal operations are stopped in the hold mode to further reduce power consumption. FIG. 1 is a block diagram of a conventional integrated circuit that reduces power consumption by stopping internal operations in the holding mode, and shows an example of a one-chip microcomputer.

In the figure, 1 is an oscillation circuit. This oscillation circuit 1 is composed of an inverter 2 and a resistor 3 provided in an integrated circuit, and an oscillation feedback circuit U consisting of a resistor 6 externally connected to external terminals 4 and 5, a crystal resonator T, and capacitors 8 and 9. has been done. A clock pulse output from this oscillation circuit 1 is sent to a timing generator 11. The timing generator 11 is designed to sequentially output timing signals necessary for various controls based on the clock pulses. In such a configuration, now this 1
If the power supply voltage of the chip microcomputer is lower than the specified value and there is a risk of malfunction, a predetermined flag H of the status register (not shown) is set to ``1''.
signal.

After this, when this H flag signal is input to the timing generator 11, the timing generator 11 stops outputting the timing signal, so this microcomputer changes from the operating mode to the holding mode, enters the standby state, and enters the low power consumption state. It is set. However, when the holding mode is entered, the internal operations such as the arithmetic processing circuit stop, but the oscillation circuit 1 continues to oscillate as in the operating mode. Generally, the oscillation frequency in the oscillation circuit 1 is the same or faster than the internal operating frequency.

Therefore, depending on the oscillation conditions such as frequency, the power consumed by the oscillation circuit 1 may be greater than the power consumed by internal operation, and the internal operation may be put into hold mode and stopped. However, the power consumed for oscillation does not decrease even if the oscillation occurs, so the conventional method has the disadvantage that it cannot be expected to reduce power consumption much. This invention has been made in consideration of the above circumstances, and its purpose is to provide a semiconductor integrated circuit that reduces power consumption by stopping the oscillation operation of an oscillation circuit during a hold mode. Our goal is to provide the following.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram of one embodiment of the semiconductor integrated circuit according to the present invention, and shows an example of a one-chip microcomputer as in the prior art. Program counter (
PC) 21 is for addressing ROM 22, and its output is sent to ROM 22.

The ROM 22 stores a program in advance, reads program data stored in an address area corresponding to the output of the program counter 21, and stores the read program data in an instruction register (IR) 23. Sent.

The instruction register 23 temporarily stores the program data read from the ROM 22 and then outputs it.
This output is sent to an instruction decoder (ID) 24.

The instruction decoder 24 decodes the program data sent from the instruction register 23 and generates various signals.

The RAM 25 stores data sent from the bus line 26, and also reads out previously stored data and outputs it to the bus line 26, and its address is designated by a RAM address register (RR) 27. It is beginning to be practiced.

The accumulator (ACC) 28 temporarily stores the data sent from the bus line 26 and sends the stored data to the arithmetic and logic unit 29.

The status register (SR) 30 has several flags therein, including the H flag for determining the operating mode and holding mode of this microcomputer, and each flag is set according to the data sent from the bus line 26. The H flag is set to be lowered when a counter, which will be described later, counts a predetermined number of pulses and its output rises.

Data is also sent to the arithmetic and logic unit 29 from a bus line 26.
Arithmetic and logical operations are performed between the data from 6 and the data from the accumulator 28 or status register 30.

The result is then sent to bus line 26. The input/output port 31 transfers data on the bus line 26 to a plurality of external terminals 321-32.

These external terminals 321 to 32 output data from the outside to the outside via the external terminals 321-32. It is now possible to input it via . One external terminal 32 of this input/output port 31. is for detecting the power supply voltage supplied to this microcomputer, and this terminal 32n
A collector of an NPN transistor Q whose base input is the power supply voltage V is externally connected to the transistor Q. Further, since the terminal voltage of a sufficiently large capacitor charged by the voltage v is supplied to the collector of the transistor Q, if the power supply voltage is sufficiently high, the transistor Q is turned on and the external terminal 32n is turned on. The level becomes a low level, and when the power supply voltage FEV decreases, the transistor Q is turned off and the level of the external terminal 32n becomes a high level. The H flag in the status register 30 is set to the external terminal 32.
. It is set (set to a high level) by program processing when the level is at the Kawawa level. The oscillation circuit (0SC) 33 generates clock pulses that control the operation of this microcomputer, and is connected to the external terminal 32.

The oscillation operation is controlled by the level of TG and the oscillation stop signal sent from the timing generator (TG) 34. The clock pulses generated here are sent to a timing generator (TG) 34 and a counter (COUNT) 35. The timing generator 34 outputs H in the status register 30.
The timing signal is generated based on the clock pulse only when the flag is not set, and when the H flag is set, the generation of the timing signal is stopped after a predetermined period and the above oscillation is stopped. An oscillation stop signal is output to circuit J3.

The counter 35 counts the clock pulses output from the oscillation circuit J3, and when the count reaches a predetermined number, its output rises. Figure 3 shows the above oscillation circuit J
3 is specifically shown. This oscillation circuit J3 is provided within the integrated circuit as shown in the figure, and is provided at the input/output port 31.
N which inputs the signal of one external terminal 32n and the oscillation stop signal from the timing generator 34, respectively.
An AND gate circuit 41 is provided within the integrated circuit and this NA
Another NAND gate circuit 42 whose one input is the output of the ND gate circuit 41, a resistor 43, and an external terminal 44.
, 45, an oscillation feedback circuit 1 consisting of an external resistor 46, a crystal oscillator 47, and capacitors 48, 49. Next, the operation of the circuit configured as described above will be explained.

First, if the power supply voltage V supplied to this microcomputer is high enough, the external terminal 3 of the input/output port 31
2. will be at a low level. At this time, the output of the oscillation circuit 10) NAND gate circuit 41 shown in FIG. 3 is at a high level, so the oscillation circuit {3} operates in oscillation and outputs a clock pulse. On the other hand, the external terminal 32. If the level is low, the H flag in the status register 30 will not be set, so the microcomputer will be in the operating mode. In addition, the timing generator 34
generates a timing signal based on the clock pulse output from oscillation circuit J3.

At this time, the oscillation stop signal is at a low level. Therefore, at this time, the microcomputer uses the instruction decoder 24.
It will operate based on the control signal output from. Next, when the power supply voltage decreases below the specified value and there is a risk of malfunction, the transistor Q is turned off and the signal output level of the external terminal 32n of the input/output port 31 is inverted to the normal level. Note that at this time, the oscillation stop signal output from the timing generator 34 is still at a low level. Therefore, even if the level of the external terminal 32n is inverted to a high level, the output of the NAND gate circuit 41 in the oscillation circuit J3 becomes a high level, and the oscillation circuit 1 continues its oscillation operation. Furthermore, when the level of the external terminal 32n becomes high level,
After that, the external terminal 32 is connected at the timing shown in FIG.
After that, the H flag of the status register 30 is set and the holding mode is entered. When the H flag is set, the timing generator 34 stops generating timing signals after inputting clock pulses until the end of one instruction cycle, and outputs a high-level oscillation stop signal. When the generation of the timing signal stops, the inside of this microcomputer except for the oscillation circuit J3 enters a standby state and is set to a low power consumption state. Furthermore, when the high-level oscillation stop signal output from the timing generator 34 is input to the NAND gate circuit 41 of the oscillation circuit J3, the level of the external terminal 32n is already at a high level, so the NAND gate circuit 41 is The output becomes low level and the NAND gate circuit 42 becomes disabled. That is, the oscillation operation of the oscillation circuit J3 is also stopped. Since the oscillation operation of the oscillation circuit J3 is thus stopped in the holding mode, the power consumption is extremely low in the holding mode, and low power consumption can be realized. In addition, in the hold mode, the oscillation circuit J3 stops the oscillation operation after waiting for the timing generator 34 to finish generating the timing signal for one instruction cycle, so that the internal operation is performed in the middle of one instruction cycle. It never stops. Next, when the power supply voltage V recovers to the specified level again, the transistor Q is turned on again and the signal at the external terminal 32n of the input/output port 31 is inverted to a low level.

When the signal at the external terminal -32n is inverted and becomes a low level, the output of the NAND gate circuit 41 of the oscillation circuit J3 becomes a high level, and the oscillation circuit J3 starts its oscillation operation again and outputs a tick pulse. However, at this time,
Since the H flag in status register 30 has not been lowered, timing generator 34 does not generate a timing signal. Therefore, at this time, the inside of the microcomputer is still in a standby state. on the other hand,
The counter 35 counts clock pulses immediately after the oscillation circuit J3 starts its oscillation operation, and when the count reaches a predetermined number, its output rises. When the output of the counter 35 rises, the H flag of the status register 30, which has been set until now, is lowered, the previous holding mode is canceled, and the operating mode is entered again. Therefore, after this, the timing generator 34 generates a timing signal based on the clock pulse outputted from the oscillation circuit J3, and at this time, the microcomputer operates based on the control signal outputted from the instruction decoder 24. Become. However, immediately after the oscillation circuit J3 starts its oscillation operation, the oscillation level is not sufficiently large, and the oscillation frequency is also unstable.

However, the timing generator 34 does not generate a timing signal until the oscillation is stabilized, and the counter 35 counts a predetermined number of clock pulses during the period from the start of oscillation until the oscillation becomes sufficiently stable. Since the holding mode is canceled and the operating mode is set after this period has elapsed, the timing generator 34 will not malfunction due to unstable lock pulses. Therefore, after the holding mode is released, processing can be easily restarted from the state before the holding mode.
Note that the present invention is not limited to the above-mentioned embodiment. For example, the above embodiment describes the case where the present invention is implemented in a one-chip microcomputer, but this invention is not limited to microcomputers, and can be applied to any device equipped with an oscillation circuit. Needless to say, the present invention can be applied to any semiconductor integrated circuit.

Further, in the above embodiment, the case where the holding mode is entered by program processing has been described, but this can also be applied to the case where the holding mode is entered by hardware. Furthermore, in the above embodiment, the oscillation circuit J3 includes two NAND gate circuits 41.
, 42 has been described, but as for one of the NAND gate circuits 42, any inverting type gate circuit having an inverting function may be used, and a NOR gate circuit can also be used. As described above, according to the present invention, since the oscillation operation of the oscillation circuit is stopped during the holding mode, it is possible to provide a semiconductor integrated circuit that can reduce power consumption.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional integrated circuit, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a concrete diagram of a part thereof, and Fig. 4 explains the operation of the above embodiment. This is a timing chart for. 21...Program counter, 22...
・ROM, 23...Instruction register, 24...
...Instruction decoder, 25...RAM, 26.
...Bus line, 27...RAM address register, 28...Accumulator, 29.
... Arithmetic logic unit, 30 ... Status register, 31 ... Input/output port, 321 ~
32.

Claims (1)

[Claims] 1. An oscillation circuit, a timing generator that generates various timing signals based on the output pulses of this oscillation circuit in the operation mode, a counter that counts the output pulses of the oscillation circuit, and a counter that stops the oscillation operation of the oscillation circuit in the hold mode. means for restarting the oscillation operation of the oscillation circuit after the oscillation operation of the oscillation circuit is stopped by this means; 1. A semiconductor integrated circuit comprising means for canceling the holding mode and setting an operating mode when a number of pulses corresponding to a period of time until the holding mode is counted.