JPS5927928B2 - sequence controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sequence controller used for controlling machine tools, etc., and more specifically, a sequence controller that is used to control machine tools, etc. Control the controlled object by selecting input elements such as switches and limit switches and output elements such as relays and solenoids, testing the on/off of the selected input/output elements, and energizing and deenergizing the output elements based on the test results. The present invention relates to a sequence controller.

Conventionally, in order to create a sequence program for such a sequence controller, first a cycle diagram is created based on the operation of the controlled object, a relay matrix is designed based on the cycle diagram, and then this relay matrix is designed based on the cycle diagram. The method used was to program the matrix into a sequence program.

For example, when creating a sequence program for performing the f5I leg in which the drill unit moves forward to process a workpiece in a machine such as the one shown in Figure 1, and the drill unit retreats after finishing machining, first, Create a cycle diagram as shown.

In this cycle diagram, the conditions for transitioning a step are written above the cycle diagram.The output elements that are energized or deenergized to transition a step are written on the top of the cycle diagram.
A relay matrix designed based on this cycle diagram is shown in FIG. 3, and a sequence program is created based on this relay matrix. However, the command words used in the program have meanings as shown in Table 1. Also, in the program, the input/output address to which the input/output element or dummy is connected, or the address of the memory that will be replaced by the dummy, is written, but for simplicity, the name of the input/output element, dummy, etc. is written and the input/output address or memory address is written. This is the address. This also applies to subsequent explanations. It is relatively easy to create a sequence program from a relay matrix in the program creation process described above, but in order to design a relay matrix from a cycle diagram, it is necessary to consider the interlocks of each operation problem. Furthermore, when controlling a machine like the one shown in Figure 1, the advance conditions and stop conditions are exactly the same, as is clear from the cycle diagram, so a circuit is required to remember when the unit has moved forward. It cannot be easily designed from a cycle diagram.

Therefore, creating a sequence program from a cycle diagram requires a great deal of effort. Furthermore, even if the operation of the controlled object changes, the sequence program must be rewritten after changing the design of the relay matrix, and if the controlled object is modified, there are drawbacks that cannot be easily addressed. had. In addition, in general sequence controllers, all programmed sequence programs are read and executed, so
When the number of steps increases and control becomes complicated, or when the number of programs increases significantly, such as when controlling multiple machines at the same time with one sequence controller, the scan time to execute all programs once becomes longer. , had drawbacks that affected control.

The present invention has been made in order to eliminate the above-mentioned drawbacks, and as shown in FIG. Then, by using a sequence program programmed with an input condition for transitioning the step, an output command that is activated when the input condition is satisfied, and an output command for transitioning the step and the step number to be performed next,
A simple sequence program that can be programmed directly from the cycle diagram by storing the step number read from this sequence program as the step operation currently being performed and executing only the sequence program related to this stored step operation. Furthermore, the scan time will not increase at all even if the amount of sequence programs increases, such as when the number of steps in sequence operation increases or when multiple machines are controlled by one sequence controller. It provides a sequence controller. Embodiments of the present invention will be described below based on the drawings.

FIG. 7 shows a first embodiment of the present invention, and is a block diagram showing a configuration when sequence control is performed by a computer such as a minicomputer. The input circuit 10 converts detection signals provided from input elements such as limit switches and pushbutton switches that detect the operating state of the controlled machine into C-level signals, and also connects the interface 1
With the input/output address data given from 1, one of the on/off states of the input element whose signal has been converted is selected and output. The output circuit 12 selects one of output elements such as a relay or a solenoid using input/output address data, and energizes or deenergizes the selected output element according to an output command given from the interface 11. It also outputs the on/off state of the output element selected by the input/output address data. The computer 13 is adapted to execute a sequence program based on an execution program programmed in advance, and if the read sequence program is a test instruction, the computer 13 is configured to execute a sequence program based on an execution program programmed in advance. Give an input/output address zeta to the input/output element, select one of the input/output elements, and read its on/off state. Further, if the sequence program is an output command, input/output address data is given to the output circuit 12 to energize and de-energize selected output elements to perform a series of sequence control. Such a series of processing is performed based on an execution program of the computer 12, and its operation will be explained in detail by taking as an example the case where two machines 20 and 30 as shown in FIG. 8 are controlled.

These two units are exactly the same, and each starts automatic operation when a start button is pressed.
When automatic operation starts, the unit moves forward and the spindle drive motor rotates to process the workpiece. When the unit reaches the forward end, it performs doweling. After the doweling is completed, the unit retreats and returns to its original position, and automatic operation begins. Finish and stop. Furthermore, when the emergency stop switch is pressed while the machine is in operation, the hydraulic circuit is blocked to stop the machine and cancel automatic operation. The above operation can be expressed in a cycle diagram as shown in FIG. 9.

In FIG. 9, the input conditions for moving each step are written on the bottom side, and the execution command for moving the step and the number of the next step are written on the bottom side for each operation step. If there are a plurality of sequence controls that are executed in parallel at the same time, a different step number is assigned to each step of each sequence control. In addition, interlock conditions with external machines or stop conditions such as emergency stop signals during each step operation are written between the step nodes. The instructions are written. A sequence program is created based on this cycle diagram, part of which is shown in Table 2. Further, the instruction words used in the sequence program are composed of five types of test instructions, three types of output instructions, and a NOP instruction, as shown in Table 3. The sequence program programmed in this way is written into the storage device of the computer 13 in the format shown in FIG. 10 by a program writing device (not shown).

In FIG. 10, the sequence table is a part that stores the step number currently being executed. A step number is stored for each sequence operation consisting of a plurality of steps. For example, the first two digits of the step number are It represents which sequence operation is being performed among a plurality of sequence operations that are being performed in parallel, and the last two digits represent the step that is currently being performed in each sequence operation. Further, the sequence pointer SP specifies one of a plurality of sequence operations, and only the sequence program corresponding to the currently executed step of the specified sequence operation is executed. Note that this sequence pointer SP is switched each time a one-step sequence program is executed, and sequentially specifies other sequence operations. The index table stores where in the storage device the sequence program corresponding to each operation step is written.The index table stores the start address and end address, which are the beginning and end memory addresses of the sequence program. is stored as index data. If the step number of the index data specified by the index pointer IP in this index table is the same as the step number specified by the sequence pointer SP, the step number specified by the read program data is specified. The sequence program is executed, and if different, the index pointer P
specifies another program and searches for the same index data as the step number specified by the sequence pointer SP. The sequence program table stores the program touch sequence program for each operation step, and the sequence program for each step includes a test of input conditions for transitioning the step and a test for the next step when the test conditions are satisfied. The number of steps to be performed and the output instructions to energize or de-energize the output elements to transition the steps are programmed. Of this sequence program table, only the sequence program corresponding to the step number specified by the sequence pointer SP is read and executed, but the setting of the sequence pointer SP and the synchronization from the index table are - An execution program that performs a series of operations of searching for a program with a step number and executing a sequence program specified by the step number will be explained with reference to the flowchart of FIG.

This execution program includes a sequence pointer SP that specifies one of a plurality of sequence operations, an index pointer IP that searches the index table for a program with the same step number as the step number,
The program includes a program counter PC that specifies the memory address where the sequence program is stored, an AND flag ANDFLG that stores whether the test instruction is an AND instruction or an OR instruction, and a test flag TESTFLG that stores the test result. Ru. When the execution program is started, the sequence pointer SP is reset in stage (2), and the content of the sequence pointer SP becomes O. (3) Stage is a routine that reads the step number specified by the sequence pointer from the sequence table.In the first read, the sequence pointer SP is 0, so the step number stored at the beginning of the sequence table is read. The number is read out. At the (4) stage, it is determined whether the read step number is a number representing the end of the sequence table. Although it is not the sequence table end in the first read, if it is determined that it is the sequence table end, (2) return to the front of the stage and reset the sequence pointer SP again. When the reading of the step number is completed, the data is updated to the index table at stage (5), and the first data of the index table is read out in units of 3 words. In the (6) stage, it is determined based on the read data whether the index table is at the end or not. Although it is not the end in the first data read, if the read data represents the end, the process moves to stage (6-1). (
6-1) At the stage, add 1 to the sequence pointer and (
3) Return to the front of the stage and read the step number of the next sequence number. At the (7) stage, the step number written in the read data is compared with the step number read at the (3) stage. If they match, the process advances to the next stage, but if they do not match, the index pointer IP is incremented by 1 at stage (7-1) and the next data is read. In the (8) stage, the test flag TESTFLG is reset before the next sequence program is executed. (9) In the stage, the start address of the data read out in the stage (7) is preset in the program counter PC, and in the AI stage, the value of the program counter PC and (7) are preset in the program counter PC.
) is compared with the end address read in the stage 2, and it is determined that the program end is reached by detecting that all the designated sequence programs have been executed and the value of the program PC becomes equal to the end address. and,
When it is determined that the program is at the end (7-1)
The index pointer is incremented by 1 at the stage and a search is made to see if there is another program with the same step number. If it is not the program end, the sequence program designated by the program counter PC is read out at stage 01). In the (self) stage, it is determined whether the read sequence program is an instruction for testing input conditions. If the read sequence program is a test instruction, the process moves to stage (16). (16)
At the stage, it is determined whether the test instruction is executed using AND instruction or OR logic. If the test instruction is executed using AND logic, the AND flag is set at stage (17-1), and when it is executed using OR logic, the AND flag is set. 17-2) Reset the AND flag on the stage. At the (18) stage, the on/off state of the input/output element specified by the input/output address data of the sequence program is checked, and whether the specified step number is currently being executed is checked, and at the (19) stage, the test conditions are checked. It is determined whether the conditions are satisfied. Then, if the test conditions are satisfied, the test flag TESTFLG is set in the (18-1) stage, the program counter PC is incremented by 1 in the (9-1) stage, and then the process returns to the front of the (sub)stage. , reads the next sequence program. If the test conditions are not satisfied, the process moves to stage (20). At the (20) stage, it is determined whether the AND flag ANDFLG is set, that is, whether the test instruction is executed using AND logic. In the case of an unyori method, there is no need to execute any subsequent programs unless the test conditions are satisfied, so the execution of the specified sequence program ends at this point, and (7-1) After moving to the stage, search to see if there is another sequence program with the same step number for the same stock as at the end of the program. However, in the case of OR logic, it is necessary to test all input conditions, so the program counter is incremented by 1 at stage (9-1) and the next program is read. When the input conditions are sequentially tested in this way and the output instruction program is subsequently read out, it is determined in the (sub) stage that the input conditions are not the input conditions, and the process moves to the (self) stage.

It is determined whether the instruction read at this (self) stage is an output instruction. If the read instruction is not an output instruction, that is, neither an input condition nor an output instruction (
(NOP instruction), the program counter is incremented by 1 at stage (9-1) and the next program is read. If the read instruction is an output instruction, the process moves to the (self) stage and it is determined whether the test flag TESTFLG is set. Regardless of whether the test instruction is executed using AND logic or OR logic, if the condition is satisfied, the test flag TESTF is set at stage (18-1).
LG is set, and in this case, at stage (15), the output element specified by the input/output address is activated or deactivated. Further, when the output instruction is a step number, that step number is written to the location specified by the sequence pointer SP in the sequence table. When the output command is thus executed at stage (15), the program counter is incremented by 1 at stage (9-1) and the next sequence program is read. Note that if it is determined in the A4) stage that the test flag is not set, there is no need to program the subsequent output commands, so the program moves to the (7-1) stage and searches for the next sequence program. do. Next, the processing steps of the execution program and the sequence program will be explained by taking as an example the case where two machines as shown in FIG. 8 are controlled simultaneously.

Now, as shown in Fig. 8, the units of the two machines 20 and 30 are both located at their home positions, and the sequence control operation is started with their home position confirmation limit switches LSLO and LS2O being pressed. shall be When sequence control is started, the sequence pointer SP is reset in stage (2) of FIG. 11, and the step number 0000 stored at the beginning of the sequence table shown in FIG. 10 is designated. On the other hand, since the unit of the machine 20 is located at the original position, the step number is 0, so the operation step number of the machine and the step number inside the controller match. In reality, the machine is returned to the origin and the step number is set to O by pressing a pushbutton switch for returning to the origin (not shown) prior to the start of sequence control. and,
(3) Step number 0000 is read at the stage.
When this step number is read out, it is determined in stage (4) whether or not it is the end of the sequence table, but since step number 0000 is not the end of the sequence table, the process moves to the next stage. (5) At the stage, the index table is jumped and the index pointer P is reset, so that the data stored in the first memory addresses 2000 to 2003 of the index table is specified. This designated data is read at stage (5-1), and it is determined at stage (6) whether it is the end of the index table. Since this data is not the sequence table end, the process moves to the next stage (7). In the (7) stage, the step number 0000 of the read data is compared with the step number 0000 of the index data specified by the sequence pointer. In this case, since both step numbers match, the process moves to the next stage and starts executing the sequence program specified by the step number. After resetting the test flag in the (8) stage, the start address 4000 of the data that could not be read to the program counter PC is preset in the (9) stage. This specifies the sequence program at memory address 4000. Subsequently, in the (self) stage, the value 4000 of the program counter and the end address 4006 of the read data are compared, but since they do not match, the operation of the next stage is performed. a1) Sequence program STO stored at memory address 4000 specified by program counter PC at stage
is read out. This read sequence program is judged at the (self) stage as to whether it meets the input condition or not.
Since this is an instruction to test whether or not , using AND logic, and is a manual condition, the process moves to the operation of stage (16). At the (16) stage, it is determined that the test instruction is executed using AND logic, and at the (17-1) stage, the AND flag is set. Then (18) it is checked whether the step number currently being performed in the stage is O, but since the step number currently being performed is O,
(19) It is determined that the condition is satisfied at the stage, (18-1)
Set the test flag TESTFLG on the stage. If the step numbers are different, it is determined at stage (20) that the AND flag ANDFLG is set, so this sequence program ends and the process moves to the operation at stage (7-1). When SPIO is tested in this way, (9-1
) stage, increments the program counter by 1 and specifies the sequence program at memory address 4001. Then, the YOFSO stored at memory address 4001
The instruction of LIO is read, but since this instruction is an output instruction that disables the solenoid SOLIO if the test result is satisfied, it is determined at the (self) stage that it is an output instruction. When it is determined that it is an output command, it is determined in stage A4 whether or not the test flag TESTFLG is set. In this case, the test result is satisfied and the test flag TESTFLG is set.
is set, the process moves to the next stage (15), the output command is executed, and the solenoid SOLIO is deenergized. When the YOFSOLIO instruction is executed in this way, the PC is increased by 1 and the next instruction is read out and executed, as in the previous case. And YONSOLll, YOFTR
The instructions 1, YOFM1, and YOFRUN1 are executed one after another every time the program counter PC is incremented by 1.

As a result, the solenoid SOLll is energized, the dwell timer TRl is deenergized, and the spindle drive motor M1 is energized.
When the automatic operation flag RUNl is set, the unit is held in its original position and the motor M1 is stopped, thereby enabling automatic operation. Then, when the execution of YOFRUNl, which is the last instruction of the sequence program specified by the index data, is completed and the program counter PC increases by 1 and reaches 4006, the program counter PC is started at the 0D stage because it matches the end address read from the index table. It is determined that it is the end. As a result, the process moves to stage (7-1), the index pointer IP is incremented by 1, and the index data stored in memory addresses 2003 to 2004 of the index table is specified. Since the zeta of the index table is read out three words at a time as described above, each time the index pointer IP is increased by 1, the next three words are read out.
word is specified. The specified data is read out at stage (5-1), and step number 0 specified by the sequence pointer is compared with the step number of the read data at stage (7). In this case, the read step number is O and they match, so the process moves to the next stage operation and the sequence program stored in memory addresses 4007 to 4009 is executed in the same way as in the previous case. . This sequence program uses AND logic to test whether the automatic operation flag RUN1 is set and also sets the start switch STA.
Test whether RTl is pressed with AND logic,
If these conditions are satisfied, the automatic operation flag RUNI is set and the step number is set to 1. When the execution of this sequence program is completed, the index pointer is increased by 1 again at the (7-1) stage, and the next index data stored in memory addresses 2006 to 2008 is read out. Then, in stage (7), the step numbers are compared, and as a result of executing the sequence program, the input conditions for moving the step are satisfied, and the output command to rewrite the step number to 1 is executed. In this case, the step number specified by the sequence pointer and the step number of the read index data are both 1, so they match, and memory addresses 4010 to 40
The sequence program stored in 16 can be executed. However, as a result of executing the sequence program, if the input conditions are not satisfied and the step number is not rewritten, the step number specified by the sequence pointer SP and the read step number do not match. Then, the index pointer is incremented by 1 again and compared with the step number of the next index data.

In this way, the index data is read out sequentially, and a search is made for index data having the same step number. When the data at the index table end is read, it is determined that the data is at the index table end at stage (6), and the sequence pointer SP is incremented by 1 at stage (6-1). Thereby, the sequence pointer SP specifies the second stored step number in the sequence table. Therefore, control of sequence number 1 is started from this point. When the step number of sequence number 1 is specified by the sequence pointer SP, the step number 0100 is read from the sequence table in the (3) stage, and the memory specified by the step number 0100 is read out in the same way as in the previous case. The sequence programs stored at addresses 5000 to 5009 are read and executed.

Now, assuming that neither start switch STARTl nor START2 is pressed, after executing the sequence program specified in step 100, by incrementing the index pointer by +1 in stage (7-1),
Since the step number specified by the sequence pointer SP does not match the step number of the read index program, the index pointer IP searches the remaining index tables, and the index pointer P searches the index table. When the end is specified, it is determined in stage (6) that it is an index table end, and the process moves to stage (6-1). At the (6-1) stage, the sequence pointer SP is increased by 1 again to designate the step number of the next memory address in the sequence table. If there are sequence operations running in parallel other than sequence numbers 0 and 1, specify one of the sequence operations, but in this example, two sequence operations are running in parallel. Therefore, 7J Camo V, which represents the sequence table end, is stored in the next memory address. For this reason(
3) 7J Camo V is read out as the step number on the stage. As a result, it is determined in stage (4) that the sequence table is at the end, and the process returns to the front of stage (2). In this way, one sequence program corresponding to steps O and 100 is executed, but as the sequence pointer SP is reset, step number 0 is designated again, and the sequence program corresponding to step number 0 is executed. After the execution of this sequence program, the sequence program corresponding to step number 100 is executed and the sequence pointer SP is reset again. Thereafter, this operation is repeated cyclically, and the sequence programs corresponding to step numbers 0 and 100 are executed alternately. Then, when the start switch STARTl is pressed, the output command is executed in order to satisfy the input condition for moving the step. As a result, the step number of sequence number 0 is rewritten to 1, and the operation shifts to step number 1. Thereafter, scanning of the sequence program corresponding to step number 1 and the sequence program having step number 100 stored in memory addresses 4010 to 4015 is repeated. Furthermore, start switch STAR
When T2 is also pressed, the step number of sequence number 1 also becomes 101, and the sequence programs of step numbers 1 and 101 are executed alternately. Thereafter, in the same manner, the sequence programs designated by the step numbers 0 and 1 are alternately and repeatedly executed, and the sequence protrusion is performed by independently transitioning the step operations. When the series of operations of advancing the unit, machining the workpiece, and retracting the unit is completed and the unit returns to its original position, the STOO and STOlOO commands are executed, respectively, and the step number is rewritten to the initial value to complete automatic operation. . In addition, in this embodiment, the case where two machines that move completely differently are used as an example to explain the case, but by programming the input conditions or sequence numbers of the reference sequence operation as the input conditions, it is possible to It is also possible to easily synchronize the timing of multiple sequence operations that are being performed in parallel.

When performing sequence control with a computer such as a minicomputer, as described above, the sequence pointer SP
l Index pointer IP l Program counter PC
etc. were formed using an executable program and provided with a sequence function using software, but these functions can of course also be realized using a hardware circuit. This embodiment will be explained below with reference to FIG. In FIG. 12, sequence memory 100, index memory 101, and program memory 102 correspond to a sequence table, an index table, and a sequence program table, respectively. The sequence memory 100 is designed to store step numbers of sequence operations performed in parallel, one of which is sequentially designated by a program counter PCl corresponding to a sequence pointer, and the designated step number is Read out. Also,
The specified step number can be rewritten with a new step number. The index memory 101 stores the start address and end address of the sequence program corresponding to each step number, but in this case there is no equivalent to the index pointer 1P, and the step number read from the sequence memory There is a one-to-one correspondence between index data in the index memory, and when a step number is specified by the program counter PCl, the index data corresponding to this step number is read out. ing. Therefore, there will never be two or more pieces of index data with the same step number, and as shown in Figure 13, sequence programs with the same step number are grouped together in one place, and each sequence program with the same step is specified by index data. . Among the read index data, the start address is preset in the program counter PC2, and the end address is given to the comparator 103. This program counter PC2 specifies one of the sequence programs stored in the program memory by the given start address. Then, each time a designated sequence program is executed, it increments by 1, and the sequence programs are designated one after another. The count value of the program counter PC2 is constantly compared by the comparator 103, and when the count value of the program counter PC2 matches the end address, it is determined that the sequence program of the step number read from the sequence memory 100 has ended. , comparator 100 provides an addition pulse to the program counter. As a result, the program counter PC2 specifies the step number of the next sequence number. The sequence programs sequentially designated by the program counter PC2 are executed by a sequence program execution circuit composed of an address register 104, an instruction register 105, a decoder 106, and a test flag 107. address register 104
temporarily stores the input/output address data of the sequence program and selects one of the input/output elements. The instruction register 105 temporarily stores the instruction part of the sequence program, and the stored instruction data is decoded by the decoder 106. Based on the instruction decoded by the decoder 106, the test flag 107 tests the on/off state of the input/output element specified by the input/output address data if the instruction is a test instruction, and if the instruction is an output instruction, the specified Outputs a signal that energizes or deenergizes the output element. Further, the test flag 107 determines that the instruction decoded by the decoder 106 is an instruction to rewrite the step number and that the input conditions for moving the step are satisfied, and a signal FT indicating that the conditions are satisfied is output. When this occurs, the game gate 10 is opened by opening the AND gate 111, and the data of the step number to be performed next in the sequence program is written into the sequence memo I river 00. Furthermore, test flag 1
As a result of the test conducted in step 07, if there is any input condition that is unsatisfactory, the execution of the sequence program of the step number specified at that point is terminated, and a signal indicating that the conditions are unsatisfied is sent.
is output, causing the program counter PC2 to count up. As a result, the sequence program corresponding to the step number of the next sequence operation is executed. The control clock generation circuit 113 outputs a series of control clocks to determine the timing of the operation of the sequence controller. The sequence program execution operation of the sequence controller configured as above will be described below.

Now, assuming that the sequence controller starts operating with the program counter PC1 reset, the content of the program counter PC2 is O, so the step number stored at address O in the sequence memory is 0000. is read out. As a result, the start address 1000 and the end address 1010 are read from the index memory, so that the program counter PC2 is preset to 1000. Then,
TNASPO, which is a test of the input conditions stored at address 1000 in the program memory, is executed. This instruction is different from the case where sequence control is performed by software, and is an instruction to test whether step O is on or not using AND logic. Therefore, in the sequence controller of this embodiment, by setting an external dummy or a dummy in the program memory corresponding to the step number currently being executed, and testing this dummy,
It is designed to test using the step number as an input condition. When the execution of this program is completed, the program counter PC2 is incremented by 1 and the next program is executed. In this way, when the program is executed sequentially and the input condition for moving the step is satisfied, the number of the next step to be performed is written to the address of the sequence memory via the gate 110. And program counter PC2
When the count value becomes 1010, step number 0 is determined by the comparator.
When it is determined that the execution of the sequence program has ended, the program counter PC2 is incremented and step number 0100 stored at address 1 of the sequence memory is designated. Furthermore, even if the input conditions are unsatisfactory and the signal FT is output from the test flag 107, step number 0100 is designated by incrementing the program counter PC2 by 1. As a result, the index data stored at address 0100 of index memory 101 is read out, and the sequence program corresponding to step number 0100 is executed in the same way as in the previous case. When the execution of this sequence program is finished, the program counter PCl is incremented by 1 again, but this program counter PCl needs to be able to count the number of sequence operations that are performed in parallel, and in this case it is a binary counter. Therefore, step number 0000 stored in sequence memory address 0 is returned.
is specified. In this way, step 0000 (5
Only the sequence program 0100 is repeatedly executed alternately. When the step transition condition is satisfied, each step number is rewritten, only the sequence program corresponding to that step is executed, and the steps progress. In this way, a plurality of sequence operations performed in parallel can be controlled by one sequence controller. Furthermore, in this case as well, it is possible to synchronize the timing of the operations of a plurality of sequence controllers that are performed in parallel, as in the case where sequence control is performed using software. As described above, the sequence controller according to the present invention includes means for storing the operation step currently being performed, means for sequentially specifying the operation step, and means for specifying a sequence program corresponding to the specified operation step. By providing means for writing the next operation step to be performed in the storage means when the conditions for transitioning the step are satisfied, it is possible to use a simple sequence program that can be programmed directly from the cycle diagram. Furthermore, since only the sequence program that corresponds to the currently executed operation step is executed, scanning time will not increase even with complex sequence control, and even large-volume sequence control programs will not affect the sequence control at all. This has the advantage that the program can be executed without giving any

Furthermore, in the sequence controller according to the present invention, program blocks formed corresponding to each of a plurality of steps are selected for each block, and the sequence program to be repeatedly executed is sequentially changed. In addition to reliably detecting that all of the multiple input/output elements that serve as advance conditions satisfy the advance conditions, it is also possible to test whether or not the emergency stop button has been pressed in each program block to prevent movement of the movable object. It is also possible to write an interlock program to stop the system, which has the advantage of achieving highly safe sequence control.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the configuration of the machine subject to sequence control, Figure 2 is a cycle diagram showing the operation of the machine shown in Figure 1, and Figure 3 is created based on the cycle diagram in Figure 2. 4 is a diagram showing a conventional example of a sequence program programmed based on the relay matrix diagram of FIG. 3, and FIG. 5 is a cycle diagram that is the basis for creating a sequence program for the sequence controller of the present invention. , FIG. 6 is a sequence program programmed based on the cycle diagram shown in FIG. 5, FIG. 7 is a block diagram showing the first embodiment of the sequence controller according to the present invention, and FIG. 8 is the operation of the sequence controller according to the present invention. 9 is a cycle diagram showing the operation of the machine shown in FIG. 8. FIG. 10 is a diagram showing a sequence program stored in a storage device. 11
12 is a flowchart showing the execution program of the computer in FIG. 7, FIG. 12 is a block diagram showing a second embodiment of the sequence controller according to the present invention, and FIG.
This figure shows the data storage state of the sequence memory and index memory I8 program memory in FIG. 12. 10,108...Input circuit, 11...
Interface, 12, 109...Output circuit,
13... Computer, 100... Sequence memo 18 101... Index memory 18 102... Program memory, 103
... Comparator, 104 ... Address register, 105 ... Instruction register, 106 ... Decoder, 107 ... Test flag, 110・・・・・・Gate, 111...
. . . AND gate, 112 . . . OR gate, 113 . . . Control clock generation circuit.

Claims (1)

[Claims] 1. In order to control a series of sequence operations consisting of multiple step operations, the on/off states of input/output elements are tested according to a preprogrammed sequence program, and output elements are energized or deenergized based on the test results. In a sequence controller that controls a controlled object, a plurality of test programs for testing a plurality of input/output elements serving as step step conditions correspond to each of the step operations, and a predetermined test program is performed based on the test results of the test program. storage means capable of storing at least an output program for energizing or deenergizing the output element of the step and a special output command for instructing the step to advance when the step advance condition is satisfied, and corresponding to each of the steps. an index table for storing a reading start address of a program block to be read; a program counter for specifying a read address of the storage means; a test flag operated based on a test result by a test program; In response to this, it is determined whether or not the previous test flag satisfies the condition, and if the condition is satisfied, the read start address of the next step is loaded into the program counter, and if the condition is not satisfied, A sequence controller comprising control means for loading a read start address of a step currently being executed into the program counter.