JPS5924409A - Recording system - Google Patents

Abstract

PURPOSE:To increase data discrimination window width and to increase a phase margin during data reading by converting two-bit data words 00, 01, 10 and 11 into code words 0100, 0010, 1000 and 1010, and recording them on NRZI recording basis. CONSTITUTION:A serial bit signal 5 is sent to the flip-flop (FF) 21a of a serial- parallel converting circuit 6, reset by CLKA, and shifted to FFs 21b, 12c-21h successively for every one-bit time. The outputs of the FFs 21a-21h are set in a read data register 17 during reading operation, but the outputs of the FFs are set in FFs 23a-23d by VFO1F directly or through AND circuits 22a and 22b. Consequently, data words and code words shown in the 2nd figure are converted and the outputs of the FFs 23a-23d as code words are supplied to an OR circuit 26 through AND circuits 25d, 25c, 25b and 25a opened by the VFO1F, CLKB, D, and an inverter circuit 24, outputting a write signal 8.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to a recording system, and particularly to a bit serial recording system suitable for performing data discrimination using a simple modulation circuit.

Conventional technology: MFM is widely used in conventional magnetic disk drives.
In the recording method, as shown in Figure 1, bit 1 is inverted,
It is not inverted at bit-0, but only the boundary between bit-0 and bit-0 is inverted at the boundary between bit and bit-. The inversion of bit 1 is the "data bit".

The inversion of the boundary between bit 0 and bit 0 is called a "clock bit." Assuming that the reciprocal of the data transfer rate is '■' (bit period), in the MFM recording method, the data GJ magnetization reversal interval is IT~2T, and the clock magnetization reversal interval is 11
' -1.5T.

Therefore, the maximum value of the peak shift when reading data is equal for the data bit and the clock bit, and the data discrimination window width, data calibration window width, and quad detection window width are both 0.51. It was necessary to do so. Therefore, in order to increase the phase margin when reading data,
There are problems such as the need to perform peak shift correction using a solitary shift circuit when incorporating data.

Purpose of the Invention The present invention has been made in view of the above circumstances, and its purpose is to solve the above-mentioned problems in the conventional recording method, and to increase the data discrimination window width by using a simple tone circuit. However, it is an object of the present invention to provide a recording method that can increase the phase margin when reading data.

The above object of the present invention is to convert 2-bit data words Do, 01.10 and 11 into code words 0100.0010.1000 and 1010, respectively, in a recording method that converts data words into code words and records them bit serially. However, data word 10 is converted into code word '1001 only when data words 10 and 01 are consecutive. ), NILZ
(2) Achieved by a recording method characterized by recording.

Embodiments of the Invention Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. .

FIG. 2 is a conversion diagram of data words and code words in the recording method according to the present invention. At the time of data writing, the serial bits are sequentially converted into a code word of this bit in units of 2 bits as a data word. Data word 16I2” + 3 d+ 4
a are the code words la, lb+2a, 2b, respectively
, 3a, 3b, 4a, 4b, 1a121L+3
a, 4a are data bits, lb, 2b, 3b, 4b are clock bits. Therefore, by the conversion shown in Fig. 2, consecutive serial bits are separated into N, I7 ZI
In the case of recording using the recording method, the magnetization reversal interval of data bits is I T -2.5'l', and the magnetization reversal interval of clock bits is 1.5T - 2.5T (see FIG. 5).

Figure 4 is a data transfer circuit diagram of a well-known magnetic disk device. When writing data, a plurality of data bytes are set in the write data register 2 at 1 byte by passing the signal line l from the processing device or control device (not shown), and the bit selection circuit 5 and the OR circuit The signal is passed through the hand and set one bit at a time in the serial/parallel conversion circuit 6, and then sent to the modulation circuit 7. The data is converted into a code word by a modulation circuit 7, and recorded on a disk (not shown) through a read/write circuit 9 and a head 10. In the M I''M recording system, the modulation circuit 7 includes a code word conversion circuit and a preshift circuit. When reading data, the data recorded on the disk disk is transferred to the head 10, read/write circuit 9, and data discrimination circuit. 14. The serial M column conversion circuit 6 is set to heavy serial through the OR circuit 4. The serial bit is converted into one byte in the serial/parallel conversion circuit 6, and transferred to the processing device or control device through the read data register 17 and signal M418.

When writing data, the PLO signal 11, which is information on the servo track (not shown) on the disk, is sent to the phase synchronization circuit 13, and when reading data, the RE A D D A 'l' A signal 12 is sent to the phase synchronization circuit 13. After synchronization, the clock circuit 15 outputs CLKA-D, , BRO~7, V.
Generates pulses such as FOIF, starts data discrimination from data bits and clock bits in data discrimination circuit 14, and determines the operation timing of demodulation circuit 1.6, bit selection circuit 3, serial/parallel conversion circuit 6, modulation circuit 7, etc. control.

FIG. 5 is a diagram showing an embodiment of the modulation circuit of the recording method according to the present invention. The serial bit signal 6 is sent to the 7-lip-flop (hereinafter referred to as FFJ) of the serial-parallel conversion circuit 6.
21a, is set by CLKA, and is sequentially shifted to FFs 21b to 210 . . . 21h every 1 bit time.

The outputs of FF21a to 21h are set to the read data register 17 during reading, but the outputs of FF21a to FF21h are set to the read data register 17 during writing.
~21d output directly or AND circuit 22a +
FF23a-23 by VFOIF through 22b
(It is set to l. As a result, the data word and code word shown in FIG. 2 are converted, and the code word FF23a
The output of ~23+1 is sequentially processed by AND circuit 25 d, 2 by FOIF, CLKBXD and inverter circuit 24-.
5 o, 25b 125a is opened and the write signal 8 is output through the OR circuit 20. The sixth tooth is a timing chart of the p-lock circuit 15 as shown in FIG.

It goes without saying that the modulation circuit shown in the above embodiment is just an example, and the present invention is not limited thereto.

Effects of the Invention As described above, according to the present invention, in a recording method in which a data word is converted into a code word and recorded bit serially, the 2-bit data fioo, 01°10, and 11 can be
code word 0100. However, data word 10 is converted to code word 1001 only when data words 10 and 01 are consecutive. ) and NRZ■ recording method, (1) data words can be converted into code words by pattern recognition in units of 2 pits, so the modulation circuit can be easily constructed.

e) Magnetization reversal interval is IT to 2.5T for data bits,
The four bits are 1.5T to 2.6T, and the ratio of the minimum magnetization reversal interval at which the pattern peak shift is maximum is:
Since 4=6 for data and clock, the data discrimination window width of the delta pit can be increased, and the phase margin when reading data is improved.

0, which can realize an excellent recording method with effects such as

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the conventional MFM recording method, FIG. 2 is a diagram explaining the conversion direction of data words and code words according to the present invention, FIG. 3 is a diagram explaining the recording method according to the present invention, and FIG. 4 is a diagram explaining the magnetic disk The figure below shows an example of a data transfer circuit of the device, FIG. 5 is a diagram showing a modulation circuit showing one embodiment of the present invention, and FIG. 6 is a timing chart of a click circuit. 5: Bit selection circuit, 4+OR circuit, 6: Serial-to-parallel conversion circuit, 7: Modulation circuit, 9: Continuous writing circuit, 10: Head, 14: Data discrimination circuit, 15: Clock cycle 11.1'
! Data register. Figure 2 Figure 4

Claims (1)

[Claims] In a recording method that converts a data word into a code word and records it bit serially, the 2-bit data word 00.01, 1
0 and 11 respectively as codewords 0100.0010.
However, data BIO
Data a 10 is not converted into a code word 1001 (1) only when and 01 are consecutive. ), a recording method characterized by recording using the NRZI recording method.