JPS5923971A - Digital television receiver - Google Patents

Abstract

PURPOSE:To improve the time accuracy of a horizontal synchronizing reproduction signal and to realize a stable horizontal reproduction, by finding an average horizontal period value and corrective value of horizontal synchronizing signals detected from digital video signals and obtaining the horizontal synchronizing reproduction signal. CONSTITUTION:A digital video signal 11 becomes a composite synchronizing signal after a synchronizing separation signal is separated at a separating circuit 123 for horizontal synchronism and a chromatic frequency component is removed by an LPF 127. When the counted value of a counter circuit 129 for detecting horizontal synchronizing pulse width reaches a prescribed value, the 1st horizontal synchronism detect signal (Hs') is outputted from a width detecting circuit 131. A period detecting counter 141 is a 11-bit counter which counts the sampling clock, and the counted value of the counter circuit 129 is transferred to a period memory 144 by the output of a horizontal synchronism periodicity/continuity circuit 138 in accordance with the signal from a latch pulse generating circuit 146 and the difference between the counted value and that of the last time is detected and a discrimination signal 152 is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital television receiver that digitally processes paceband video signals, and in particular to a digital television receiver that enables stable and highly accurate horizontal synchronized playback. Regarding.

[Technical background of the invention and its problems]

Conventionally, all signal processing in television receivers has been performed by analog signal processing, but there have been problems that need to be improved, particularly in analog signal processing after the video stage, as described below. In other words, in terms of performance, it is a problem caused by the processing performance on the time axis, which is considered to be a general weakness of analog signal processing.Specifically, it is a problem caused by the processing performance on the time axis, which is considered to be a general weakness of analog signal processing. These include signal separation performance, various image quality improvement performance, and synchronization performance. One problem, cost, and production is that even if the circuit is converted to RC, there are many external parts and adjustments.

In order to solve such problems, it is economized to completely digitalize the signal processing up to the color signal demodulation after the video stage.In such so-called digital television receivers, One of the major challenges is how to perform horizontal period reproduction stably and with high precision.

[Purpose of the invention]

An object of the present invention is to provide a digital television receiver that is capable of highly stable and highly accurate horizontally synchronized reproduction and that provides high quality images.

[Disguise of invention]

The present invention detects a horizontal synchronizing signal from an r-notal video signal, determines the average horizontal period (14I) of the detected signal and a correction value therefor, and calculates the average horizontal period value and the signal from the horizontal phase detection circuit. A first horizontal synchronization reproduction signal having an accuracy determined by the period of a predetermined reference clock is generated based on horizontal synchronization [
It is designed to obtain q raw signals.

Accordingly, the present invention provides a means for detecting a horizontal synchronizing signal from digital video No. 16, and a horizontal period value for a plurality of continuous periods of the horizontal synchronizing signal obtained by this means as a digital value with an accuracy of a predetermined reference clock period. υ control by the output of the judgment circuit of the first horizontal period JRI1 memory circuit to store and the judgment circuit which judges whether the difference between each period value in this memory circuit is within a predetermined value. a second horizontal cycle JIIIJ memory circuit that outputs a horizontal cycle value obtained by averaging horizontal cycle values for a plurality of cycles from the first horizontal cycle memory circuit and a correction value therefor; and the horizontal synchronization detection iM- W
A horizontal phase detection circuit compares and detects the phase between the horizontal flybank signal and the horizontal fly bank signal, and the output of the production circuit and the average horizontal period value from the second horizontal period memory circuit. Based on = ■ The first horizontal synchronous reproduction V with the accuracy of the reference clock period is reproduced, and this first horizontal period 41. The second horizontal synchronization P which is corrected according to the value and at 46 degrees below the reference clock cycle is a horizontal synchronization signal which is output as a horizontal drive signal.

[Effects of the Invention] According to the present invention, since horizontal synchronization is performed over one shift on average of the period of the horizontal synchronization detection signal, stable horizontal period reproduction is possible.

In addition, in the case of digital signal processing, the time accuracy of the horizontally periodic reproduced signal is usually determined by the period of the reference clock (the same clock as the sampling clock used when digitizing VIP" No. 1d). According to the present invention, it is possible to increase this to 41v degrees, which is less than the reference clock cycle.

Therefore, the reference clock frequency and horizontal frequency are integer multiples.
It is possible to obtain a high-quality image free of so-called gear components even when the video signal is manually input, which is not related to the above.

[Embodiments of the invention]

FIG. 1 shows a block diagram of essential parts of a digital TV receiver according to an embodiment of the present invention.

In the figure, an AC-coupled analog video signal 1 is input to a buffer circuit 2 . Buffer circuit 2
Output 3 is a low-pass filter (L
PF) Guided by 4.

The cutoff frequency of LPF 4 makes this system NTSC
.

Since it is shared by PAL, it is set to 5.5 MHz.

The band-limited video signal output buffer is
is led to circuit 8. 2777771 times when the analog video signal 1 is input in hd8 as "p-p",
/D converter (ADC) IO human power 1. (Adjusted so that No. 9 is approximately 2Vp-p. ADCI O
samples the input signal 9 with the sampling clock (φ5) 12, quantizes it to, for example, 8 bits, and outputs it.

The frequency f8 of the zangling lock (φ5) 12 is fs=4f8c (fsc; color subcarrier frequency).

φs12 is guided to the digital circuit section 61.

An 8-bit digitalized video signal synchronized with φ812 (hereinafter referred to as the DVS signal) is also sent to the digital circuit section 6 in the same way. I'm bored. All blocks within the digital circuit section 6 are composed of digital circuits. DVS
1i4 number 11 is guided to a synchronization detection/timing generation circuit 27. The synchronization detection/timing generation circuit 27 is I) VS
A synchronization pulse is detected from the signal 1.1, and various timing signals 28, 29, 30 are detected according to the synchronization pulse detection signal.
゜、? Z, generates 32.

Pedestal clamp circuit 19 ← This is a circuit for DC reproduction of L video signal 1, and υDV is determined by timing signal 32.
Detect the Bedisk level of S 18 No. 11 and set the tlill 1fRI to the wave death level or nova value.
Output IWW2O3. Output 20 of flange circuit 19
is operated by a D/A converter (+) AC) 21 and converted into an analog signal. Output 22e of DAC21",
It is superimposed on the input of the guffa amplifier circuit 8 as a flange voltage via a resistor to control its DC level.

Timing signal 3 is PLL (Phase Locke).
dL o o p) This is a timing signal necessary for the control circuit 23. The PLL control circuit 23 is a circuit for controlling the frequency and phase of the sampling clock (φ5) 120. That is, ADC 10 ~ synchronization detection/timing generation circuit 27 ~ PLL control circuit 23 ~ DAC 16 ~ VCXO 1
PI, I in the loop from 3 to ADC10.

forming a circuit. In this embodiment, basically NTSC
For input, set the PLL so that the 4th one at φ5120 matches the ■ axis, and for PAL input, match the U axis.
It takes a while.

The switching information for NTSC and PAL input is signal 15 (hereinafter NT
SC/PAL switching signal). PI, I
, the i-tuned j signal output 24 of the control circuit 23 is DA, C76.
and converted into an analog signal 14. This analog control No. 11 14 comes out and the pressure fits! I jIIll type crystal oscillator (VCXO) 13/, through this, VCXOI, ? Sampling clock φs1 is applied to the output of
Get 2.

VCXOI,? The crystal oscillator is switched by an NTSC/FAI switching signal 15 to obtain a predetermined φS. In addition, regarding the principle implementation of the PLL groan control system of the IrU example, see U.S. Patent No. 42
It is stated in the specification of No. 91332.

In FIG. 1B1, control data I7 is control data for controlling a digital TV receiver, and is received from, for example, a remote control receiver 18 circuit (not shown). The control data 17 is subcoded by a decoder 47 to control each part. This decoded control signal is used for color saturation and contrast.
The light control signal M number 4B and the hue control signal 49 are intertwined. Hue control signal 49i
j The hue is controlled by changing the phase of the sampling clock φ812° via the PLL control circuit 23. A PLL control circuit 23 (also referred to as a horizontal flyback signal (hereinafter referred to as fHFB signal) 18 is inputted to the PLL control circuit 23,
PID signal (hereinafter referred to as PID signal) 25 is generated.

The timing signal output 29 of the synchronization detection/timing generation circuit 27 is guided to the horizontal countdown circuit 32. The horizontal countdown circuit 32 performs horizontal synchronous reproduction from the timing signal 29 using the fny n signal 18 and outputs a horizontal drive signal (fHp out) 94.

The horizontal countdown circuit 32 also determines the relationship between the Zanzo ring clock (φB) 12 and the horizontal synchronization signal, and
For TSC signal input, φg! =;910/a (fa
: horizontal frequency) fI′t, , PAI, φ11
Horizontal synchronization standard mode (HMOD) when slope is 1135fa
A signal 35 is output. Synchronization detection/timing generation circuit 2
7 timing output 30 and horizontal countdown circuit 3
The output 33 of the vertical countdown circuit 32 that performs vertical synchronization reproduction is led to the vertical countdown circuit 36 that performs vertical synchronization reproduction.

The vertical countdown circuit 36 receives the regenerated vertical synchronization signal (fyDout), ? Outputs 7.

After the fHOout signal 34 is amplified by a driver circuit (fl driver) 50, it passes through a signal line 51 to a horizontal deflection system (
(not shown).

- power, fvDout multiplier 37 is led to a V runcibyte circuit 52 including vertical runzo generation and one circuit on the vertical hide divider side, and its output 53d is sent to the vertical th1 analogue (omitted).

The DVS signal 1 also includes a luminance signal (A) and a chromaticity signal (C).
), the Y-C separation circuit 38 separates the

The y-C separation circuit 38 includes a separation circuit that performs Y-C separation using vertical correlation (known as a comb filter), and a separation circuit that uses horizontal force direction sample points without using vertical correlation and performs Y-C separation using only horizontal correlation. HMOD
Signal 35 selects the isolation circuit. That is, HM6o=
When ゛t'', Y-C separation is performed using a comb filter.
At the time of D-0#, the configuration is such that Y-C separation is performed using a pantonodes filter. An N'l'SC/PAL switching signal is led to the y-C separation circuit 38, and one horizontal delay amount is switched in accordance with this switching signal. This amount of delay is 910 bits of delay for NTSC and 1135 bits of delay for PAL (known as the IH delay line).

Separated color signal (C signal) 39, pulse (φc) 26 that provides a reference phase for color demodulation, PID signal 25° control signal B 4B, burst flag and pulse BFP
2/l is folded into color grossing circuit 4.

The color process circuit 41 is an automatic color saturation control (AC
C) Based on the circuit, color kit circuit, and φ026.
! Rusu and 2suke's sync 4! The color signal (N
TSCfI, Q signal, PAL, 'cU, V 1b
It consists of a color demodulation circuit that demodulates the signal (signal). The control signal 48 input to the color process circuit 41 is A
The CCl path is set to 'do11' to control the color saturation level, that is, the intensity of the color. As the output 42 of the color process circuit 41,
Demodulated outputs r/u and Q/V are obtained.

Luminance signal separated by Y-C separation circuit 38 (Y1M number)
40 is led to the upper 2 circuit 43 of YPro. The input of the other power to the Y-pro upper 2 circuit 43 is the control data 1b No. 48, and the brightness and contrast are controlled by this signal.
be let down This Y Pro upper 2 circuit 43Q”, Prite,
Consisting of one contrast control circuit and a circuit for obtaining horizontal and vertical contour correction signals, it outputs a contrast control (II) or corrected Y signal 44. 3 by a predetermined matrix operation p.
The signals 46 are the primary colors R, G, and B. This R, G, B 1
The signal b 46 is converted back to an analog signal by the DAC 54. The DAC 54 is composed of three 8-bit DACs for R, G, and B, and its output 55 is connected to a buffer amplifier 56.
guided by. ] Each buffer amplifier 56 amplifies the input signal and leads R, G, and H outputs 57, 58, and 59 to a color output circuit (not shown). Color output circuit 1-L CR1''6θ is connected.

Next, a detailed explanation will be given of the specific configuration of the main parts shown in FIG.

First, FIG. 2 is a diagram for explaining notation regarding the following detailed explanation. Note that positive logic will be used in the following explanation.

FIG. 2(a) H: Shows an adder. For A input cuff 0 consisting of N bits and B input 7 consisting of M bits,
This shows that A10B output cuff will be 3UL bits.

Co72 indicates the carry force applied to the lowest bit. As shown in (,), signals consisting of multiple bits will be expressed as M, MfS, L-6.

Figure (b) shows the fd subtractor. A cuff 5゜8
The human cuff 7 is raised by the booster 78 and becomes the A-B output cuff 6. As shown in the figure, the input to be subtracted from among the inputs of the adder 78 is given a minus sign.

Same r! j<I (e) indicates an N-bit latch circuit.

The human power 80 is guided by the latch 83 and is latched at the rising timing of the clock 78, resulting in an output 84. Signal s in the figure
2i'; Indicates input to tv terminal R, signal 82
When is 0.1, the latch output 84 is all 0.

Further, the signal 8 in the figure indicates the human power applied to the preset terminal Pr, and when this signal 81 is 1'', 8.!l'% output 84 becomes all ``t''.

Figure (d) shows a shift register. Signal 85 indicates an input, signal 86 indicates a shift clock (φ), and No. 16 88 indicates an output. The signal 87 is an input to the reset terminal) t, and when this is 1#, the output 88 becomes all "0".

FIG. 4(e) shows a synchronous M-bit counter.

The manual clock is 90, the clock synchronous reset signal is 91, and the output is 92.

In the figure, N indicates a counter number, and j=1-M indicates M counter stages. In addition, clock 9
For a counter having a reset terminal asynchronous to 0, the reset terminal is expressed as R9.

FIG. 3(f) shows a clock synchronous type presettable counter. That is, 96 indicates preset data manual input, and 95 indicates preset timing signal input. Same figure (
g) fi, NAND type Seratricera) (Ils) shows a flip-flop, and when the S terminal input power 99 is "0", the Q output 10 becomes '1#'.

Figure (h) shows the data selector, input to 104°B
The input 105 is outputted as 108 according to the selection signal (S) 109. Output 108, sr fi is S・A+SB
becomes. That is, when S="1", the output 108 has A input 1.
04 information is output, and when 's-"o", the information of B input 105 is output to output 10B. In the following explanation, when the count state of a multi-stage counter is expressed in units of input clocks. For this, the counter output is QN from the upper bit.

When QN-1+...Q 3 + Q 21 Q 1, '000...000# is zero, and "ooo...
・001# to 1゜000...010" to 2.'000
...011'' will be expressed as 3.

(Synchronization detection/timing generation circuit) In FIG. 1, when the output 22 of the pedestal clamp DAC 2 is Ov, an analog video signal with a DC clamp voltage of 0 is obtained at the output of the buffer 60. Now, D.C.
When the clamp voltage is QV, APL (Average Picture Level
When the smallest signal of l) is input, the dynamic range of ADC1θ is 3-1.3- as shown in Figure 3.
The buffer 2, LPF 4, buffer 6, and buffer amplifier 8 shown in FIG. 1 are adjusted so that the input to the ADC 10 has a waveform as shown in 3-3.

In Figure 3, 4 Destal Levels (PDL) 3-4
00101111', horizontal synchronization signal separation level (soul), ? -5 is selected to be approximately W level of (PDL) 3-4" 00001111 M. According to the control loop of the pedestal clamp in one embodiment of the present invention, the pedestal level of the input video signal 1 is 1) D
L) 3-4 (1) is clamped. This clamp circuit will be described later.

FIG. 4 shows the state of the signal 4-1 of the pedestal clamp voltage OV and the signal 4-2 with a normal ring applied, regarding the magnitude of ADClO. In Figure 4,
(SDLV) 4-3 indicates the vertical synchronization signal separation level, and in order to ensure on-board synchronized playback especially against disturbances such as ghosts, (SDLH) From 3-5 (PDL)
Get it close to 3-4.

In row 1 (SDLV) 4-,? is 00011.
111”.

In this way, the digital video signal DYS 11 subjected to the star clamp is guided to the synchronization detection/timing generation circuit 27.

FIG. 6 shows the configuration of the synchronization detection/timing generation circuit 27. This circuit 27 is broadly divided into a separation/horizontal synchronization pulse width detection circuit system 120, a horizontal synchronization periodicity/continuity detection circuit system 12, and a timing generation circuit 122.

First, the input DVS signal 11 is for horizontal synchronization.

Horizontal circuit JIJJ crystal circuit I23 for separating synchronization signals for vertical synchronization. Vertical synchronization separation circuit 125
, the synchronization separation signal 124 and cvs Iq No. 1
26 are separated. Same le j minute 19! f W* No. 124 is an LPF 12 that removes high frequency components and dark color frequency components.
Filtered by 7. Output 12 of LPF'127
8 is a four-way synchronization (No. II (C8H)), which is led to a counter circuit 129 for horizontal period pulse width detection.The output 130 of the counter circuit 29 is inputted to a width detection circuit 131,
When this counting cycle reaches a predetermined value, the pulse width of the horizontal synchronizing signal reaches a predetermined value. ,? Is the width 1] 1 circuit 1? The output is shifted from 1. The width detection circuit 21 control dirt circuit 133 is 11s from the :114 pinching circuit 13.
'When the old month 132 is output, the counter circuit 129 is
8H1 @ No. 128 Human power is controlled so as not to be received for a certain period of time, and C8H signal 1 due to signal input with large ghost
This is to prevent horizontal synchronization malfunctions due to cracks in the 2B. C8H signal F 12 B and counter circuit output 130i: Horizontal synchronization timing that controls the rising and falling υ timing of the C8H signal 128: 1ilJ (al1
is led to circuit 135. If the horizontal synchronization timing control circuit 35 does not rise within a certain period of time from the output timing of the Hs' signal 132,
Timing generation circuit thread 12 that generates various timing signals for burst flag pulses, PLi, and Kling
2 is inactive.

In this way, the circle 7L, clamping, etc. operations are performed only when the C8H signal 12B that satisfies the predetermined conditions arrives.
A very stable PLL and clamp circuit (resistant to external disturbances) can be constructed.

[Horizontal opening] The periodicity/continuity detection circuit system 12 detects the periodicity and continuity of the horizontal synchronizing signal (actually the Is' signal), and detects the l(s' times signal) having a predetermined period and continuity. is obtained as a second horizontal synchronization detection signal (Hs multiplied signal 139).

The period detection counter 141 is an 11-stage counter that counts φS as a reference clock, and its 11-bit output 43 stores the count value for two periods (it is also stored in the possible period memory circuit 144). NJ Su1shi, rl
IIs with (April 139 horizontal opening 1υ] circumference jυ] sex/continuity sharp turn + 1WG 73g output &? and SR6Qlo from the latch/9 pulse generation circuit 146.
ut lid @J47 is generated, and due to the stiffness, the output 43 of the counter 14) is output from the memory circuit 144.
i/(-stored.

Difference output circuit z4g &'', the difference in fu'+ for two cycles in the 11j memory circuit 144 (Higashide, Kanagawa circuit 1.51
is the output 150 of the difference detection circuit i Sui 148.
1 @ issue) 1.52 wo lJj force'.

In the timing generation circuit 122, the horizontal synchronization detection circuit 1.5, ? IIs signal 139 and n
S 4 R1; Detects the falling timing of the horizontal synchronization signal from No. 136, and when the falling timing is detected, the counter 1
, 58, and controls the counter reset flip-flop 156 to start the counting operation of 4F-+
Generate i'157. The counter 158 has a six-stage configuration, and the output 159 of this counter 158 and P
LL control circuit output 5R9Q + No. J 61, 5R9
The Q2 signal 162 outputs the PLL, each weight timing signal 163 to 169 necessary for flange circuit operation, and the
Stiff flag nozzle (BFP) 2B Generated from the timing generation circuit 160 for fly, PLL, and flange.

The 61241st synchronization detection/timing generation circuit 27 will be explained in more detail. FIG. 7 shows a specific circuit diagram of the synchronization separation/horizontal synchronization width detection circuit system 120 and the horizontal synchronization periodicity/continuity detection circuit system 121 in FIG. 6.

In FIG. 7, the DvS signal 11 is sent to a comparison circuit (Compl) as a horizontal synchronization separation circuit 123.

X, given as input, is compared with the horizontal synchronization separation level (SDLH) 181, which is the human power, X2≧X
The output of 1 is obtained as a separated signal 124. Similarly, a comparison circuit (Comp2) as the vertical synchronization separation circuit 125
J s: Z-side vertical synchronization separation number (C8V) 1
26 is input. Each horizontal and vertical synchronization separation level (S
r) LII) 781, (SDLV) 183 is the third
5DLJI = ”00(011111”, 5r
) LV = "O+lO1] IN", so 1.1 each]py, circuits 180, 182 &; Ratio 1ii
jl! The 124 outputs of the J Muri path 180 are guided to a shift reno star 184 having a four-stage configuration. The shift clock of the shift reno star 184 is φS. This shift reno star 1
The output of each bit of 84 is given to the 4-man power NAND dart 185, and the output 128 is given to t2s) I (C3Ir
) is f! be hit. ft register 184";
0・Rite 1,'? , 5 H: J, PF 12
7 to 4Q, and 6J below the fsc period, that is, color frequency components, are removed.

-Sword, counter circuit 129 + 'f8A extraction circuit 13
1° start circuit 133. In the horizontal synchronization timing system n11 circuit 134, as shown in the time chart in FIG. 190 output) t is transferred to the shift reno star 191, and the width is 4 by tracing the ANDr-t 192.
A design pulse (Hs') 132 is generated. Its
'When the signal is equalized, the RS frizzo flop 193 is set fL, and its Q output 195 causes the
88, the reset signal 189 of the counter 187 is forced to "o". OR&'-) 196 is a gate for obtaining horizontal synchronization timing control output, and
87 count 1st shift is "48"' to "128" l
°'1" is output. Now, the output of the ri-to-ly6 is °
The C3I signal falls during the period “1” (C8I signal 1
28 rises) and the output 1 of NAND r-to 197
36, the waveform shown as R84R in Fig. 8 is obtained, and the RS
4 It can be seen that the fall of the R signal 136 gives the timing of the fall of the CST- (signal.The NAND dart 194 has a count value of the counter 187 of '239'.
When , the Q output 195 of the flip 70 and the output 191 is inverted. After this outputs the υHs' signal 132,
240 "-R48" = "192" (unit of φ8), the counter 187 operates so as not to receive the C8I signal input. AND dirt 1. ? ,? 4 is QIB・aS
The logic output of 4Q (described later) is output as 132-1.

Hs' 14 No. 32 is folded into the horizontal synchronization periodicity/continuity detection circuit system 12. Before explaining the detection circuit system 12, the NTSC, PA,
The corresponding range of horizontal frequencies and the operation of the synchronization detection counter 141 at the time of reception of each Iij of L will be described.

broadcast? NTsc tii No. RJ defined by skin: 4.
fsc=910. fn(fll; horizontal-frequency &'l+f
sc; 4fs at color subcarrier frequency c = 1.
4. , 3 M) I z ).

-Force, 4f sc? 9 ], No. 46 such as OfH also exist in - part's Color Par call signal generator, Video Derm, etc. In other words, Color Zabuki, Yaria Frequency f
There is a signal that has no relationship between 8c and the horizontal frequency fH. Now, if we assume that the corresponding horizontal frequency range is fn = 15.73 ± 0.5 KHz to avoid any practical problems, the sample clock φs (=4 fsc) is changed by the counter 187 within one horizontal period that overlaps with this range. 880”～”94
4# can be counted.

For PAL, 4fsc#1135fu (4/sc
#l 7.73MHz), and similarly 10=15.
Assuming 625KHz±0.5KHz, the number of φB that can be counted in one horizontal period is "1099" to "1173".
'It turns out that.

Periodicity detection of the horizontal synchronization signal must cover the above-mentioned horizontal frequency range. Therefore, the period detection counter 141 (213) in FIG. 7 that detects periodicity is
The counter is capable of counting one horizontal period with reference to 0J, and has an 11-stage configuration. When the Hs/signal 132 arrives, the counter 213 reaches a count of ``144'' in NTSC.
By presetting the count to "64" in PAL, the timing of periodicity detection can be determined easily. The circuit configuration of No. 32 can also be simplified.

Figure 9 shows the range corresponding to Hs' signal 2 and the horizontal period.
- shows the relationship between the count signal (HMasR) and the count 1 of the counter 213. As shown in the figure, only the Hs' signal 2 that is obtained continuously at a predetermined period is the horizontal synchronization detection signal H.
As s, it is obtained by the product logic shown as f1s=H8'·HMa a Iζ. 5R6Q1 is the shift register 2 that accumulates this Hg-1: No. 139 and φsk shift clock.
15 output is shown. 9-1 and 9-2 in FIG. 9 indicate the count status when receiving the count 21 J(7) NTSC, PAL =+S signal.

Mg l 0 Figure Hs' 1i = No. 132 circumference (4J
A time chart for detecting J nature/continuity is shown. HMa
When the sR signal is received as an NTSC signal, the counter 21 and ? It rises at a count of 1024" and falls in synchronization with the fall of the Hs' signal. Also,
When the 11s' signal is missing as shown in 10-3, HM
The asR signal falls at a count of "1088", and the counter 213 waits for the arrival of the next Hs' signal while being preset to a count of 144".

When the old us' signal is obtained as shown in 10-4,
An Hs' signal H8iW indicated by 1o-5 is obtained.

The basic operation is the same when the PAL signal G is used.

As shown in FIG. 10, it is reasonable to assume that the horizontal synchronization detection signal H11 can be obtained as a signal with high precision independent of disturbances.

In FIG. 7, as the output of OR goo 1207) Lh
'la s R1r3 is obtained, AND gate 208
f (s signal) 39 is used as the output. The Q output of RS Frizzo 70 and 212 is reset by the inversion of Hs' signal 1.12 and set by the output of NOR dart 211.
Q) is given. The preset signal of counter 213 is OR
It is obtained as the output 203 of dart 204. The preset data generation circuit 201 that is loaded with the NTSC signal is
As expected, when receiving the NTSC1 signal, the digital value ゛00010010000 corresponds to ``144# count''.
", and upon reception of the PAL signal, a digital signal I'00001000000 corresponding to the '64# count" is generated, respectively.

Ha signal 139 is directed to shift register 215. Q! of this shift register 215! Output 147 is count 2
The timing for latching the 1.1-bit output 214 of No. 13 to the latch 216 is provided. The output 149 of latch 216 is applied to latch 217 in four steps. These two stages of latches 21
6.217 is uG 1's horizontal circumference 1% Jl me seven circuit 14
The counter 213 has two cycles of data from the counter 213. 1 of latches 216 and 217
It is the music reduction device 219 as the difference detection circuit 148 that detects the difference of 1 white, and the difference output 220 is determined at the judgment time h"r'115.
Output to 1.

Wholesaler 1: t, 11, no output 2 at route 15
Out of 20 11 bits of data, 3rd place 9 bits)
AND gate 22 node and ANr) +'- gate 222, and OR dart 221.222 output.
Input [7 and output I) CK (,4 No. 152 is obtained. That is, output 149 of latch 216 and latch 217
If the difference in the output 218 is within 3”, DCK ha
No. 152 becomes "l."Hs1'g No. 139. Output J 49 of latch 216, DCK signal J52. Output 147I of shift register 215 is led to horizontal current down circuit 32 in FIG.

FIG. 11 shows a more specific configuration of the burst flag/PLL/lamp evening/emming generation circuit thread 122. H
The inverted No. 18 No. 232 of the 8x No. 139 sets it's free, the D0 toggle 234, and the R84n (Fi No. 136 resets this flip-flop 234. This is a signal that rises in synchronization with the trailing edge) and is guided to the shift register 236.The Q1 output 154 of the shift register 236 is a one-stage counter (flip-def 7').
237VC led. Now, Ql output 1 of the shift register
When 54 changes from '0# to '1'', 94 of counter 237
1 output 157 is 0#, which causes υ counter 238
At t, the reset state is released and counting starts. The counter 238 has a six-stage configuration with outputs Q, ? 6,
Q J 5.

A self-reset is applied via the NAND dart 239 using the logic of Q33.

The operation of the timing generation circuit 160 is shown in FIG. In FIG. 12, the CH8 signal (output of the LPF 127 in FIG. 7), the Hs signal 139. φS, shift register 236
Q1 output of 154. Q of counter 237, 41 output 15
7. Q of counter 238,? 7, Q,? 2
. . . Corresponding to the Q36 output, various timing signals are shown together with the count I of the counter 238. These timing signals people output 28.163.164.1
65.166, 167.168゜169.157,23
0, 161, and 162 will be explained in detail in 4.111 of the detailed description of the general control circuit of the flag circuit 1, which will be described later.

(Bedestel Clamp Circuit) The hard destil clamp circuit 19 in Fig. 1 is as shown in Fig. 4-2.
As shown by the waveform, the best signal level of the incoming DV81n No. 1 is (Pl)L), ? -4pa() old 011
This is a circuit that clamps on the 11” band.

613 shows a specific circuit diagram of the destal clamp circuit 19. H8r) signal 280 in the figure is H@signal 139
This is a signal indicating a synchronization detection state which becomes 1# when fn is set, and is input to the synchronization detection determination circuit 285. Now, r
(If SD="0", that is, synchronization detection is not performed, it is not possible to obtain the timing information (for example, RFP 2 B) to apply the pedestal clamp, so it is necessary to cut out the synchronization signal part first. .For this reason 1
(When the SD signal 280 changes from "1" to "0", the shift register 284 detects the falling edge of the H8D signal 280,
This detection signal 276 (output of the gate 275) causes the latch 27 to store the clamp pressure as a digital i.
Reset 2. Output 20 of latch 272 is all °
When it becomes ``0'', Kurambiya IE: (DAC2 in Figure 1
1 output 22) becomes Ov, and the clamp control system is set to the initial state.

Generally, if there is a video signal input, the relationship between the ADC's dynamic range and the signal at the time of initial setting is
It is shown as 4-1 in the figure. In FIG. 13, the output of the gate 252 that takes the OR logic of the 8-bit signal that is the DVS signal 11 is output only during the period when the input signal 1 crosses the LSB side end of the dynamic range of ADClo. When O/l/ becomes "0", °t becomes On. This r −) 252 output rr
It is led to an i8-stage (four-stage shift register 253).

NOR with all outputs of shift register 253 as input
The output 255 of the Dart 254 is converted into a signal, and the output of the Dart 252 is passed through the LPF.
．． 1) A level detection circuit 28 for the VS signal 1 is configured.The rise timing of the output signal 255 of this detection circuit 28 is determined by the NAND gate 2.
56 and sets the RS flip-flop 257. Q output 258IrJ of this flip-flop 257
, , 1.0 bits are led to the B input of the data selector 269. At this time, the B input data of the r-data selector 269 is converted to MSB 1t by an encoder (not shown).
1! I to ' 11111110 (assumed to be input after 10" conversion. 10 bit output 270 of data selector 269 and 12 bit output 273 of latch 272
(reduced by matching LSB) 1. z'is in vessel 27 no
'L' 4 is output from I'I.The timing of that signal or the 03 output of the shift reno star 253 (AND output 278
1q is loaded into the old latch 272 at the output timing).

-1- By repeating the operations described above, the clamp level is increased until a clamp level of 6; ll11'! ei -'i l 39 is 1?
When it is stolen, 1ist) -"]" roaring period ('i
jj output] J (one horse becomes TJSf) - '1', the A signal 268 is led to the output 270 of the output selector 269 that constitutes the switching circuit 283, and the 'ξ destination clamp mode is established. Become. ■) vSIM No. 1 is a reduction vJ device 2
At 50 (PDL),? s J-0010111
6 戊k) will be applied for 1" (7). 1jj1. Uki 25
The sign (8gn) bit of the output of 0 is the DVC8 (A No. 286)
It leads to 11 circuits. t, decrease 1'? Vessel 2s.

The 8-bit output containing the sgn bit of
He, Funeral 1-11. ! ! , is the %φS period shown in FIG. 12 from counter 238 at 1, Q,? 1 output is sampled at 230.

Adder 265. The latch 266 is a digital integration circuit 2
82. The number of integrations is determined by the φ input 163 of the latch 266. In order to perform the integration of the color burst period as shown in FIG. 12, the number of integrations is set to 12. Of the output 267 of the latch 266, a 10-bit output 268 with the lower two bits discarded is led to the input of the data selector 269.

The Co input of the adder A-265 is a wobbling signal derived from the Q32 output 241 from the counter 238 in FIG. 11, thereby improving the accuracy of the shift lamp. When the above-described 12 integrations are completed, the latch 266 receives the L signal from the timing generation circuit 160.
A reset is applied at the timing of the 21st signal 164.

Equalizer 271. The latch 272 also constitutes a deep integration circuit 284, and the input 270 of the subtracter 27 is all 0.
The integral is folded back so that ``, !llll
The pedestal level becomes stable. Note that the 1-'+2φ1 gear signal 169 and r- from the timing generation circuit 160
The output of the gate 278 becomes a signal 279 that provides a clock for the launch 272, and its inverted output 20-1 is the DA for the flange.
It is used as a clock for the data latch of C21 (omitted in FIG. 1).

(PLL, control circuit) P[, L control circuit 23) Since the principle configuration example is described in the specification of US Pat. No. 4.29133230, the specific circuit configuration and percent Let's talk about the symptoms.

FIG. 14 is a block diagram showing a schematic configuration of the PLL control circuit 23. The error detection circuit 300 uses timing signals L7φ1 signal 162, L2R signal 164 + L
It is controlled by the 6R signal 165 to perform an integral calculation on the DVS signal 1. Note that the sampling point of P43 is shown on the color burst waveform 5-1 in FIG. In FIG. 5, 5-2 indicates a period (burst period) during which calculation is performed, and in this embodiment, 5-2 was used as 6.

That is, the integral calculation of the above equation (1) is performed for every six strike periods.

If the target sampling phase is θ with respect to the phase of the 31: sea urchin color sample shown in Figure 5, then i
The prefectural difference signals are as follows. (2) Equation 11 [↓The error calculation circuit performs the difference 31? 02, and its ゛〈Tora calculation power,? 0.
7 i, j: Guided to error integration circuit l118304. 1
The output 24 of the 1-W difference integrator circuit 304 is led to the DAC 16, which applies the PLL. (2) Formula,
1 linear phase of L θ (actually, by changing the t, an OO value to Eif variation, it is possible to print an arbitrary nano 0 ring phase 0. In addition, the hue can be controlled by making the value of tan θ variable. That is, upon receiving the control signal 49, the hue control data generation circuit 305 selects a value of tanθ according to predetermined control data, and outputs a signal 306 indicating the value to the error calculation circuit 302. do.

-Katana, integral calculation result of equation (1) in 011, tamashi error detection circuit, ? The sgn bit of the output 301 of 00 is led to the reference sampling phase detection circuit 314, where the reference phase A? which survives the reference sampling phase is detected. A rule 315 is generated. Does this reference phase/ya Lus 315 continuously generate base 1\', /# Lus? l11. is guided to the quasi-pulse generation circuit 316, and the reference position (11, that is, N
■輔 in the case of TSC, U 1ll11 in the case of PAL
φc1 words 26 indicating OL, respectively, are obtained as base thread pulses. Essentially, for PAL, the U-axis is obtained as a reference phase and a PAL identity signal is required.

The DVC8 signal 286 consisting of 1 bit is guided to the burst detection integration circuit 308, and the 6-cycle period φ of the color burst is
At the same time as being sampled with the c color number 26, the Zanzo ring result is integrated. The integration result 308 is led to a time constant circuit (residing in the integration circuit) 310 for obtaining stability of the PAL identity signal. The output 311 of the time constant circuit 310, the PID-1, No. 1 25, and the timing signal LI2φI No. 5 169 cause the PAL eye point to be detected in the PAL identity group fart dart circuit 312.
It is determined whether or not the 1st and 4th staff members are working (1^), and there is no affiliation, 1 is output, and a reset signal 37J is output.PAL-ident generation circuit 307 is 1,
hyB4'r' is a one-stage counter with 184 inputs, and a PID signal is output as its count output. A reset signal 313 is input to the reset terminal of this counter. [Do Jki standard - Linsoling phase is Q to U1ura in PAL, I) According to ID1-No. 25, it is a phase of earth 450 for Perth l-f\1kan.

FIG. 15 shows a more specific circuit of the PL + ill + i11 circuit 23 (h complete display 4~. DV8 double edition 11 is asked by the latch 320. Reset number 16 of the lap-320 is LIAI number 165. Latch 320 output 321
is directed to subtractor 322. Output 32 of reducer A, device 322
3 is exposed 2I to latch 324, and output 3 of latch 324
25 is led to latch 327.

The output 328 of latch 327 consists of 12 bits and decreases t
? +”4 s This is the input for 22 strokes. This output is 32
An output 330 of 8 bits from the MSB side of 8 is led to the error calculator circuit 302. The 12-bit output 325 of the latch 320 also has an error rjt H-circuit? Guided to 02.

The L2R1 signal 164 and the L7φ signal 162 are signals that control the error calculation circuit 302, and the output latch 324 of the latch 324 in the integral calculation result shown in equation (1)
, 327 is controlled by σV. 326 , , ? 29 is led to a reference Zanzo ring phase detection circuit 314.

Now, with NTSC, the Q axis (q#1+) with θ-33° can be detected, and with PAL, with θ=±45°, the U axis can be detected under the control of the PID signal.

In FIG. 15, AND dart 338 is the Q-axis detection cage, and AND dart 3. ? 9, ? 40 or U
This is the date for I+ detection. Each Kate s3s~,?
40 output t'', which leads to an OR date 341. The output 315 of the OR dart 341 is sent to the reference pulse generation circuit 316 J4. The shift register 354 is for detecting the reference +1111, and its Q1 output 355 is used as the counter 356.
q-Reset. Q62 output of counter 356, 95
7 ilJ: Input to the shift register 358, synchronized with the φS clock, and Q! of the shift register 358. From the output, φC and M26 are obtained. This φC signal 26
The rising timing of will indicate the Q-axis. 1st
Figure 6 shows L7φ1i No. 162, L6R signal 1 e 5
．． sRc+R (Q No. 167° Shiftre Nosta 354
input 315 and its Q1 output 355 + Q61
+Q62 output 357 of counter 356. φS and the first
Each waveform of the Q output of the flip-flop R851 in FIG. 1 is shown.

Hue control was in 2-bit steps.

The control data 49 is decoded by a data decoder 333 and encoded by an encoder ROM E 35. For NTSC, control data 49 is 00
When #, the value of θ is 33° (center value), when “01”, θ=
27°, when '10' θ = 370, when '11'' θ
= 410 (Z) and tan 330 is sg
If we approximate with 6 bits including n, jan 33°= ”
0HHOI” and similarly JAN 27
°='010000'', tan 37'=
"011000'.

jan410="(111100").

In the case of PAL, the encoded value is controlled by prn information 25. When using PALO, control data” o o
" is θ=±45°, and the encoded output is approximated by 7 bits including ggn. When PID-"1", 01111
11” is obtained as the encoded output, PID-”O” (
(hereinafter simply referred to as KA10), "1000000' is ('47;).nian) o -rua'-ta"
01 ” (1 = PID te'0110000 ”
Wow, get PID f "1000000". When the control data is ``10'', set 0111111 on HD,
I) Obtain "1110000" as ID.

When control data is "11", PID is '01111'
Get '1100000' by raining 1".

In this way, regarding hue control, N1'SC
A predetermined encoded output (output of encoder 335) 336 is obtained according to the signal and PID signal 25. An output 336 of the encoder 335 indicates one unit of tanθ and is led to the error calculation circuit 302.

The error calculation circuit 302 includes a multiplier 332 that multiplies the output 325 of the latch 324 and the output 336 of the encoder 3350, and an adder 33 that adds the output 337 of the multiplier 332 and the output 330 of the latch 327. Timing signal (#,,6) 16g iJ, Higashi Station, power of 332 (1), gives timing. Output 3 of adder 331
43 is input to the adder 344 in the error A noble circuit 304. The other input of adder 344 is the output 352 of latch 351. Output 346 of adder 344 is led to latch 351. L12φ1g is latch 351
AND dart 348 while giving the latch timing of
．． 347, and is used for the detection timing of auto-70- and under-slow.

These boosters 344. Latch 35 J, ANI) Dart 347. ．． 14B constitutes an error integration circuit 304. The latch 351 has a 13-bit configuration, with the MSB
The 9-bit output 24 from the side is the DAC for PI and L shown in Figure 1.
I am led to 16.

The dart 348 is an O74-70 detection case, and when the output 349 is 1", it presets the latch 351 and makes the output all "bi".
7! m, i: underflow detection date, output 350
When is 1'', the latch 351 is reset and its outputs are all '0#.

Note that the output 353 of the adder a 44 indicates an overflow output.

In FIG. 15, the nvcs (Ei number 286 is led to an adder 361, and the output 362 of the adder 361 is led to a latch 363. The AND gate 359 outputs a U-axis transverse wave phase signal 360 in PAL. , and the latch 363 as a clock.

These f-t359. Adder 361. The latch 363 constitutes a burst detection integration circuit 308. The sgn output 365 of this integration circuit 308 is guided to a time constant circuit 310 and further integrated.

The time constant circuit 310 includes an adder 366, an sgn output 368 of this adder 366, and other 5-bit outputs 36
It is mainly composed of latches 371 and 372 that latch 7.

Note that the AND gate 373 and the NOR dart 374 are for detecting overflow and underflow, respectively, and the detection timing signal is a signal φi=168. latch 3
71 output 377 is PAL ident judgment dart circuit 3
Guided by 79. Now, if the Q71 output 381 of the PAL ident generation force counter 380 is 1" and the output 377 of the latch 371 is "1", the counter 380 is reset by the reset signal 313 at the timing of the L12φ signal 169, and the U-axis The transverse wave and the PAL ident are returned to the specified conditions.Then, P is output to the Q71 output of the counter 380.
II) A signal 25 is obtained.

(Horizontal Countdown Circuit) A detailed block diagram of the horizontal countdown circuit 32 in FIG. 1 is shown in 171ffl. The horizontal countdown circuit 32 consists of four thick cover blocks 461, 462, 46.
．． ”), 464. Output L4 of the periodic memory circuit 144 in FIG. 6 where continuity and periodicity are detected.
A second horizontal period memory circuit 461 stores the period of the horizontal synchronization signal coming from the out signal 149, the timing signal 147, and the DCK output 152 of the determination circuit 15.゛Also, the horizontal period data 42 stored in this way
4 as input, detects the relationship between the incoming horizontal frequency III and φS, and detects the HMOD signal 400 indicating the horizontal standard mode.
The horizontal standard mode detection circuit 464 determines this.

[-1M0D signal 400 is Y-C as shown in FIG.
When p is guided by the separation circuit 38 and HMOD-“1”,
As is well known, the y-c separation circuit 38 uses line correlation to separate Y and C (M numbers) (this is known as a comb filter).

First, when HMOD = "0", if Y and C separation is performed using line correlation, the separation may become very poor in some cases (sample points on the IH delay line are very close to each other on the screen). (if the force is in force), CIW for Y and C is performed by BPF using well-known sample points in the horizontal force direction. In this way, f(MOD signal 400 turns off the operation of Y-(1) separation circuit 38) Q+ai+.

The output 424 of the horizontal rotation 1 memory circuit 461 is led to the water 1'-synchronous regeneration circuit 462, and this regeneration circuit 462 generates the horizontal drive (M + j (, fHD out ) 34
Attach. fHFB Tsukuda No. 1 signal arrives) Ls I No. 11 No. 1
39 crying 39 Comparing, if there is no IJr constant phase relationship,
Outputting the signal 458 to the horizontal J0j reproducing circuit 462,
The circuit for pulling in the phase is the horizontal phase detection circuit 463.

]-1 Each block of 17th shi 1 461,462°46
3.464 will be explained in more detail.

(,) Horizontal cycle] Memory circuit 461L4out signal 149 is guided to subtracter 401.

- power, 5R from the latch pulse generation circuit 146 of FIG.
6Q1 out 4? The r number 147 is led to a memory timing generation circuit 408 for horizontal cycles, and various timing signals 409, 410 and 411 are generated in this circuit 40B. These timing signals 409, 410, and 411 are controlled by the DCK signal 152 from the determination circuit 151 in FIG. The output 402 of the reducer 40 is input to a difference detection dart circuit 405, and its difference value is detected.

This dart circuit 405 supplies control signals 403-1 and 407 to the time constant switching circuit 403 and control signal generation dart circuit 417 depending on the magnitude of the difference value, and also supplies wobbling signals to the adder 412 when the difference value is zero. A signal 406 is provided. The time constant switching circuit 403 operates to control the time constant of the system according to the above difference value.
The output 404 of is directed to an adder 412. Adder 41
The other input of 2 is 16 bits consisting of 11 bits on the MSB side, and is derived from the output 424 of the horizontal period value memory circuit 421 and the output 423 of the LSB 11115 bits behind the 16 bits of the horizontal period correction memory circuit 422 (Z). This is the signal 425. Of the 16 bits output from the adder 6412, the MSB 1411111 bits are stored in the switching circuit 415. The output 427 of the Fi11 quasi-horizontal period generating circuit 426 is led to the other input of the 9-channel switching circuit 415. If the horizontal period value does not satisfy a predetermined condition (for example, Pow
erON), the abnormality in the horizontal period is detected by the abnormality 1 direct detection circuit 43 and a detection 1 signal 432 is sent to the horizontal period value preset circuit 433.

The horizontal period value preset circuit 423 goes high together with the signal 432.
8D 1=i By inputting the month 280, the signal 434 is supplied to the control signal generation dart circuit 417.

As a result, the dart circuit 417 is connected to the horizontal synchronization value memory circuit 4.
21 is supplied with a preset timing signal 419, and a switching circuit 415 is supplied with a switching signal 420, through which the memory circuit 421 is preset to a standard horizontal period value given by a signal 427.

FIG. 18 shows a specific circuit configuration of the horizontal periodic memory circuit 46. In FIG. 18, the horizontal period memory timing generation circuit 408 includes a six-stage shift register 484,
It is composed of AND dart 485°RS frizzo flop 491. FIG. 23 shows a time chart of each timing signal.

As can be understood from Fig. 23, case °-1485 is r)
(J(When signal 152 is °゛1#, self-reset fi?
``Output f 4 B 7, Q of shift register 484
There will be no output after I'll. That is, if the detected difference is φS and the value is greater than or equal to 3N, the periodic memory does not perform any operation and maintains the previous state.

The output of the subtracter 401 has an effective bit length of 8 bits, and the 8 bits, number 13 474, is the data selector 47.
50B human power. - signal 474, of the 8-bit signal 474, No. 11 of the LSB side 3 bits 473 iIJ: Data selector 4750A input 0 and \M of the signal 474
SB @116 pit signal 472, LSB side 2-bit signal 47] are sent to the hanger 405 when the difference is detected.
The power is 7, the difference between the two is 7 power! +y tt 0
The magnitude of the output of 7 is
・Circuit 405 plane, 6 manpower AN[) ke-
G 479. 6 Human power Ni5 rya Kate
6 outputs of 480 float to OIL port 4B2.

0R) f"-to 482 output 4786-J, difference is sufficient"
If the value is less than 3'', it will be ``1'', and if it is greater than 7''3'', it will be 0''.

Data selector 475 output 4θ4 stripes 11 bits 41
It has become N. For example, when the output of the subtractor 40 is +°゛2''', the input 473 inputs °'oto'', and the output 478 of the dart 482 is ``t''.
” At this time, the output 404 Sea 1 of the garter selector 475: “FlooOOOOOOIO” from the MSB side.
becomes. - When the output of the device 01 is +゛8'', the B input 474 receives ``OOO0010 (J'', and 0Il)f'' - the output 478 of the output 482 is 0''
becomes. At this time, the output 404 of the data selector 475 is "
00000100000”.

That is, when the difference (signal 474) is large, the time constant is made small to speed up the convergence of the system, which will be described later, and when the difference is small, the time constant is made large to ensure the stability of the system. Therefore, the horizontal period memory circuit 46 converges quickly, and when it converges to a certain 4iK, the time constant is increased, so that the horizontal period memory circuit 46 can be obtained with high performance.

Data selector 4750 output 404 is directed to adder 412. The other input to the adder 412 is a 16-bit signal 425 consisting of the 11-bit output 424 of the horizontal period value memory circuit 412 and the 5-bit outputs 514 and 576 of the horizontal period correction memory circuit 422. Internal input 4
04°425 is added with the LSB aligned.

The wobbling power 406 (adds 1″ to the adder LSB) of the adder Jfi43472 is the difference detection dart circuit 4
This is obtained as the output of AND dart 483 when 05 is detected as zero.

Of the output 476 of the adder 412 consisting of 16 bits, M
The SB side 11 bit 508 is the 8th bit of the data selector 509.
Guided by human power. 3 pits following this 1, 507 i
r, j half cycle Nli is led to the latch 513 in the positive memory circuit 422, and LSB flllll 2 bits←
1. Latch 515 is used. Data selector 5
09 A human power 427 outputs a standard horizontal cycle.
ing. In other words, the value of '1054'' in NTSC is '1 (10
00/1110", PAL "'1199"(recon"l)
001010JIII”.Data selector, 50
The output 510 of 9 is applied to a latch 512.

41', In Fig. 18, the different value detection dirt circuit 431 that detects an abnormality in the horizontal period j4J1 value is predetermined], and is a gate circuit that determines whether there is a period 1 plane in the four or is old. In SC, the period value is 1024'' to 1088.
``1・(6-person ANI) Key) 51
7 (broil. In PAL, "1.1601' ~
“AND whether or not it is within 'J224”) 519
If the period iTh+424 is not at a predetermined value, the output 522 of the NOR gate 52 becomes ulm, which is obtained as 0Rr-) 503. OR ke °-) 5
The input of the other force of 01 is ll5D 1 convex sign 280.

When the input 502 of the shift reno star 503 becomes l'', A
The output 505 of the ND dart 504 becomes '1'', and this output 505 causes the data selector 509 to open to 1.AND
At this time, the r-to 500 outputs 499 as the φS clock. The output 499 of this AND gate 499 and the Q5 output 49.0 of the shift resistor 484 are sent to an OR gate 497. The output 498 of the OR dart 497 becomes the human power for closing the latches 512, 513, and 515.

Output 505 of gate 5θ4 is switched, resets latch 513 and traces OR gate 495 to latch 515.
Reset. - Signal 477 and Noritsubu flop 49
Q output of 4 9 2 if AND da −
G 494. The latch 515 is reset through the OR key 495. Fig. 24 shows a time chart of the horizontal cycle 1-shift presetting circuit.

(b) Horizontal standard mode detection circuit 464 FIG. 19 shows a detailed circuit diagram of the horizontal standard mode detection circuit 464. In FIG. 19, the horizontal standard mode detection dart circuit 428
detects candy at the output 424 of the horizontal period value memory circuit 421, and outputs °'l'' at the output 550 (if it can be corrected to the vote standard mode).

In the 20th ζ1, Ni'SC, IIAL, (
I; 17 quasi-mode is set, ru is included. now,
Considering 1 shift of N-□ as 1'n, the value of N becomes "9 (14" to I'40D-") to +1 for the input of 9161+, as shown at 560 in Figure 20. 44 votes (indicates mode input), and other than i1, i■ (MOD-"0").

, 56o stores the output of the horizontal period value memory circuit 421 at the 18th
The release date of the latch 512 of 1/ζ is shown in the same month. That is, when the latch 512 (1) output -c M, "1048'~", 10 fi O" is HIV
I (JD = “1” range. 562, 5
6.9 was similarly shown for PAL IfC. FAI,
If you look at the output of latch 512 at μ5, it is "1192".
~ rlMOD = ” for the input “1208”
l”.

In Figure 19, dart, 540, 541, 542 are 1
= to detect HFviOn of JTsc, and 544, 545, 547 are I) AL, H
- It is not for detecting MOD. Eidejo bow 550
is input to the AND gate 551 together with the timing signal 5R12Qsr=493, and the counter 55
5 and all RS flip-flops 558 are set. Also, the inversion signal of signal 550 is signal 493
with ANr) input to date 552, counter 5
55 input signals.

The RS flip-flop 558 is reset by the counter 55.
This is done by the output 557 of the NAND dart 556 which ANDs the outputs of each of the 5. Integrating circuit 4 as shown
30, for the human power that turns HMOD-ON, it is necessary that the integration of 8 continuous horizontal synchronized human power is established, and this integration improves the stability of the HMOD No. 4 signal. Therefore, the result is The stability of Y-C separation is maintained at its peak.

(c) Horizontal synchronization regeneration circuit 462 In FIG. 17, the horizontal synchronization regeneration circuit 462 basically operates the horizontal synchronization counter circuit 445 that reproduces the horizontal synchronization signal according to the horizontal period value l715 output 424, and performs a predetermined 7'HD out (obtains No. 8 34).

FIG. 21 shows a specific circuit configuration of the horizontal synchronization reproducing circuit 462. Horizontal counter preset value calculation times +yh 4.9
s includes the output 424 of the latch 512 in FIG.
0 is derived and added by adder 570-1. The output 460 of the encoder circuit 495 is data for controlling the count number of the horizontal counter and drawing in the horizontal phase.
If the phases of the s count signal 39 and the fnpB signal 18 match, all will be ``0''J.The output of the adder 570-1 consisting of 11 bits is guided to the latch 570-2, and the phase is synchronized with the φ8 count signal. Output 43 of Unich 570-2
61. The signal is led to a coincidence detection circuit 437 consisting of an r11-bit comparator 57). The other input to comparator 57 is the 11 bit output of horizontal counter 572. Comparator 571
The coincidence output 438 is the preset 7At of the counter 572.
-F'PT, and at the same time, the shift register 576 in the horizontal drive pulse generation circuit 439 is asked.

Q of shift register 576, output 577 sets RS flip-flop 578.

Q1 output 441 of shift register 576 is output from counter 57
This is a signal indicating 1H notification that preset has been applied to 2.
The signal is detected by the horizontal phase detection circuit 463.

Horizontal counter 572 fd fno out i δ 34
This counter is composed of an 11-stage counter that uses φS as a clock input. In the case of NTSC, the preset data of this counter 572 is converted into a count value of 1.
45” and 116 s H in PAL, these are given by the reset data generation circuit 574. This preset value is applied to the horizontal period detection counter 21 in FIG.
A value that is 91 counts higher than the preset value of 3 is used.

Then, the count 1 of 573 is taken out as a THC signal 447 through AND gate 573.

The reset signal of the RS flip-flop 578 in the horizontal drive signal and pulse generation circuit 439 is the dirt signal 579, 580.
, 581. A fuoIM number 440 is obtained at the output of flip-flop 578. f'Ho signal 44
0 is the drive number controlled in φS clock units! It's Luz.

FIG. 25 shows the output 445 of the comparator 57. Ql output 44 of shift register 576, fHD signal 440, and N
'l' 8C shows the count value of the counter 572 in PAL.

Figure 26 shows the general fHDcj No. 440, /HF
The summary and phase relationship of the count value of the counter 522 in B-8 1B, THc signal 447, OJ:hirtn'sc, and IJAL are shown. Same figure 1'H
It can be seen that the 832 count, which is the rise timing of the C signal 447, is located approximately in the middle of one period of the fuym signal 18.

The 5-bit output (3 bits s 74 on the MSB side, 2 bits 516 on the LSB side) of the horizontal period correction memory circuit 422 in FIG. 18 is led to a decoder circuit 448.

In FIG. 21, the decoder circuits 448 and 590 are composed of 5-bit manual decoders with 32 outputs.

When the 5-bit input is "00000#", the decoder 590
The first decode output 587 becomes '1'.
0001'', the second decode output 588 is l''.

When “11111”, the final decode output 589 is “’1”
becomes. Output 581°588 of decoder 590,...
589 is the AND key 9 in the selection middle circuit 444.
1.583, 584...585 one sword input.

The fIID No. 4 signal is a horizontal drive pulse delay 9 of a tap body consisting of 62 inverter rows. I=i lj4ro4
42, and at the same time guided to the cage 583. The total delay end of the 62 inverter rows of the delay circuit 442 is preferably one period of φ8, and if we assume that φS is NTSC, the total amount of delay is 70 n5ec, and the delay for one inverter stage is approximately 1 It will be about n5ec. 5F12 for every two inverters from delay circuit 442
, 586, and each output is an AND signal in the selected dirt circuit 444) 583, 584...
-Given to 585 single power input. AND dirt 58
3 # Output 584,...585, a total of 32 bits.
R gate 58611Cil is applied, and /aDout signal 34 is obtained at the output of OR gate 586.

In this way, the output obtained by delaying /HD signal 0 is selected according to the output of the horizontal period correction memory circuit 422, and J'
The uoout signal 34 is set to No. 1. As a result, fnDo
In the case of t+t, a highly accurate resolution can be obtained in the φS clock unit or υσ.

FIG. 29 is a diagram for explaining this effect in correspondence with specific turns on the 1V screen. Figure 29 (
, ) indicates a vertical line that should originally be displayed on the screen. The same figure (b
) li: This is an example of displaying vertical lines when J°□1) out li No. 74 is output to φ day type br without performing the horizontal period correction.

When φg'=N'/u (that is, when the relationship between φS and fu is not an integral multiple, as is the case with PAL's standard 1st day number), the vertical line that should originally be displayed (the broken line in the figure) )29-
4 is displayed as shown by the solid line, 29-1°29-2
．． As shown at point 29-3, a gear having a width of φS period is generated. The φ8 period is approximately 56 nsec in PAL.

Therefore, this gear can be detected with the naked eye. Unless this gear is below the detection limit of the naked eye on the screen, it will not be sufficient for a high-definition television receiver.

In this embodiment, in order to bring this gear sufficiently below the detection limit, as described above, the delay amount of the fHD signal 440 in FIG. Through this control, the resolution of horizontal synchronous reproduction is improved to below the φS unit.

As a result, as shown in Fig. 29(c), the gear component is theoretically reduced by 1/32 K compared to that shown in Fig. 29(b),
No problem at all in practice (d) Horizontal phase detection circuit 463 In FIG. 17, the horizontal phase detection circuit 463 detects the incoming horizontal synchronization signal (Hs signal 139 as an actual signal)
, detects the phase relationship between the furs signal 18, controls the horizontal synchronization regeneration circuit 462 according to the detected phase information, and as a result pulls the phase of the Hs signal 139 and /HP s signal 18 into a predetermined phase relationship. This is a useless circuit.

In this case, the structure is such that the phase pull-in is performed continuously and the pull-in time is fast.

FIG. 22 shows a specific circuit configuration of the horizontal phase detection circuit 463. In FIG. 22, the frKFR signal 18 is htvB
NA
The rise erupts at ND gate 60. /'H
When the FB signal 18 rises four times, its detection (
ii No. 45), the ttS flip-flop 60 in the J'HFR timing generation counter circuit 463,? Set sle. The Q output 604 of the flip-flop 603 is input to a preset terminal of a counter 641 having eight stages. Preset value of counter 641: ``20'' count for Q or NTSC, ``02'' count for PAL, and the following comparison pulse is N1'SC.

PAL is shared. The output 605 of the counter 64 is sent to the comparison noculus generation circuit 454.

Comparison! The signal generation circuit 454 receives the incoming I(s signal 13
Various timing signals (comparison/reference) of the fHrs signal 18 with respect to the fHrs signal 18 are generated. The comparison pulse is 1'P1. T.P.
2...6 types of legs of TP6, dirt 6 as shown
06,607,608,609,610゜611 Top and RS flip 70 knob 618,619゜620.621
, 622 is made. The output 612 of the dirt 61 is T
PI, output 624 of flip 70 619 is T
P2, the output 623 of the flip-flop 618 is TP3,
The output 626 of the flip-flop f620 is TP4, and the output 628 of the flip-flop 622 is TP5. The output 627 of 62 is TP6.

Fig. 27 shows the fHFB number 1 signal counter preset timing 604 (CTR9PT) with the phase pulled in.
), HI! Signal 139.1'Pi, TP2゜TP3,1
'P5. Each time chart of TP6 is shown together with the count value of counter 64. Counter in Figure 27 (CT
) t9) Counter value of 64 "104" to "'108"
The /HFII number 18 signal pulse "1"'s J cut is the value of 11 in the I signal, and Ha number 139 is drawn into this position 16.

As shown in the figure, the ratios 1' P 1 and 'I' P 2 are pulses located on the image side of the pull-in position ut,
Detecting that the horizontal phase is slightly shifted? + 1' P 4 (rJ-fnv
With a ratio of 1 bite pulse as shown in the figure in s4M tj rus "l" c7), from the retracted position about 60 clocks φ8
This is a noggle that detects a deviation of 11/11M1 degree. TP5. TP6 is for example 1'V channel switching, fII F B16 No. 18 and Hs partner signal 39
This is a pulse that detects that the phase of the THC signal is significantly shifted, and is switched at the timing of the THC signal (22, 447).

In FIG. 22, the comparison pulse i'P1612°1'P
2624. TP2425, TP3623. 1
”P4626.

TP5622, 1'P6627 is phase comparison circuit 457
lls (No. 8 139 and phase comparison and detection are performed. TP, 9623, 1"P4626, TP
5622. TP6627 has latch 6 consisting of 4 bits.
Guided by 29. HIT to the clock of latch 629
1g No. 139 was obtained.

For example, when TP3 is 1", II8 signal 139 is input to the output of Chiro 29 (1-1 in TP3).
! + exists) and PI-81Lj No. 594 is “]
''.Thus, the comparison pulse 'I' P ,3.

TP, 4. TP5. Hs signal 1 in TP6,? 9 arrives, the output of the latch 629 according to the comparison pulse input reaches 1".The output of the latch 629 corresponding to each comparison pulse is converted into a PT-8 signal, 594, PI+8 signal, signal 93, PI+32 signal 591. , PI-32 signal 5
92 and'. The fix of these signals -8, +8
, +32, -32, the latch output that crosses 05 is 1''
21 shows the limit value of the count value of the horizontal synchronization counter 572 in FIG. 21 at the time of .

For example, the P I +32 signal 591 is the horizontal period counter 5
By delaying the preset type 7 of 72 by 32 counts, it becomes a signal for phase pull-in. In FIG. 22, the 5R13Q+ signal 441 from the 21st flip 70 knob 576 is input to the reset terminal of the latch 629, and the latch 629V is cleared every time the horizontal open Jl, II counter 572 is preset.

1-J1 A ratio close to the phase of Nozomi! Rus TPI 612
, TP2624 has T
P3.1'P4゜TP5. It is handled separately from the case of TP6. 'I'PI Pulse 612 is Hs Jogetsu 139 with ANI) Ke9-Toro,? There's no human power involved, ke-
The output of 1.630 is sent to a two-stage counter 632. 7. The logic output of the first bow 18 is led to the reset terminal door of the counter 632. By setting the frizz flop f634 through the key b633 and resetting it with the 5R13Q+ signal 640, PI-2-6 596 is obtained. That is, ) Is 1 No. 139 is the TPI signal 61
If there are 7 and 4 consecutive times in 2, the cape signal pi-2
is obtained. T.P.? For each issue 624, as in 1IT1, from the output of flip-flop 639 I)
I+2AM No. 595 is written as I<j.

In FIG. 21, the output I'I-2 of the phase comparison circuit 457
Haku No. 596, px+szs No. 595, PI-8 signal 59
4, PI+8 signal 593, PI-32 signal 592, pI
+32 signal 591 is horizontal counter control l! 41 is input to the l encoder circuit 459. This encoder circuit 459
If arranged as shown in the figure, when PI + 32 signal + i59 is "1", it will output "0J00000" which indicates the value of +32, and P
I-32 signal, when 92 is 61#, -3 to output 460
It outputs '1100000'' indicating the value of 2. Then, the output 460 of the encoder 459 is guided to the addition unit 570 in the horizontal counter preset value calculation circuit 435.

(Vertical Countdown Circuit) As shown in FIG. 28, the vertical countdown circuit 36 in FIG. 1 includes a vertical reproduction circuit 36-1 and an H8 signal 1.
Vertical reproduction circuit 36
-1, publicly known document: JP-A-55-159673
A basic circuit example is described in detail in "Monthly Publication 1 - Vertical Synchronization Circuit", so please refer to it. The vertical reproduction circuit 36-1 in the embodiment of the present invention may be constructed by partially modifying the above-mentioned known document. Regarding this changed part, the 28th
The counters 651, 13+653 in the figure are two-stage counters corresponding to numbers 10 and 12 in Figure 4 of the two known documents. In this example, l: Qs
61. :The i number 6.50 is used as the input clock of the counter 65), and the Q2 output 652 of the counter 651 is used as the input clock of the counter 65).
53, and a signal of 2.7'H is obtained from the counter 653. Also, reset the counter 65 manually -, 5R
b, reset counter 653 manually 9: I: S R]
3Q +1D ”j + lkoe+qet, 1
(Refer to FIG. 4 of the Jz publication). 1, C3Vli 1-i' instead of C8 in the above known document
126 is not used. fV o o in Figure 28
signal 37 is the vertical drive signal o, fVn
(lLIt Is -'i, 97 is the counter 66
oKm will be removed. Resetting the counter 660 manually
The information signal is 39. IL S flip flop 6
63 is to memorize the 41'ml standing advantageous state of the same period,
) - Is set in 1g No. 662, NANr) )
1"' - is reset by the output of Toro 6. That is, fv
When one or more Hs signals 139 are output within one period of the Dout signal, it is determined that synchronization has been established, and the Q output of the flip-flop 663 becomes '1''. 48111, and r(SD signal 280 is obtained from the output of Nftrenostar 665. In other words, if synchronization is established, H8D = " 1
”.In the event of a fire, the Q output of the flip-flop 663 is R8]8Q +fvDout-Q1 as shown in the figure.
The signal 664 is ORed as shown in 41 and sent to the shift register 665 as a signal 664. The signal 664 is used to bring the flange circuit 19 into the initial state once every two vertical periods of HsD. ) number.

[Brief explanation of drawings]

The drawings are for explaining one embodiment of the present invention. Fig. 1 is a block diagram of the main parts of a digital TV receiver, and Fig. 2 is a diagram for explaining the notation method of the circuit shown in the same embodiment. 3 and 4 are A for explaining the operation of the same embodiment.
DC dynamic range and video signal waveform diagram, Figure 5 is a burst waveform diagram to explain the original use 1 of the PLLN path, Figure 6 is a block diagram of the synchronization detection/timing generation circuit, and Figure 7 is a diagram of the synchronization detection/timing generation circuit. Specific circuit diagrams of the synchronization separation circuit and horizontal phase detection circuit 416, Figures 8 to 101 Recommendation 1G
, Figure 7 is a time chart showing the operation, Figure 11 is the burst flag, circle 7, and flange timing generation 1.
A concrete circuit diagram of Kawaji, FIG. 12 is a time chart showing the movement A'F of FIG. L city +1 r1
11 is a block diagram of the circuit, FIG. 15 is a specific circuit diagram of the PLL control circuit, FIG. 16 is a time chart showing the operation of FIG. 15, FIG. 17 is a block diagram of the horizontal countdown circuit h1, and 181551 is a horizontal cycle Figure 19 is a concrete circuit diagram of the horizontal standard mode detection circuit, Figure 20-1 is a diagram for explaining the operation of Figure 19, Figure 21 is A specific circuit diagram of the horizontal synchronization regeneration circuit, FIG. 22 is a specific circuit diagram of the horizontal phase detection circuit, FIGS. 23 and 24 are time charts showing the operation of FIG. 18,
25 and 26 are time charts showing the operation of FIG. 21, FIG. 27 is a time chart showing the operation of FIG. 22, and FIG. 28 is a circuit diagram of the vertical countdown circuit.
FIG. 29 is a diagram for explaining the operation of FIG. 21. J 1 (DVS) ・-f Jill Rubitio signal,' 8
(J'1lFB)...Horizontal flyback signal, 27.
...Synchronization detection/timing generation circuit, 32...Horizontal countdown circuit1. ? 4 (Inno x)...Horizontal drive signal, 1 s 9 (H!])...Horizontal synchronization detection signal, 144...First horizontal period memory circuit, 15
No...judgment circuit, 152 (DCtO...judgment signal,
46)...Second horizontal periodic memory circuit, 462...
Horizontal phase detection circuit, 462...Horizontal synchronization regeneration circuit.

Claims (4)

[Claims] (1) In a digital television receiver that performs signal processing after digitizing the video signal, a means for detecting a horizontal synchronization signal from the digital video signal, and a plurality of continuous periods of the horizontal synchronization signal obtained by this means. A first horizontal period memory circuit that stores a horizontal period value of minutes as a digital value with a predetermined reference clock period precision, and a determination that determines whether the difference between each period value in this memory circuit is within a predetermined value. a second horizontal period that is controlled by the output of the determination circuit and outputs a horizontal period value obtained by averaging horizontal period values for a plurality of periods from the first horizontal period memory circuit, and a correction value therefor; a memory circuit; a horizontal phase detection circuit that compares and detects the phases of the horizontal synchronization detection signal and the horizontal flyback signal; and an output of the horizontal phase detection circuit and the averaged horizontal signal from the second horizontal period memory circuit. A first horizontal synchronization reproduction signal having an accuracy of the reference clock cycle which is equal to the period value is reproduced, and the first horizontal synchronization reproduction signal is converted to the reference clock according to a correction value from the second horizontal synchronization memory circuit. A digital television receiver characterized in that it further includes a horizontal synchronization reproducing circuit that outputs a second horizontal synchronization reproduction signal corrected with accuracy below the period as a horizontal dry signal. (2) The means for detecting the horizontal synchronization signal includes a means for separating the half-alignment synchronization signal from the digital video signal, and a means for starting counting at the leading edge of each pulse of this composite synchronization signal and counting 1.
means for generating a first horizontal synchronization detection signal every time the surface reaches a predetermined angle; The digital television set 7 receiver 1fJ4m according to claim 1, further comprising means for selecting and outputting the detected signal. (3) The digital television receiver according to claim 1, wherein the reference clock is the same clock as a sampling clock used when digitizing a video signal. (4) The horizontal synchronization regeneration circuit includes a tapped delay circuit which inputs the first horizontal synchronization reproduction signal, and a tap output of this delay circuit into a second horizontal period memory circuit according to the correction value from the second horizontal period memory circuit. 2. The digital television receiver according to claim 1, further comprising a dirt circuit for selecting a horizontal period reproduction signal.