JPS59232432A - Manufacture of hybrid integrated circuit - Google Patents

Manufacture of hybrid integrated circuit

Info

Publication number
JPS59232432A
JPS59232432A JP58107126A JP10712683A JPS59232432A JP S59232432 A JPS59232432 A JP S59232432A JP 58107126 A JP58107126 A JP 58107126A JP 10712683 A JP10712683 A JP 10712683A JP S59232432 A JPS59232432 A JP S59232432A
Authority
JP
Japan
Prior art keywords
layer
integrated circuit
reticulate
hybrid integrated
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58107126A
Other languages
Japanese (ja)
Inventor
Giichi Saito
斉藤　義一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58107126A priority Critical patent/JPS59232432A/en
Publication of JPS59232432A publication Critical patent/JPS59232432A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
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    • H01L2224/05083—Three-layer arrangements
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/0554—External layer
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48455—Details of wedge bonds
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48455—Details of wedge bonds
    • H01L2224/48456—Shape
    • H01L2224/48458—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85203—Thermocompression bonding
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
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    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
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    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
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    • H01L2924/01079—Gold [Au]
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    • H01L2924/01082—Lead [Pb]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding

Abstract

PURPOSE:To increase the bonding strength by a method wherein the surface of a bonding pad is split-formed into the recessed portions and the projected portions which are reticulate in plane view. CONSTITUTION:In a bonding pad of a tantalum thin film hybrid integrated circuit, a Ta2 N layer 2, an Ni-Cr layer 3 and an evaporation Au layer 4 are laminated by priority of the numeral on the upper surface of a substrate 1, an Au layer 15 being formed on the evaporation Au layer 4 by deposition. The configuration of the Au layer 15 is such that a multiplicity of projected parts 15a of rectangular column are disposed, which layer is reticulate in plane view. One end of a lead terminal 16 consisting of an Au-plated thin metal wire is bonded on the Au layer 15 by the thermo compression bonding. The layer 15 is formed in such a manner that a reticulate resin layer is formed by photo lithography and an Au is deposited such as to fill the reticulate portions of the resist layer.

Description

【発明の詳細な説明】 （ａ）発明の技術分野 本発明は混成集積回路の製造方法、　ｌｌ？にボンディ
ング強度を高めるボンティングパッド形成法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for manufacturing a hybrid integrated circuit. This invention relates to a bonding pad formation method for increasing bonding strength.

（ｂ）技術の背景 基板上Ｖζ回路素子を形成及び搭載してなる混成集積回
路において、半導体回路素子や外部接続用リード端子等
の搭載及び搭載回路素子の電極を形成回路素子に接続す
る手段として、熱圧着やワイヤボンディングが一般に行
われており、前記基板上にはそのだめのボンティングパ
ッドが形成されている。(b) Background of the technology In a hybrid integrated circuit formed by forming and mounting Vζ circuit elements on a substrate, as a means for mounting semiconductor circuit elements and external connection lead terminals, and for connecting electrodes of mounted circuit elements to formed circuit elements. , thermocompression bonding and wire bonding are generally performed, and additional bonding pads are formed on the substrate.

（ｃ）　　従来技術と問題点 第１図は従来方法で形成されたタンタル薄膜混成集積回
路のボンティングパッドに外部リード端子を接続した部
分の側面図である。(c) Prior Art and Problems FIG. 1 is a side view of a portion where external lead terminals are connected to bonding pads of a tantalum thin film hybrid integrated circuit formed by a conventional method.

第１図において、１はアルミナ基板、２は基板１の表面
に被着したＴａｘＮ層、３はＴａｚＮ層２の上にパター
ン形成しだＮｉ−０ｒ層、４はＮｉ−Ｃｒ層３の上に蒸
着形成したＡｕ層（パッド基層）５はＡｌ１層４の上に
めっき形成しブｊＡｕ層であり。In FIG. 1, 1 is an alumina substrate, 2 is a TaxN layer deposited on the surface of the substrate 1, 3 is a Ni-0r layer patterned on the TazN layer 2, and 4 is a Ni-Cr layer 3 The vapor-deposited Au layer (pad base layer) 5 is formed by plating on the Al1 layer 4.

Ａｕめっきした金属細線（又はＡｕ細線）ＶＣてなるリ
ード端子６の一端がＡｕ層５の上に熱圧着法でボンディ
ングされている。One end of a lead terminal 6 made of an Au-plated thin metal wire (or thin Au wire) VC is bonded onto the Au layer 5 by thermocompression bonding.

このように構成されたパッドのＡｕ層５は、細線６との
Ａｌｌ相互拡散を確保するため、一般に３　ｔｒ　ｍ〜
５　／１ｍの均一厚さに被着している。従って。The Au layer 5 of the pad configured in this manner generally has a thickness of 3 t m to
It is coated to a uniform thickness of 5/1 m. Therefore.

多数のボンディングパラｉ・有する集積回路を多数個製
造するとき、高価であり有限の天然資源である金（八Ｕ
）の消費量は極めて大量になるとともに、ボンディング
強度を高める技術的努力が限界に達しており、それらの
新規対策が望まれていた・（ｄ、）　　発明の目的 本発明の目的は、上記問題点に鑑みてＡｌｌの消費量を
低減させ、同時にボンティング強度を高めることである
６ （ｅｌ　　発明の溝成 上記目的は、ボンディングパラｔ′のクシ、くとも表面
を平面視網目状の凹凸に分割形成することを特徴とした
混成集積回路の製造方法により達成される。When manufacturing a large number of integrated circuits with a large number of bonding parameters, it is necessary to use gold (8U), which is an expensive and limited natural resource.
) consumption has become extremely large, and technical efforts to increase bonding strength have reached their limits, and new countermeasures have been desired. (d,) Purpose of the Invention The purpose of the present invention is to solve the above problems. In view of the above, the purpose of the invention is to reduce the consumption of All and at the same time increase the bonding strength. This is achieved by a method of manufacturing a hybrid integrated circuit characterized by forming it in parts.

（ｆ＋　　発明の実施例　　・ 以下５図面を用いて本発明方法の実施例を説明する。(f+　Embodiment of the invention　・ Examples of the method of the present invention will be described below using the five drawings.

第２図は本発明方法の一実施例に係わりタンタル薄膜混
成集積回路のボンディングパソド（Ｃ外部リード端子を
接続した部分の側面図、第３図は外部リード端子を接続
してない前記）Ｚ・ノドの平面図第４図は前記パッドの
ΔＵめつき層を被着する実施例を説明するだめの側面図
でるる。FIG. 2 shows a bonding pad for a tantalum thin film hybrid integrated circuit according to an embodiment of the method of the present invention (C is a side view of the part to which external lead terminals are connected, and FIG. 3 is a side view of the part to which the external lead terminals are not connected) Z・Plan view of the throat FIG. 4 is a side view for explaining an embodiment in which the ΔU plating layer of the pad is applied.

第１図と共通可能な部分に同一符号（１，２，３，４）
を用いた第２図において、基板１０所定部上面に積層さ
れたＴａｌＮ層２とｔｙｔ−ｃｒＪ１３と蒸着ＡｕＪｆ
ｉ　４の上にめっき形成されたＡｌ１層１５は第３図に
示す如く、角柱形状の突起１５ａ　が多数個（図は３６
個）配列された網目状であり、その上にＡｌｌめっきし
た金属細線（又（、」、Ａｕ細線）Ｋてなるリード端子
１６の一端が熱圧着法でボンディングきれている。ただ
し、リード端子１６の凹部１６ａｊ：ｊボンテイングウ
エツンで押しつぶされてできたものでらり１凹部１６８
の近傍の下方に位置する突起１５ａは、リード端子１６
の表面となじむように塑性変形し、リード端子１６にボ
ンディングされている。従って、第１図のリード端子６
と第２図のリード端子Ｊ６とを同じ条件でボンディング
したとき、リード端子６かＡｕ層５に接続される面積よ
りも、リード端子１６とＡｕｌ鱗工５とが接続される面
積の方が大きくなる。Same symbols (1, 2, 3, 4) for parts that can be in common with Figure 1
In FIG. 2, a TalN layer 2 laminated on the upper surface of a predetermined portion of a substrate 10, a tyt-crJ 13, and a deposited AuJf
As shown in FIG. 3, the Al1 layer 15 formed by plating on i4 has a large number of prismatic protrusions 15a (36 in the figure).
One end of the lead terminal 16, which is made of thin metal wires (also thin Au wires) plated with All-plated metal wires, is bonded by thermocompression bonding. However, the lead terminals 16 Concave part 16aj:j It is made by being crushed by bonding wetness.Recess 168
The protrusion 15a located below near the lead terminal 16
It is plastically deformed to fit the surface of the lead terminal 16 and is bonded to the lead terminal 16. Therefore, the lead terminal 6 in FIG.
and lead terminal J6 in FIG. 2 are bonded under the same conditions, the area where lead terminal 16 and Au scale 5 are connected is larger than the area where lead terminal 6 is connected to Au layer 5. Become.

第３図において、蒸着Ａｕ層４の上ｙｃめつき升成され
突起１５ａの断面寸法はＷ　Ｘ　Ｗとし、そオらの列方
向及び行方向間隔は１，７・である。セしてνと、υは
１例えばリード端子】６の直径（又は幅）が２００　ｔ
ノｍのときそれぞれ５０　ａ　ｍ　ＶＣするが如く五定
される 第４図において、基板１及び蒸着Ａｕ層４の−・に被着
；ｇ７’Ｌ／ｊし／ストＩｆ＜１７．１．７　ａは、複
数個ＱＡｌｌ突起１５ＩＬ（Ａｕｌψ１１５）　　をめ
っき形成さ→るためのものであり、それらは各突起１５
ａにヌ向する網目状パターンが設けられたマスクを用し
たフォトリソグラクイ技術により形成されてい２そして
突起１５ａは、レジスト層１７と１７ａＱ間隙を埋めて
、Ａｌ１１け４の上（（めっき被着され２なか２、ト記
実施例では基板−Ｆのパッドに外部引続用リード端子を
ごム圧着法で搭載しメこ一例であ２が、他の回路素子の
搭載例えは半導体素子を・フコ−ツボ／ティングすると
き、及び超音波法などイ１の方法での搭載等にも本発明
方法が適用されることをイτ１記する。In FIG. 3, the cross-sectional dimensions of the protrusions 15a formed on the vapor-deposited Au layer 4 are W x W, and the spacing between them in the column and row directions is 1.7. Set ν and υ are 1. For example, the diameter (or width) of the lead terminal] 6 is 200 t
In FIG. 4, when 50 am VC is applied to the substrate 1 and the vapor-deposited Au layer 4; a is for forming a plurality of QAll protrusions 15IL (Aulψ115) by plating, and they are formed on each protrusion 15.
The protrusions 15a are formed by photolithography using a mask with a mesh pattern facing toward a, filling the gap between the resist layers 17 and 17aQ, 2, 2 and 2. In the above embodiment, external connection lead terminals are mounted on the pads of the board-F by the rubber crimping method. This is just one example, but other circuit elements can be mounted, such as semiconductor elements - It is noted in τ1 that the method of the present invention is also applicable to acupoint/ting, and mounting using the method of 1, such as the ultrasonic method.

多　　（ｇ）発明の効果 ｔ　　　　以上説明した如く本発明によれし１１．カミ
ンテインｌ　　　グバツＦが相手の面になじみ易く、そ
のことによ−ってボンティング面積が拡がる等に」：す
、γＦンティング強度は従来のものよ！７１０〜２０係
強くなったのみたらず、被着するＡｕの月が減少するた
ヒ　　　め混成集積回路のコス（・が低減し、さらに網
目状、　　　のバク−／を設けたマスクを用いて本発明
方法にセ　　　係わるレジスト層を形成することにより
、工程をづ　　　増すことなく本発明が製品に適用され
る効イは大きい・・ ５゜　４、図面の簡単な説明 、　　　　第１図は従来方法で形成されたタンクルジ薄
１１Ｊ（混成集積回路のパッドに外部リード端子をポン
ティ良　　　ングしだ部分の側面図、第２図は本発明方
法の一実施例に係わりタンタル薄膜混成集積回路のツク
′ノドに外部リード端子をボンティングＬ７だ部分の側
は　　　面図、第３図は第２図に示しだツクノドの前記
７にンデインク前におりる平面図、第４図は８￥２図及
び第３図に示（〜だパッドのＡｌ１めつ＠層を被着する
実施例を説明するだめの’Ｉｔ”ＩＩ面図である、図に
ふいて、１は基板、２１＜ｌ、ＴａｘＮ層、３はＮ　１
−Ｃｒ層、４ｉ＋：蒸着Ａｕｌ済、５．１５に！、めっ
きＡｌ１層、１５ｅ、ＩｔよＡｕ層Ｊ５を構成するＡｕ
突起、１７゜１７８（弓しジストパターンヲ示ス・ 代理人　弁理士　松岡宏四西−「Ｉ？、１．ｊ（＋、−
，・′ｌ１１(g) Effects of the invention t As explained above, the present invention has advantages 11. The γF bonding strength is the same as that of the conventional one! 710-20, the cost of the hybrid integrated circuit is reduced because the amount of Au deposited is reduced, and the cost of the hybrid integrated circuit is also reduced. By forming a resist layer according to the inventive method, the present invention can be applied to products without increasing the number of steps. Figure 2 is a side view of the part where the external lead terminals are connected to the pads of the hybrid integrated circuit. The side of the part where the external lead terminal is bonded L7 is a top view, Figure 3 is a plan view of the connection shown in Figure 2, and Figure 4 is a top view of the connector shown in Figure 2. This is a 'It'II plane view for explaining the embodiment of depositing the Al1 layer on the pad shown in (-). In the figure, 1 is the substrate, 21<l, the TaxN layer, 3 is the N 1
-Cr layer, 4i+: Evaporated Au finished, 5.15! , plated Al1 layer, 15e, It and Au constituting Au layer J5
Protrusion, 17° 178 (showing the arched jist pattern, agent and patent attorney Hiroshi Matsuoka - "I?, 1.j (+, -
,・'l11

Claims (2)

【特許請求の範囲】[Claims] （１）ボンディングバットの少なくとも表面を平面視網
目状の凹凸に分割形成することを特徴とした混成集積回
路の製造方法。(1) A method for manufacturing a hybrid integrated circuit, characterized in that at least the surface of a bonding bat is divided into concavities and convexities that are mesh-like in plan view. （２）前記網目状にパターン形成されたマスクを用いて
パッド基層の上に網状のレジストハターンを形成し、該
レンストパターンの網目間隙を埋めるめっき層を被着す
ることを４？徴とした前記特許請求の範囲第１項に記載
した混成集積回路の製造方法・(2) Forming a net-like resist pattern on the pad base layer using the mask patterned into a mesh pattern, and depositing a plating layer that fills the gaps between the meshes of the resist pattern. A method for manufacturing a hybrid integrated circuit according to claim 1, which is characterized in that
JP58107126A 1983-06-15 1983-06-15 Manufacture of hybrid integrated circuit Pending JPS59232432A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58107126A JPS59232432A (en) 1983-06-15 1983-06-15 Manufacture of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58107126A JPS59232432A (en) 1983-06-15 1983-06-15 Manufacture of hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS59232432A true JPS59232432A (en) 1984-12-27

Family

ID=14451150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58107126A Pending JPS59232432A (en) 1983-06-15 1983-06-15 Manufacture of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS59232432A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6087756A (en) * 1997-08-11 2000-07-11 Murata Manufacturing Co., Ltd. Surface acoustic wave
US6414415B1 (en) 1999-02-18 2002-07-02 Murata Manufacturing Co., Ltd. Surface acoustic wave device and method for manufacturing the same
US7102461B2 (en) * 2003-07-28 2006-09-05 Tdk Corporation Surface acoustic wave element, surface acoustic wave device, surface acoustic wave duplexer, and method of manufacturing surface acoustic wave element

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6087756A (en) * 1997-08-11 2000-07-11 Murata Manufacturing Co., Ltd. Surface acoustic wave
US6414415B1 (en) 1999-02-18 2002-07-02 Murata Manufacturing Co., Ltd. Surface acoustic wave device and method for manufacturing the same
US7102461B2 (en) * 2003-07-28 2006-09-05 Tdk Corporation Surface acoustic wave element, surface acoustic wave device, surface acoustic wave duplexer, and method of manufacturing surface acoustic wave element

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