JPS59231666A - Peripheral element of microprocessor - Google Patents

Abstract

PURPOSE:To allow a clock signal which is supplied from a CPU or externally to place a peripheral element in an operation stop state optionally, and reduce the power consumption of a system by stopping an internal clock. CONSTITUTION:An instruction decoding part 2 decodes an instruction on a data bus DB while a signal M1' is ''0'' to generate a prescribed output signal, which is supplied to respective parts in the peripheral element. When the signal on the data bus DB is an operation stop instruction, an output signal D is set to ''1'' to set an operation stop and inputted to the reset terminal of an FF 3 to enter an operation stop mode, and an internal control signal ST is set to ''0''. An AND gate 4, even when supplied with a clock signal phi from, for example, the CPU, does not generate any internal clock signal CK and the peripheral element 1 stops operating. Further, when an instruction read signal M1' is supplied to the set terminal of the FF 3, the FF 3 is set and the operation stop is reset.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to peripheral elements in a microprocessor system, and particularly to peripheral elements whose operation can be stopped.

<Prior art> Figure 1 shows an example of the configuration of a microprocessor system that has been widely used in the past.The central microprocessor (hereinafter simply referred to as CPU) has memory and peripheral elements connected to data bus DB, address bus AB, and and control bus CB
They are connected by three types of buses:

The microprocessor system (i; tNch-MOS) that has traditionally been used in industrial applications was comprised of a microprocessor system (tNch-MOS), but in recent years, the number of battery-powered devices and various portable computer-related devices has increased, and the structure and characteristics of these devices have changed. Therefore, it is desired to reduce power consumption, and attempts have been made to configure the circuit with CMO5) transistors.

CMO5) The circuit composed of transistors is Nch-MO
S) It has the advantage of being able to significantly reduce power consumption compared to the case consisting of transistors, and in addition,
Transistor circuits have different characteristics during operation,
Therefore, in order to further enhance the effect of low power consumption, it is desirable to appropriately control the operating state to increase the period of non-operating state and to suppress unnecessary power consumption. However, in conventional microprocessor systems, even CMO8
Even if a reduction in power consumption was achieved through the use of a conventional technology, the peripheral elements remained active even during non-operation, and it was difficult to say that sufficient reduction in power consumption had been achieved.

<Object of the Invention> The present invention provides a microprocessor system in which a CPU and peripheral elements are combined, and in particular, a peripheral element that can arbitrarily stop operating the peripheral elements to reduce power consumption as a microprocessor system. .

<Example> Peripheral elements that are connected to the CPU via various buses and become part of the microprocessor system include PIO (Pa
rallel Inputoutput Contr
oller).

CTC (Counter Timer CrrcrJ
) + SI O (Serial Input
output controller) and
DMA (Direct Memory Access
In order to control the operation of various terminal devices such as a CRT and a floppy disk device using a CPU, there is a control circuit that connects the two.

FIG. 2 shows a peripheral element 1 illustrating an embodiment for executing the operation stop according to the present invention in the above-mentioned peripheral element.
FIG. Peripheral element 1 in this embodiment
Similarly to the CPU, the peripheral element 1 is brought into an operable state by using the internal clock instead of the CMO No. 5 φ key. Therefore, by stopping the internal clock φ applied to the peripheral element 1, the peripheral element 1 can be brought into a stopped state.

In FIG. 2, since the instruction read from memory to CPt1 is placed on the data bus, the data bus DB
It is also input to the peripheral element 1 which shares the same. The peripheral element 1 is provided with an instruction decoding section 2 for inputting information carried on the data bus DB and decoding the contents.The reading timing is controlled by the instruction read signal M1 given from the CPU, and the decoding is performed. executed. In addition, the command read signal - "
In the state of "0", "go" indicates that the cycle currently being executed is an instruction read cycle.

The instruction decoder 2 decodes the instruction on the data bus DB when the instruction read signal M1 is 10'', forms a predetermined output signal, and supplies signals corresponding to the input instruction to each part in the peripheral elements. However, especially when the signal on the data bus DB is an operation stop command, the output signal is set to "1" in order to detect it and set the operation stop. The output signal RI is applied to the reset terminal of the flip-flop 3 provided to hold the operation stop mode, and in the operation stop mode, the internal control signal ST is set to "0" as the output of the flip-flop 3. do.

The internal control signal ST is applied to one input terminal of the AND gate 4, and controls whether or not to pass the clock signal φ applied from the CPU to the other input terminal. The output of the AND gate 4 is supplied to the circuit inside the peripheral element 1 as an internal clock signal CK. Therefore, when the internal control signal ST is 10'' and the operation stop mode is set, even if the clock signal φ is applied from the CPU to the peripheral element 1, the internal clock signal CK is not generated and the peripheral element 1 As a result, the operation is stopped.

That is, the command on the data bus DB is decoded by the peripheral element itself, and the operation is stopped.

By the above-described structure and operation, the operation is stopped, the reset state of the flip-flop 3 is changed to the nut state, the stoppage of the operation is canceled, and the clock signal φ is allowed to pass through the AND gate 4, and the peripheral elements are The internal clock signal CK is supplied to the internal circuit to maintain the operating state. That is, the operation stoppage is canceled in response to the operation stoppage.

In the above embodiment, the mode setting is performed by disabling the operation stop command in the peripheral element itself. However, a dedicated terminal for inputting the operation stop command to the peripheral element is provided, and the input signal from the operation stop command terminal causes the mode to be set. It is also possible to control the operation of the lip-flop 3. Also, add a register for an operation stop command in the peripheral element, set the operation stop command to the register from the CPU, and control conduction/cutoff of the AND gate 4 using the output of the register. You can also do it.

The operation stop mode can be canceled using the command read signal Mgo in any of the peripheral elements provided with the operation stop command terminal and the peripheral elements using the register. Cancellation can be performed using a chip enable signal or a write signal other than the instruction read signal Mgo.

Further, in the case of a peripheral element provided with an operation stop command terminal, the operation stop can be canceled by canceling the operation stop mode set in the operation stop mode control register.

Note that the operation stop command given to the data bus DB may be a stop command for only the peripheral element 1;
The stop command may also include the PU or other peripheral elements.

Here, both the CPU and the peripheral elements are composed of CMOS transistors, but there is a particularly great advantage in stopping the internal clock and stopping the operation of the peripheral elements composed of such 0M08 circuits. The current consumption can be significantly reduced compared to the case where the current state is maintained. That is, the point at which current consumption occurs in the 0M08 circuit is when the signal is inverted, and therefore, by stopping the operation based on the clock signal that is most frequently inverted, current consumption can be effectively suppressed.

Effects> As described above, according to the present invention, by adding a function to set an operation stop command mode to a CPU-coupled peripheral element and controlling the execution or stop of the operation, normal command read cycles and terminals can be controlled. By using this method, peripheral elements can be operated efficiently, and microprocessor peripheral elements with excellent economic efficiency can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a microprocessor system, and FIG. 2 is a block diagram of an embodiment according to the present invention. 1: Peripheral element, 2: Instruction decoder, 3 Near lip 70
Tsubu, 4: Gate, DB: Data bus, Ml:
Command read signal, sT: internal control signal. Agent Patent Attorney Aihiko Fuku (and 2 others) No. 1 (3) No. 2 Aihiko No. 1

Claims (1)

[Claims] 1. In a peripheral element coupled to a microprocessor (CPU), means for internally setting an operation stop mode based on an input signal, and a signal for continuing operation in the operation stop mode. A microprocessor peripheral element comprising: a gate circuit for blocking the supply of the microprocessor. 2. Claim 1, wherein the microprocessor and peripheral elements are composed of a CMO8.
Microprocessor peripheral elements described in Section 1. 3. The microprocessor peripheral element according to claim 1 or 2, wherein the signal for instructing the continuation of operation is a clock signal.