JPS59228476A - Brightness controller for large-screen video device - Google Patents

Abstract

PURPOSE:To control the brightness of light emitting elements of a matrix type display panel used for a large-screen video device by using a video memory, brightness memory, counter, comparator, etc. CONSTITUTION:A separating circuit 1 separates a TV video signal VS into red, green, and blue signals R, G, and B, a horizontal synchronizing signal HSS, a blanking signal BS, and a vertical synchronizing signal VSS. An A/D conversion part 2 converts the separated signals. A correction part 3 makes logarithmic corrections matching with visual sensation by making digital signals of R, G, and B linear in pulse width and brightness. A buffer part 4 is actuated with a buffering signal so as to reduce the access speed of the video memory 5 as the next stage. A latch part 6 latches the output of the video memory 5 with a signal from a decoder 10. An addition part 7 corrects the brightness of the light emitting elements on the basis of the signal of the memory 5 and the latch address signal of the brightness memory from the counter part 8.

Description

TECHNICAL FIELD The present invention relates to a brightness control device for a large screen video device. The device according to the present invention is used, for example, in a large screen video device for displaying records, etc. in stadiums, baseball stadiums, etc.

BACKGROUND OF THE INVENTION Conventionally, various types of large display devices have been proposed for use in large stadiums and the like. In other words, there are those that use a light bulb matrix method in which a large number of incandescent light bulbs are arranged, and those that use a large number of L
ED, fluorescent tubes, etc.) IJ sock display panels, etc. The former has the basic problems of making it easy to make a large screen, but it is difficult to obtain high brightness and high quality, and it also consumes a lot of power.The latter has the basic problems that it is difficult to obtain high brightness, slow response speed, and It has problems such as low efficiency.

Purpose of the Invention The purpose of the present invention is to time-divide the brightness of light emitting elements of a matrix type display panel used in a large screen video device using an image memory, a brightness memory, a counter, a comparator, etc.
It is an object of the present invention to provide a brightness control device with low power consumption, which can speed up the response speed of a light emitting element and freely control any display location to any brightness.

SUMMARY OF THE INVENTION According to the present invention, an object of the present invention is to provide a brightness control device for a large screen video device, which brightness control device converts a television video signal into red, green, and blue color signals and a horizontal synchronization signal. A separation circuit separates the blanking signal into a synchronizing signal and sends it out, and an image memory at the subsequent stage based on the reference frequency from the crystal oscillator, the horizontal synchronizing signal, the blanking signal, and the vertical synchronizing signal.

a counter unit that sends an address signal and a timing signal to the luminance memory to specify an address; a correction unit that performs logarithmic correction of the signal after analog-to-digital conversion of each of the color signals to match the visual sense; A buffer section converts bits in order to adjust the access speed after the image memory based on the buffering signal sent from the counter section; an image memory whose address is specified by the direction address signal; and a latch section which latches the image output from the image memory based on the latch address signal from the counter section in order to provide a time lag between the image output from the image memory and the luminance memory at the subsequent stage. , an addition section that corrects luminance variations of the light emitting elements at the subsequent stage based on the luminance memory signal from the latch section and the latch address signal from the counter section.

A brightness memory that stores the brightness memory signal according to predetermined brightness gradation data based on a brightness memory address signal and horizontal and vertical address signals sent from the counter section, and a nuclear vertical address signal and its count signal. a brightness memory unit having a brightness counter that counts the number of brightness adjustments based on the brightness value, and a comparator that compares the output of the brightness counter with the output of the brightness memory and outputs a lighting instruction for the light emitting element; and the brightness memory unit. This is achieved by providing a brightness control device for a large screen video device, comprising a light emitting element that is turned on after the output from the device is converted into a predetermined timing and drive level by a latch circuit and a driver circuit.

Embodiment FIG. 1 is a block diagram showing a brightness control device for a large screen video device according to the present invention. At the first station, 1 connects the television video signal VS to the red signal R9, the green signal G, the blue signal B and the horizontal synchronization signal Hi9S.

This is a separation circuit that separates a blanking signal BS and a vertical synchronization signal vSS. 2 is a separated le.

An analog/digital (A/I) converter that converts G and B into digital signals, such as an A/D converter 21A/D converter 2 provided corresponding to each of JG and B.
2 and A/I) converter 23. 3 is R
A correction circuit 31 is provided corresponding to each of R2O and B. .32 and 33. 4 is a buffer section activated by a buffering signal in order to slow down the access speed of the image memory 5 at the next stage; It is composed of buffer circuits 4R, 4G, and 4B provided in accordance with the above.5
is an image memo IJ (V-RAM) that stores RlG and B corrected by the correction unit 3, and the dots of RlG and B that constitute the large TV screen shown in Fig. 8 are shown in Fig. 9(a). They are arranged as shown and stored as luminance gradation data as shown in FIG. 9(b). In this case, each dot of JG and B is composed of 6 bits and has 64 gradations as a brightness level. Also, the memory address is the 9th
As shown in Figure (a), one raster of 320 dots is divided into 8-pixel units, and 8 dots in each column of JIR, G, and B are designated as one address. 6 is a latch unit that latches the image output from the image memory with the signal from the decoder 91;
Latch circuit 6 provided corresponding to each of 2O and B
Consists of R, 6G and 6B. 7 is the latch signal of the image memory 5 and the brightness memory R from the counter section 8;
The R2O adder is for correcting the luminance variation of the light emitting elements based on the G and B latch address signals.
Addition circuit 71.7 provided corresponding to each of
2 and 73. Reference numeral 8 denotes a counter section, which includes a horizontal address counter 81 that sends out various timing signals based on a reference frequency from a crystal oscillator C0, a horizontal synchronizing signal Hss from a separation circuit 1, and a blanking signal; The circuit 1 is composed of a vertical address counter 82 which performs address designation in the vertical direction based on the blanking signal BS from the circuit 1 and the vertical synchronization signal SS. The horizontal address counter 81 and vertical address counter 82 are shown in more detail in FIG. Decoders 9 and 10 send an address signal from the counter section 8 to a subsequent gate circuit. 11 is a luminance memory section, each of which is connected to a decoder 111.11 as shown in detail in FIG. Brightness memory 113. Brightness counter 11
The luminance memory 113 is composed of a 4° gate circuit 112 and a comparator 115, and has a memory form similar to the image memory shown in FIG. In this case, the maximum brightness is considered to be the time (vertical synchronization period) for translating 256 rasters (actually 262.5 rasks, but for convenience, the rest is a dummy), and this is divided into 64 equal parts, or 4 rasters. The time it takes to scan these four rusks is one unit of brightness level. 12 is a latch portion shown in FIG. 6(b).
, R and G corresponding to each of the brightness memory sections 11 as shown in (c).

An 8-bit latch circuit (0
0 to 339). Reference numeral 13 is a driver section for driving the light emitting element 14.
As shown in c), R and G correspond to the number of light emitting elements 14.
, B are provided from OO to 339.

A decoder 15 sends ratio, G, and B signals to the latch circuit at the subsequent stage based on various signals from the counter.

FIG. 2 is a block diagram illustrating the buffer unit 4 and decoder 9 shown in FIG. 1 in more detail.

In FIG. 2, the buffer section 4 includes a 6-bit latch circuit 41i provided for each of the o and B signals sent out from the correction section 3, 41G, 41B, 42R, 42
G, 42B, a dart circuit 43 for converting in units of 8 pits (, 43G, 43B), and a switch 44 for performing brightness correction based on reference input from the microcomputer MC. )t, G, and B signals sequentially latch the 6-bit luminance information of )(,, (), and H in latches O to 7 for each of the 6-bit latch circuits 41R, 41G, and 41B.) memory 5
In order to slow down the access speed after the output of the image memory 5, it is converted into units of 8 dots (6 bits/dot x 8 bits - 48 bits for f), but in this case, 6 bit latch times jJ411 (.

The timing for sending bits from each of latches 0 to 7 of 41G and 411 (to latches O' to 7' in the next stage) is synchronized with the timing of latch 0 in the previous stage by the signal O from the output phrase decoder 91 of the decoder 9. The latch 0' of each of the 6-bit latch circuits 4214, 42(), and 42H is simultaneously controlled by darts 43L, 43G, and 43B.
The outputs of 7' to 7' are time-divided in units of 6it, u, and tt by the time-division output gate code from the decoder 92. In addition, the enable timing of 42G and 42B is also determined by the latch address signal (
O~7) Using 04.5.6, latch address (0~
In the case of 3), the image memory 5 is placed in a read state, and 4 to 7 are placed in a write state. Further, a switch 44 is provided to correct the brightness of the light emitting element group 14 using a reference input from a microcomputer (not shown) MC. The image memory input signal 81 is outputted from the switch 44 to the image memory 5 as a 48-bit normal signal.

FIG. 3 is a block diagram illustrating in more detail the horizontal address counter 81 and vertical address counter 82 of the counter section 8 shown in FIG. 1. Horizontal address counter 8
1, the output of the crystal oscillator CRO is passed through the frequency dividing circuit 811.
The frequency is divided by , and its output is input to the pinary counter 812 together with the control clock CCL. The pinary counter 812 uses a counter whose clock advances by 640 steps. In this case, 640 steps are obtained by multiplying 2 steps for reading/writing the 8-pixel 9-image memory as the buffer address and 40 addresses as the 8-pixel rate address of 1 raster. . Therefore, since the time required for one rask is 63.5 μs, the frequency of the control clock CCL is 64 μs.
The result is 99 ns divided by 0 steps. The output of the pinary counter 812 is input to a memory (l(, OM) 813, and the memory 813 outputs various signals as counter outputs, as shown in the timing chart of FIG. 7. That is, the horizontal address counter 81 From there is a control clock CCL and a buffering signal ■.

Latch address (octal, 1.2, 4) signal ■, horizontal address (40, 1, 2.4, 8, 16.32) signal ■1 image memory write enable signal ■, brightness memory address signal ( Ao, AI)■, #[memory write timing signal ■, and reset signal ■. Further, the write address signal (4) is also used as an R/W timing signal for the image memory. The reset signal is used to distinguish between necessary memory addresses and unnecessary memory addresses, and when the horizontal synchronization signal H88 and the blanking signal BS match in the all AND circuit 814 and in the rising edge detection circuit 815, the AND condition is determined. The ROM 813 is controlled by the latch circuit 816 according to the signal that detects the rising edge.

All necessary addresses are accessed within this reset cycle, so if there are more addresses than necessary, the memory IJ (RO
A latch circuit 816 is provided to inhibit the output of M) 813. On the other hand, the vertical address counter 82 detects a coincidence between the horizontal synchronizing signal H8B and the superposition synchronizing signal vSS and the blanking signal BS based on an AND circuit 824 and a reset signal obtained from a rising edge detection circuit 825. , the pinary counter 821 outputs a pulse 2° 2Z 22.23 indicating the vertical raster number in 256 base, and the pinary counter 822 outputs 2't 2'l 2
'l 27 parables are each output to dart 823. As shown in the timing chart in FIG. 7, the vertical address signals (1,2,4,8,16,32,64°12
8) Output ■. The actual vertical synchronization period is 262
．． 5 Since it is a raster, if it exceeds 256 rasks, use 2
56 carry C2 is latched by the latch circuit 826 to prohibit counter output. Also, carry C1 is pulse 2
When all of .degree. to 23 are "1", they are all returned to "0" at the next clock, which is used to carry up the counter.

FIG. 4 shows the image memory 5 and latch section 6 shown in FIG.
FIG. 2 is a block diagram illustrating in more detail. Fourth
In the figure, an image memory input signal Sl is inputted to the image memory 5 as a motherboard signal from the buffer section 4 to the pit 48, and furthermore, a horizontal address signal ■ and a vertical address signal ■ of the latch address signal are inputted from the counter section 8. and write enable signal ■ are input. In actual use, the image memory 5 used 3×40×256=30720 addresses. The outputs of the both-edge memory 5 are input to the 48-bit latches 61R, 61G, and 61B of the latch circuit 6, respectively, and at the same time, the outputs of the decoder 9 are input to the 48-bit latches 61R, 61G, and 61B of the latch circuit 6.
R, G, Bi indicating arm 0.1.2 are each 61R from
, 61G, and 61B. Latch 61) L, 61
G, 61B are a one-picture image memory 5 and a luminance memory 1, which will be described later.
This is provided to take a time lag with 1, and to read out quickly from the image memory and send it to the brightness memory at an appropriate speed. The outputs from 61R, 61G, and 61B are sent to 1(,,,
(), 48-bit gate 62R, 62 with B signal
G, 63B, and from the 48-bit gate, a signal of 6 bits x 8 dots = 48 bits becomes the luminance memory signal S2.
It is output to the luminance memory 11 at the subsequent stage as .

FIG. 5 is a block diagram illustrating the luminance memory 11 shown in FIG. 1 in more detail. In FIG. 5, the luminance memory 11 includes a decoder 111a, a decoder 1llb with an output y-t, and 48-bit gates 112.6 of 154 blocks.
It is composed of 4 blocks of luminance memory 113, 64 blocks of luminance counter 114, and 64 sets of comparators 115. The decoder 111a generates a status signal 1 ('wl-63) that controls reading/writing of the luminance memory 113 and a signal (C to 1F) that resets the luminance counter 114.The me memory 113 and luminance counter specified by the status signal 114 are in the state of write (W) and count value 1 preset.Therefore, only one of 0 to 63 is always in the state of write and preset, and the remaining (63 locations) are in the state of read (LL) and count enable. Decoder 111b with output 9
is the write enable (timing) of the brightness memory 113
It is used to generate signals, and sends signals WE1-WE63 to each of the brightness memories.

Each of the 48-bit gates 112 uses a bidirectional data bus (W-, tt) for the 24-degree memory, so when the 'y4If memory is all written, the path is enabled and data is written to the luminance memory. It's crowded. Brightness counter 11
Each of 4 has 64 counts, but the count up is partially irregular like 1.1, 2, 3, 4.5...63, and the output is sent to the comparator 115 in the subsequent stage. each P
will be sent to. Each of the comparators 115 inputs the bus data and the brightness memory register to its Q, and compares the value of the intensity counter input to P to generate an on/off signal for the light emitting element. , outputs a lighting signal (00 to 638) to the latch circuit 12 at the subsequent stage when Q≧P.

6(a) to (C) show the decoder 15° latch section 12, driver section 13, and light emitting element group 14 shown in FIG.
FIG. 2 is a block diagram illustrating in more detail. 6th
In Figure (a), each decoder O to 39 of the decoder 15
are provided to generate timing signals for latching into the 8-bit latch constituting the latch section 12, and
The R, G, and B decoders O to 39 for each row are at address Ao of the brightness memory.

Al, and vertical addresses 1 and 2 are input.

Further, the timing of each latch is synchronized with the luminance memory write timing signal (2). This signal is used as a latch clock pulse. 8 bit latch (00~339
) simply latch the on/off signal of the light emitting element 14, and each of the subsequent driver circuits 13
4 into drivable signals. For the horizontal address delay, comparators (0 to 39) are installed as shown in Figure 6 (al), and the horizontal address signal ■
This can be done by finding the conditions under which the set values of the switches (8WQ to 39) are the same. Comparator (O~
The reason for providing the switch (SWO-8W39) is to treat the input signal as a bus signal and enable printed wiring on the back panel.In actual use, the comparator,
Decoder, lunch.

By mounting the driver section on a single printed board, the input signal becomes a path and printed wiring is possible.

Effects of the Invention By the brightness control device t for a large screen video device according to the present invention, the response speed of the light emitting element is increased, and any display 11r+1 can be freely controlled to any brightness, and consumption and sleep power are also reduced. I can do it.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an =i control device as an embodiment of the present invention, and FIG. 2 is a block diagram illustrating in more detail the buffer section and rgouda 9 meeting shown in FIG. 1. FIG. 3 is a block diagram illustrating the counter section shown in FIG. 1 in more detail, and FIG. 4 is a block diagram illustrating the latch section 6 shown in FIG. 1 in more detail. 5 is a block diagram explaining the luminance memory shown in FIG. 1 in more detail, FIG. 6(a) is a block diagram explaining the decoder 15 shown in FIG. 1 in more detail, FIG. 6(b), ( c) is the latch part 12 shown in FIG.
．． A block diagram explaining the driver 131 and the light emitting element 14 in more detail, FIG. 7 is a timing chart of signals sent from the counter section shown in FIG. 11, FIG. 8 is a diagram showing the dot arrangement of a large screen, and FIG.
) is a diagram showing the memory configuration of the image memory and brightness memory shown in FIG. 1, and FIG. 9(b) is a diagram showing brightness gradation data. Explanation of symbols 1... Separation circuit, 2... Analog-digital converter, 3... Correction section, 4... Buffer section, 5... Image memory, 6... Latch section, 7. ... Addition section, 8...
Counter section, 9, 10.15.111... Decoder, 11... Luminance memory section, 12... Latch group,
13... Driver group, 14... Light emitting element group, 44.
...Switcher, 81...Horizontal address counter, 82.
... Vertical address counter, 91 ... Decoder with output dirt, 112.823 ... Dirt, 113 ... Brightness memory, 114 ... Brightness counter, 115 ... Comparator, 811 ... Frequency division circuit, 812°821.822
...Binary counter, 813...Memory. Patent applicant Fujitsu Shinden Co., Ltd. Patent application agent Patent attorney: Akira Ki, patent attorney Kazuyuki Nishidate Patent attorney: 1) Akira Shino, patent attorney Akira Yamaguchi

Claims (1)

[Claims] 1. A brightness control device for a large screen video device, the brightness control device converting a television screen video signal into red. Based on the separation circuit that separates and sends out green and blue color signals, horizontal synchronization signals, blanking signals, and vertical synchronization signals, and the reference frequency from the crystal oscillator and the horizontal synchronization signals, blanking signals, and vertical synchronization signals. A counter section that sends address signals and timing signals to the subsequent image memory and luminance memory to specify addresses, and a counter unit that performs address designation, and the signals after analog-to-digital conversion of each of the color signals in order to match the visual sense. a correction unit that performs logarithmic correction; a buffer unit that performs bit conversion to adjust the access speed after the image memory based on the buffering signal sent from the counter unit; In order to provide a time lag between the image memory addressed by the horizontal and vertical address signals from the counter section and the image output from the image memory and the luminance memory at the subsequent stage, the image memory is controlled based on the latch address signal from the counter section. a latch section that latches; an adder section that corrects luminance variations in subsequent light emitting elements based on a luminance memory signal from the latch section and a latch address signal from the counter section; A brightness memory for storing according to a predetermined brightness particle r-even based on the transmitted brightness memory address signal and the horizontal and vertical address signals, and a brightness memory for brightness adjustment based on the vertical address signal and its count signal. A brightness memory unit that includes a brightness counter that performs counting, and a comparator that compares the cough brightness counter output with the brightness memory output and outputs a lighting instruction for the light emitting element, and the output from the brightness memory unit is connected to a latch circuit. and a light emitting element that turns on after being converted to a predetermined timing and drive level by a driver circuit.