JPS59225556A - Manufacture of hybrid integrated circuit - Google Patents

Manufacture of hybrid integrated circuit

Info

Publication number
JPS59225556A
JPS59225556A JP58101064A JP10106483A JPS59225556A JP S59225556 A JPS59225556 A JP S59225556A JP 58101064 A JP58101064 A JP 58101064A JP 10106483 A JP10106483 A JP 10106483A JP S59225556 A JPS59225556 A JP S59225556A
Authority
JP
Japan
Prior art keywords
layer
integrated circuit
hybrid integrated
bonding
annealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58101064A
Other languages
Japanese (ja)
Inventor
Eiji Miyajima
宮嶋　栄志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58101064A priority Critical patent/JPS59225556A/en
Publication of JPS59225556A publication Critical patent/JPS59225556A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/702—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To contrive to enhance certainty of bonding, and to enhance precision of a formed resistance element at manufacture of a hybrid integrated circuit by a method wherein after the pattern of a base layer for a bonding pad consisting of an Au thin film is formed on a substrate, annealing treatment is performed, and then an Au layer is formed according to plating. CONSTITUTION:An Au layer 3 is evaporated on an Ni-Cr layer 2 adhered on a glazed alumina substrate 1. Annealing is performed to stabilize the resistance element formed in such a way. The annealing (b) thereof is executed in condition such as for 4hr at 275 deg.C to insure the desired strength at the later process of a hybrid integrated circuit, for example. The after a plated Au layer 4 is formed (c) on the pad part, trimming (d) of the resistance element is performed, and after then loading (e) of individual elements, outside lead terminals, etc. and connection of the circuits of the loaded elements are performed. Because diffusion of the Ni-Cr layer 2 to the plated Au layer 4 of the bonding pad is not generated in the hybrid integrated circuit manufactured in such a way, bonding to the pad can be performed surely, and the constant of the formed resistance element is not changed according to bonding.

Description

【発明の詳細な説明】 （ａ）　　発明の技術分野 本発明は混成集積回路の製造方法、特にその基板に形成
させた回路素子のアニールに関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method of manufacturing a hybrid integrated circuit, and more particularly to annealing circuit elements formed on a substrate thereof.

（ｂ）　　技術の背景 基板上に回路素子を形成及び搭載してなる混成集積回路
において、半導体素子等を搭載及び搭載素子を基板上の
形成回路に導体接続するため、該基板上にはポンディン
グパッドが形成される。一方、基板上に抵抗素子を形成
、例えばＴａ、Ｎ層の表層部を陽極酸化させてＴａｘｅ
ｓ層を適当な厚さに形成させた抵抗素子は、その抵抗値
を安定化させるためのアニ・−ルが行われている。(b) Background of the technology In hybrid integrated circuits in which circuit elements are formed and mounted on a substrate, bonding is required on the substrate in order to mount semiconductor elements and connect the mounted elements to the formed circuit on the substrate. A pad is formed. On the other hand, a resistance element is formed on the substrate, for example, by anodizing the surface layer of the Ta and N layers,
A resistor element having an S layer formed to an appropriate thickness is annealed to stabilize its resistance value.

（ｃｌ　　従来技術と問題点 第１図は熱圧着法により回路素子を搭載又は金属細線を
ボンディングするパッドの一般構成を示す断面図、第２
図は抵抗素子を形成した薄膜混成集積回路の従来方法に
よる主要工程を示した図である。(cl) Prior Art and Problems Figure 1 is a cross-sectional view showing the general configuration of a pad on which a circuit element is mounted or a thin metal wire is bonded by thermocompression bonding.
The figure shows the main steps of a conventional method for manufacturing a thin film hybrid integrated circuit in which a resistive element is formed.

第１図において、１はグレーズドアルミナ基板。In Figure 1, 1 is a glazed alumina substrate.

２は基板１の上に被着したＮｉ−ＣｒＭｅ　　３はＮｉ
−ＣｒＪＭ２の上に蒸着したＡｕ層、４はＡｕ層３の上
にめっき形成したＡｕ層である。そしてこのように構成
されたポンディングパッドは、一般に厚さ２００Ａ程度
のＮｉ−Ｃｒ層２を下地層として厚さ６０００Ａ程度の
蒸着Ａｕ層３を基層とし、その上にボンディング上必要
となる数μｍの厚さにめっきＡｕ層４を形成している。2 is Ni-CrMe deposited on the substrate 1 3 is Ni
-CrJM An Au layer is deposited on 2, and 4 is an Au layer formed on Au layer 3 by plating. The bonding pad constructed in this way generally has a Ni-Cr layer 2 with a thickness of about 200A as a base layer, a vapor-deposited Au layer 3 with a thickness of about 6000A as a base layer, and a layer of several micrometers necessary for bonding on top of the Ni-Cr layer 2 with a thickness of about 200A as a base layer. The plated Au layer 4 is formed to a thickness of .

第２図において、混成集積回路は基板上に薄膜抵抗素子
や導体パターン等を形成したのち、パッド部分にめっき
Ａｕ層（４）を形成する。次いで、前記抵抗素子を安定
化させるためのアニール、例えば２００℃に加熱して、
炉中に前記基板を約４時間投入する。然るのち、前記抵
抗素子のトリミングを行なって抵抗値を定数に調整して
から、個別素子や外部リード端子等を搭載及び搭載素子
の回路接続を行なう。In FIG. 2, the hybrid integrated circuit is manufactured by forming thin film resistive elements, conductor patterns, etc. on a substrate, and then forming a plating Au layer (4) on the pad portion. Next, annealing is performed to stabilize the resistive element, for example, by heating it to 200°C.
The substrate is placed in a furnace for about 4 hours. After that, the resistor element is trimmed to adjust the resistance value to a constant value, and then individual elements, external lead terminals, etc. are mounted, and circuit connections of the mounted elements are performed.

然しながら、前記アニールを後工程での加熱温度と同等
以上にする理想的条件で実施したときは、Ｎｉ−Ｃｒ層
２がＡ　ｕ　Ｊ衿３．４に熱拡散し、該拡散のはなはだ
しいときにはパッドへ熱圧着法でボンディングすること
が不可能となるため、アニール条件が制約されたシめつ
きＡｕ層４をその対応策として厚くしていた。とともに
、素子の搭載及び搭載素子の回路を金属細線で接続する
条件が、アニールの実施条件に制約されるという欠点が
あった。However, when the annealing is carried out under ideal conditions at a heating temperature equal to or higher than the heating temperature in the subsequent process, the Ni-Cr layer 2 will thermally diffuse into the Au J collar 3.4, and when the diffusion is extreme, it will spread to the pad. Since it is impossible to bond by thermocompression bonding, the crimped Au layer 4, which has limited annealing conditions, has been made thicker as a countermeasure. Additionally, there is a drawback that the conditions for mounting the elements and connecting the circuits of the mounted elements using thin metal wires are restricted by the conditions for performing annealing.

（ｄ）　　発明の目的 本発明の目的は、上記問題点を除去した混成集積回路の
製造方法を提供することである。(d) Object of the Invention An object of the present invention is to provide a method for manufacturing a hybrid integrated circuit that eliminates the above-mentioned problems.

（ｅ）　　発明の構成 上記目的は、基板上にＡｕの薄膜からなるポンディング
パッド用基層をパターン形成したのち、該基板上に形成
させた回路素子のアニール処理を行い、次いで該基層の
上にＡｕ層をめっき形成することを特徴とする混成集積
回路の製造方法によシ達成される。(e) Structure of the Invention The above object is to pattern a base layer for a bonding pad made of a thin Au film on a substrate, perform an annealing treatment on the circuit elements formed on the substrate, and then apply a bonding pad base layer on the base layer. This is achieved by a method of manufacturing a hybrid integrated circuit characterized by forming an Au layer by plating.

（ｆ）　　発明の実施例 以下、本発明方法の実施例に係わる薄膜混成集積回路の
主要工程を示！ｒへ第３図について説明する。(f) Embodiments of the Invention The main steps of a thin film hybrid integrated circuit according to embodiments of the method of the present invention are shown below! 3 will be explained.

第３図において、混成集積回路は基板上に抵抗素子や導
体パターン及びポンディングパッドの基層（第１図の蒸
着Ａｕ層３）等を形成したのち、該抵抗素子を安定化さ
せるためのアニールを行なう。In Figure 3, the hybrid integrated circuit is manufactured by forming a resistive element, a conductor pattern, a base layer of a bonding pad (deposited Au layer 3 in Figure 1) on a substrate, and then annealing is performed to stabilize the resistive element. Let's do it.

ただし、前記アニールは混成集積回路のその後の工程、
例えば所望の強度を確保するための２７５℃で４時間の
如き条件にて実施する。However, the annealing is a subsequent step of the hybrid integrated circuit.
For example, it is carried out under conditions such as 275° C. for 4 hours to ensure the desired strength.

、　　次いで、パッド部分にめっきＡｕ層を形成させた
のち、前記抵抗素子のトリミングを行なってから、個別
素子や外部リード端子等を搭載及び搭載素子の回路接続
を行なう。Next, after forming a plating Au layer on the pad portion, the resistor element is trimmed, and then individual elements, external lead terminals, etc. are mounted, and circuit connections of the mounted elements are performed.

従って、このように製造された混成集積回路は、ポンデ
ィングパッドのめつきＡ　ｕ　層にＮｉ−Ｃｒ層の拡散
が行なわれてないため、パッドへのボンディングが確実
に行なわれるとともに、該ボンディングにより形成抵抗
素子の定数が変化しない。又は従来方法のものより変化
量が著しく低減したとともに、Ｎｉ−Ｃｒ層の拡散に対
処してめっきＡｕ層を厚くする必要がなくなった。Therefore, in the hybrid integrated circuit manufactured in this way, since the Ni-Cr layer is not diffused into the plating A u layer of the bonding pad, bonding to the pad is ensured, and the bonding The constant of the forming resistive element does not change. Alternatively, the amount of change is significantly reduced compared to that of the conventional method, and there is no need to increase the thickness of the plated Au layer in order to cope with the diffusion of the Ni--Cr layer.

（ロ））発明の詳細 な説明した如く本発明方法によれば、ボンディングの確
実性及び形成した抵抗素子の精度が向上【７、そのこと
によって混成乗積回路の＠照性が高められた効果は極め
て大きい。(b)) As described in detail, according to the method of the present invention, the reliability of bonding and the accuracy of the formed resistive elements are improved [7, which has the effect of improving the @ illumination of the hybrid product circuit. is extremely large.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はポンディングパッドの一般的構成例を示す断面
図、第２図は抵抗素子を形成した薄膜混成集積回路の従
来方法による主要工程を示した図、第３図は本発明方法
の実施例に係わシ薄膜混成集積回路を製造する主要工程
を示した図である。 図において、１は基板、２はＮｉ−Ｃｒ層、３は蒸着Ａ
ｕ層、４はめつきＡｕ層を示す。Figure 1 is a cross-sectional view showing an example of a general configuration of a bonding pad, Figure 2 is a diagram showing the main steps of a conventional method for producing a thin film hybrid integrated circuit in which a resistor element is formed, and Figure 3 is a diagram showing the implementation of the method of the present invention. FIG. 3 is a diagram illustrating the main steps of manufacturing a thin film hybrid integrated circuit according to an example. In the figure, 1 is the substrate, 2 is the Ni-Cr layer, and 3 is the vapor deposition A.
U layer, 4-plated Au layer is shown.

Claims (1)

【特許請求の範囲】[Claims] 基板上ＫＡｕの薄膜からなるポンプイングツ（ラド周基
層をパターン形成したのち、該基板上に形成させた回路
素子のアニール処理を行い、次いで該基層の上にＡｕ層
をめっき形成することを特徴とする混成集積回路の製造
方法。Pumpings consisting of a thin film of KAu on a substrate (characterized by patterning a peripheral base layer, annealing the circuit elements formed on the substrate, and then plating an Au layer on the base layer) A method for manufacturing hybrid integrated circuits.
JP58101064A 1983-06-07 1983-06-07 Manufacture of hybrid integrated circuit Pending JPS59225556A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58101064A JPS59225556A (en) 1983-06-07 1983-06-07 Manufacture of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58101064A JPS59225556A (en) 1983-06-07 1983-06-07 Manufacture of hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS59225556A true JPS59225556A (en) 1984-12-18

Family

ID=14290673

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58101064A Pending JPS59225556A (en) 1983-06-07 1983-06-07 Manufacture of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS59225556A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6777797B2 (en) 2002-06-27 2004-08-17 Oki Electric Industry. Co., Ltd. Stacked multi-chip package, process for fabrication of chip structuring package, and process for wire-bonding

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6777797B2 (en) 2002-06-27 2004-08-17 Oki Electric Industry. Co., Ltd. Stacked multi-chip package, process for fabrication of chip structuring package, and process for wire-bonding
US7179685B2 (en) 2002-06-27 2007-02-20 Oki Electric Industry Co., Ltd. Fabrication method for stacked multi-chip package

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