JPS5922494A - Gate signal generator - Google Patents

Abstract

PURPOSE:To eliminate the effect of temperature even with no adjustment, by generating a gate signal with a digital counter and using a clock signal used for the digital counter in common for a reference signal of a servo circuit. CONSTITUTION:An output level of the digital counter 38 goes to L0, when it counts n2(=tau2/fCP, where fCP is clock frequency) sets of clocks. The tau2 is selected between H/2-H, where H is the horizontal scanning period. Then, there exists an equalizing pulse at the vertical synchronizing section, a set input is impressed before the count is finished and the counter output keeps Hi. The output of the counter 38 is applied to a counter 39 and an output of the counter 39 is inverted at an inverter 40, then a gate signal is obtained. Since the output of the reference clock signal generating circuit for servo is used in common for the clock signal, the oscillating circuit is not especially required for the provision.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate signal generating device used in a SECAM type magnetic recording/reproducing device.

FIG. 1 is a diagram schematically showing a magnetic recording/reproducing apparatus. The magnetic tape 1 is wound diagonally around the cylinder 2 and attached to the capstan 3.
It is driven and travels in the direction of the arrow. A cylinder motor (not shown) is driven by a cylinder motor drive circuit 4.

Further, a capstan motor (not shown) is driven by a capstan motor drive circuit 5.

6 is a servo circuit that connects cylinder 2 and capstan 3.
is controlled so that it rotates at a specified speed and phase. Reference numeral 7 denotes a reference clock generating circuit, and the servo circuit 6 operates digitally using the output of this circuit.

FIG. 2 is a block diagram of a circuit for recording and reproducing video signals. The luminance signal component of the video signal input from the video signal input terminal 8 is modulated into an FM signal by the luminance signal recording processing circuit 9 and input to the YC mix circuit 10, while the color signal component is input to the YC mix circuit 10. The signal processed by the circuit shown in FIG. 1 is superimposed with the FM-modulated luminance signal by the YC mix circuit, outputted from the recording signal output terminal 18, and recorded on the magnetic tape 1 by the head attached to the cylinder 2. 11H hand bath filter,
12 is a Havel filter, 16 is a limiter, 14 is a countdown circuit, 15 is a gate circuit, 16 is a low-pass filter, and 17 is an equalizer. Bandpass filter 11
The color signal components extracted through the filter are applied to the bell filter 12. The color signal of SECAM method is F
It is an M modulated signal, but the antibell filter on the transmitting side
Since the MO sideband is emphasized, this bell filter suppresses the MO sideband and the signal is returned to the original FM signal. The signal, which has passed through the limiter 13 that limits the amplitude fluctuation of the FM signal and has become a rectangular wave signal, is passed through a color down circuit.
The frequency is reduced to 1/4. A signal that has passed through a gate circuit 15 (to be described later) has unnecessary components removed by a low-pass filter 16, and side banded by an equalizer 17. FIG. 6 shows the waveforms of each part. A color signal is extracted from the video signal (a) by a low-pass filter 11 and a bell filter 1
If 2 is passed through, it becomes as shown in (b). However, when a limiter is applied, noise appears in the synchronization signal section where there is no color signal, as shown in (c). If this is recorded and played back and then added to the luminance signal again, unnecessary noise will be superimposed on the synchronization signal, causing the TV receiver's synchronization separation to malfunction, causing phenomena such as jitter and the inability to achieve vertical synchronization. be. In order to avoid this, a gate signal (d) is created by waveform shaping the synchronization signal, and this is added to the gate circuit 15 to suppress the unpleasant noise component as shown in (e).

The gate signal is generated by a gate signal generation circuit 32.

31 is a synchronization signal input terminal. On the other hand, the playback side will be explained. The RF multiplied signal reproduced by the head is applied to the reproduced RF signal input terminal 19. The luminance signal is FM demodulated by the luminance signal reproduction processing circuit 20 and input to the YC mix circuit 21 . The color signal component is returned to the original signal by circuits 22 to 29, mixed with the luminance signal by the YC mix circuit 21, and sent to the video signal output terminal -f! -50 is output.

22 is a low-pass filter, 26 is a reproduction equalizer, 24
25 is a band pass filter, 26 is a limiter, 27 is a gate circuit, 28 is a band pass filter,
29 Hantipel filter. Low pass filter 2
The reproduced color signal extracted in step 2 passes through a reproduction equalizer 23 having characteristics opposite to those of the recording equalizer 17, and is multiplied by 4 in a multiplier circuit 24. The band pass filter 25 removes unnecessary frequency components and reduces the limit to 1. The signal added at 26 is now limited in amplitude. Noise generated in the synchronizing signal portion by applying the limiter during recording as described above is similarly removed by the gate circuit 27. Unnecessary harmonic components are removed by a bandpass filter 28, sidebands are emphasized by an antibell filter 29, and a color signal is applied to a YC mix circuit.

Next, a conventional gate signal generation circuit will be described. Fourth
The figure shows an example of this, where 66 is a synchronizing signal input terminal and 67 is a gate signal output terminal. Figure 5 shows the waveform. The vertical synchronization signal of the input synchronization signal (c) is separated by the vertical synchronization signal separation circuit 54 as shown in FIG. As shown in (b), the multi is maintained at Lo level for a period of τl from the fall of the horizontal synchronizing signal (a). τl is determined by the time constant of the capacitor C and the variable resistor R. The output of the mono multi 65 is ORed. added to the other input of the circuit,
A gate signal is obtained that gates both the vertical synchronization section and the horizontal synchronization section.

In this way, the conventional circuit uses an analog monomulti, so adjustment is required to absorb circuit variations, and the present invention has the disadvantage that the time constant changes depending on the temperature. The purpose is to eliminate the conventional drawbacks mentioned above! Another object of the present invention is to provide a gate signal generating device that does not require adjustment and is not affected by temperature.

The present invention is characterized in that a gate signal is generated by a digital counter, and a clock signal used for the digital counter is also used as a reference signal for a servo circuit.

Hereinafter, the present invention will be explained according to examples. FIG. 6 is a diagram showing an embodiment of the present invention. 38 in Figure 6
, 39 is a digital counter, 4° is an inverter, 41
is a clock input terminal. FIG. 7 shows the waveforms of each part. FIG. 6(a) shows a synchronizing signal input from the synchronizing signal input terminal 63 to the digital counter 68 in FIG. 6, and Φ) is a clock applied to the digital counters 58 and 59. The tenth counter 3B is set and starts counting at the falling edge of the synchronization signal, and n2=τz/fcp (however, f
When cp is the clock frequency) clocks are counted, the output level becomes Lo. If a set input is applied within 11 after the start of counting, counting starts again from zero.

τ2 is selected between V2 and H, assuming that the horizontal scanning period is H.

Then, since there is an equalization pulse in the vertical synchronization section, the set input is applied before the count ends, and the counter output maintains Hi as shown in (c). The output of the first counter is added to the second counter 39, and when the output of the first counter rises, the second counter 69 is set and starts counting. The output level becomes Lo as shown in FIG. 7(e). This τl is equal to τ1 in FIG. When the output of the second counter 39 is inverted by an inverter 40, the gate signal shown in FIG. 4(e) is obtained.

The vertical synchronization section indicated by the broken line is also Hi. The clock signal applied to the clock input terminal 41 is 7 in FIG.
Since the output of the servo reference clock signal generation circuit shown in can be shared, there is no need to provide a separate oscillation circuit.

As described above, according to the present invention, the gate signal is generated using a digital counter, so there is no need for adjustment and there is no change due to temperature. Furthermore, since the reference clock signal used in the servo circuit is commonly used as the clock for the counter, there is an advantage that there is no need to provide a separate oscillation circuit.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the outline of a magnetic recording and reproducing device.
FIG. 42 is a block diagram of a video signal recording/reproducing circuit, FIG. 3 is a waveform diagram showing waveforms of various parts in FIG. 2, and FIG. 4 is a block diagram of a conventional gate signal generation circuit. 5 is a waveform diagram showing the waveforms of each part in FIG. 4, and FIG. 6 is a waveform diagram showing the waveform of each part in FIG. FIG. 7 is a waveform diagram showing waveforms at various parts in FIG. 6. 1...Magnetic tape, 2...Cylinder, 6...
- Capstan, 4... Cylinder motor drive circuit, 5... Capsun motor drive circuit, 6... Digital servo circuit, 7... Reference clock generation circuit, 8... Video signal input terminal, 9 ... Luminance signal recording processing circuit, 10 ... YC mix circuit, 15 - limiter, 14
...Countdown circuit, 15...Gate circuit, 18...Record signal output terminal, 19...Reproduction RF signal input terminal, 20...Brightness signal reproduction processing circuit, 21...YC mix circuit- 24... multiplication circuit,
26... Limiter circuit, 27... Gate circuit, 60
...Video signal output terminal, 31...Sync signal input terminal, 32...Gate signal generation circuit, 33...Sync signal input terminal, 64...Vertical synchronization signal separation circuit, 35...Mono Multi, 37...Gate signal output terminal, 38.39...Digital counter, 41...Clock signal input terminal.

Claims (1)

[Claims] 1. A magnetic recording and reproducing device that performs FM modulation on the luminance signal of the SECAM system video signal, and counts down the color signal and multiplexes it onto the lower frequency side of the lower band of the FM signal and records the color signal component. A device for suppressing noise components generated in a non-existent synchronization signal portion by a gate signal includes a reference clock signal generation circuit that generates a reference clock for a digital servo circuit that controls a cylinder and a capstan, and the reference clock signal generation circuit. It has a digital counter that uses the output signal of the circuit as a clock, and by applying the synchronization signal of the video signal to the digital counter as a count start signal, the output of the digital counter is used to gate the noise component generated in the synchronization signal section. A gate signal generating device characterized in that the gate signal is generated at a constant rate.