JPS5922280B2 - Wireless maritime navigation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wireless maritime route-directing device comprising two or more route-directing members separated from each other at sea and cooperating with each other by means of coded radio signals.

Maritime navigation elements, such as lights and foghorns, are used to mark obstacles in waterways and otherwise direct maritime navigation.

Often, multiple indicating members are used in combination to generate synchronized or continuous navigation signals.

See, eg, US Pat. No. 3,781,853.

Such navigation devices are interconnected by electrical cables for control.

However, there are many problems in attempting to interconnect two navigation members that are separated from each other underwater, such as floating buoys.

Such cables are subjected to external forces that tend to break them, causing voltage loss in the cables and making installation difficult.

The invention relates to a wireless maritime navigation device comprising two or more navigation elements interconnected by radio signals, such as acoustic signals, instead of interconnecting cables.

The present invention relates to various improvements in wireless maritime navigation devices in which two or more navigation elements cooperate by means of radio signals.

It is an object of the present invention to comprise at least one transmitter and one receiver for controlling the operation of maritime navigation elements, each of which includes a timing clock and coded radio signal transmission means. An object of the present invention is to provide a wireless maritime navigation device that can be used as a wireless navigation device.

The first navigation member is electrically connected to and operated by the transmitter.

The receiver is remote from the transmitter and includes a timing clock and means for receiving and decoding the coded signal from the transmitter.

The second navigation member is electrically connected to and operated by the receiver.

Although the receiver timing clock is self-operating so that the second navigation member is always properly timed, the receiver timing clock is controlled and reset by the transmitter timing clock through a coded signal so that the receiver The aircraft's navigation elements are controlled by a transmitter.

Another object of the invention is to provide at least one transmitter and a receiver for controlling the operation of each of the maritime navigation members, the receiver being controlled by the transmitter through coded radio signals. It is an object of the present invention to provide a wireless maritime navigation device in which a receiver is prevented from being operated by spurious external signals.

Another object of the present invention is to provide accurate time control between the route indicating member of the transmitter and the route indicating member of the receiver over a long period of time even if a predetermined signal is not received by the receiver. and a stable timing clock in both the receiver and the receiver.

Yet another object of the invention is to provide a closed circuit in a receiver adapted to inhibit control of the receiver by the transmitter when external radio signals exceed a predetermined level.

Other features and advantages of the invention will become apparent from the following description of the embodiments.

Although the wireless marine navigation device of this invention is described for illustrative purposes as using audio signals to synchronize navigational lighting, the invention is useful for controlling other types of navigational navigation elements, such as horns. It is recognized that it is useful and advantageous to use forms of wireless signals, such as light waves or radio waves.

Furthermore, although the invention is described in connection with a navigation system in which the navigation lights are synchronized with each other, the invention also provides a system in which one navigation element is controlled by a second navigation element, such that in a desired time sequence. It is recognized that it can be used in any operation in which it is designed.

Referring to FIG. 1, the wireless marine navigation system of the present invention is indicated generally by the reference numeral 10, marking the opposite limits 12, 14 of a waterway 16.

The first marine buoy 18 includes a transmitter 20 that operates conventional channel lighting 22 and transmits a coded sound signal 24;
Sound signal 24 operates and controls one or more channel lights, such as lights 26 on buoy 28, including receiver 30.

A second set of buoys 32,34 each having a respective channel illumination 36,38 is provided along the waterway 16;
has a transmitter 40 and buoy 34 has a receiver 42.

However, the sound signal 44 emitted from the transmitter 40
The sound signal 24 emitted from the transmitter 20 has a different code.

Similarly, system 10 includes buoys 46, 48, etc. each having navigational lights 50, 52, buoy 46 having a transmitter 54 and buoy 48 having a receiver 56.

The sound signal 58 emitted from the transmitter 54 is transmitted to the transmitter 20.4.
The coded signal 58 is the same as the coded signal 24, or if the buoys 46, 48 are far enough away from the buoy 18°28, the coded signal 58 is the same as the coded signal 24. It may be.

A common circuit, designated generally by the reference numeral 60, is illustrated, which circuit includes transmitters such as transmitter 20 of buoy 18 and buoy 28.
receiver, such as receiver 30.

The common circuit includes a photosensitive switch circuit 62, which circuit 62
switches to cut off input voltage from other circuits during the day, thereby conserving battery power for general use.

Circuit 60 also includes a voltage regulation circuit 64 that provides regulated voltages to other circuits.

Additionally, a crystal oscillator 66 is provided which operates when the photosensitive switch circuit 62 is closed and receives power from the voltage regulator 64 to generate a 1 MHz 5 volt rectangle for use by either the transmitter or the receiver. generate waves.

Referring to FIG. 3, a transmitter circuit, generally indicated by the reference numeral 68, operates and synchronizes a digital counter 70 that receives a 1 MHz signal from common circuit 60 of FIG. 2, and for combined route lighting. The first to generate the pulse
Including exit cuff 2.

For example, referring to buoy 18 in FIG.
The output cuff 2 generates a synchronization signal to the route lighting 22, which may be of any suitable type, such as a model TF-3B flasher/lamp changer sold by Tideland Signal Corporation. can.

Additionally, the transmitter circuit generates a 50 kilohertz gate signal at output cuff 4 of a suitable code providing a sound signal such as signal 24 in FIG.

The desired code is obtained from memory circuit 76 through the appropriate code selection switch 78.

The switch 78 outputs coded signals 1, 2, 3 as shown in FIG.
1.2.3, which correspond to signals 24, 44, 5B of FIG. 1, respectively.

Referring to FIG. 4, a digital counter 82 receives a 1 MHz timing signal from common circuit 60 of FIG.

Counter 82 sends a signal to a second digital counter 84, and an amplifier 86 connected to the output of counter 84 is operated to provide a synchronization signal to the route lights, such as in FIG. .

Therefore, the route illumination connected to the receiver 30 is
Even if there is no sound signal from the transmitter circuit shown in the figure, operation signals from the timing counters 82 and 84 are normally received.

Receiver circuit 80 also includes a detector 88 that receives signals from transmitter 68 of FIG. 3 to synchronize illumination 26 of receiver 28 of FIG. 1 with illumination 22 of transmitter 20 of FIG. Receive sound signals.

However, since external noise that interferes with the sound signal from the transmitter circuit 68 in FIG. 80 control is prohibited.

When closed circuit 90 does not inhibit normal system operation, the sense signal is sent to flip-flop circuit 92 which operates digital counter 94.

Counter 94 operates memory circuit 96 and
produces a code output identical to the transmitter code to which receiver circuit 80 responds.

The output from memory circuit 96 is compared with the sense signal in digital comparator 98 and, if the result of this comparison is correct, a reset signal is sent over line 100 to digital counter 84 to control the operation of receiver illumination 26. This counter 84 is reset, thereby ensuring synchronization of the receiver and transmitter route illuminations.

The timing signal from the common circuit includes a crystal oscillator 66, and the transmitter circuit 68 of FIG. 3 and the receiver circuit 80 of FIG. 4 include digital counters that count down the timing signal to a highly accurate and stable signal. Please note that there are.

Therefore, even if the receiver does not fully decode the sound signal from the transmitter for a period of time, the outputs of transmitter circuit 68 and receiver circuit 80 remain synchronized for a long time.

Referring to FIG. 5, the common circuitry of FIG. 2 is shown in more detail.

The photosensitive switch 62 operates as a switch that cuts off input voltage from other circuits during the day.

Reverse polarity diode 104 protects the entire circuit when the input voltage is reversed.

An operational amplifier 106 is used in this circuit as a voltage comparator.

Photosensitive switch 62 is connected to a voltage divider consisting of resistor 108 and the input voltage.

Another voltage divider is formed from resistors 110,114.

When light hits the photosensitive switch 62, the voltage at the negative terminal of the amplifier 106 becomes higher than the voltage at the positive terminal.

Therefore, the output of amplifier 106 is low (approximately 1 volt)
.

When the photosensitive switch 62 is in the dark, the voltage at the negative terminal of the amplifier 106 is lower than the voltage at its positive terminal;
The output of amplifier 106 is high (approximately 11 volts).

When the output of amplifier 106 is low (daytime), transistor 116 is off and transistor 118 is also off.

Therefore, no voltage is transmitted to other parts of the device.

When the output of amplifier 106 is high (at night), transistor 116 is conductive and transistor 118 is conductive to provide voltage to other circuit sections.

Voltage regulator 64 is an integrated circuit component.

An unregulated voltage (approximately 12 volts when transistor 118 is conductive) is applied to the input of regulator 64, and a regulated 5 volt voltage is placed at its output.

A 1 MHz crystal oscillator 66 receives the 5 volt voltage from regulator 64 and produces a 1 MHz 5 volt square wave output.

Referring to FIG. 6, the transmitter circuit 68 shown in block form in FIG. 3 is shown in further detail.

Circuit 68 receives a 1 MHz signal on line 120 from common circuit 60 (FIGS. 2 and 5), which signal is
Divide by 0) Counter 122, 124゜126, 128
The frequency is transmitted to 1 MHz and counts down from 1 MHz to 100 Hz.

The 100 kHz signal from output 130 of counter 122 is transmitted to flip-flop 132 to become a 50 kHz signal.

The 100 hertz signal from counter 128 is communicated to binary counter 134.

The first flip-flop of counter 134 is not used (
This flip-flop is 5 for the remaining flip-flops.
(generates a 0 Hertz signal).

When 50 hertz is converted into time, it is 20 milliseconds.

If 250 20 millisecond time intervals are counted, the total time interval is 5000 milliseconds.

Counter 134 does this counting.

The output of binary counter 134 is used as an address in memory 136.

Memory 136 is a read memory programmed according to the code to be transmitted.

Outputs 1, 2, and 3 of the memory 136 are the three types of codes shown in FIG.

Output 4 of memory 136 is the service line.

This service line 4 does two things.

That is, a synchronization signal is generated for the route flashing lights associated with the transmitter circuit 68, and the counter 134 is
Generates a reset signal when the count is reached.

The diode 138 connects the generated synchronization signal to the counter 134.
The diode 140 also prevents the reset signal from being transmitted as a synchronization signal.

Synchronization signal 4 from memory 136 occurs at count 206 of binary counter 134.

The final signal for each code occurs at count 196.

The difference between them is therefore 10 counts or 200 milliseconds.

Sound travels at a speed of approximately 5000 feet/second underwater.

So 200 milliseconds is equivalent to 1000 feet.

The delay between the time the final pulse travels and the time the synchronization signal occurs corresponds to 200 milliseconds or 1000 feet of propagation time in water.

This delay time is 170 milliseconds or a distance of 850 milliseconds.
ft. circuitry can be included in the receiver.

Thus, the transmitter 20 and receiver 30 (FIG. 1) may be spaced 850 feet apart with this delay circuit or 1000 feet apart without this delay circuit.
If the feet are spaced apart from each other, the lighting 22.
26 is accurately synchronized.

If the mutual spacing is narrower, the receiver lights 26 will be turned on first, and if the mutual spacing is wider, the transmitter lights 22 will be turned on first.

The synchronization signal leaving the memory 136 is sent to two inverters 142.
．． 144 and transistor set 146 before being sent from line 72 to the illumination.

Only one of code outputs 1, 2, and 3 is used at a given time.

The following explanation applies to all three codes.

The code output of memory 136 is low for the base (0 volts) and high for the transfer (5 volts).

When the output of memory 136 is low, the base of transistor 148 is held low through diode 150.

When the output of memory 136 is high, diode 150 is disconnected.

The time required for each count of the binary counter 134 is 2
0 milliseconds and it is desirable that the transmission burst time is 10 milliseconds, so the binary counter 1
34 output 152 (50 Hz square wave), inverter 1
54 and diode 156 are used to limit the burst length.

Therefore, the output of inverter 154 is high only during the first 10 milliseconds of the 20 milliseconds when the output of memory 136 is high.

For the next 10 milliseconds, the base of transistor 148 is held low through diode 156, inhibiting transmission.

However, if both diodes 154 and 156 are disconnected, the 50 kilohertz signal from flip-flop 132 is applied to the base of transistor 148, amplified, and transmitted through output line 74 to the underwater transducer.

7A and 7B, the receiver circuit 80 of FIG.
The clock and sensing circuits are shown in detail.

This portion of the receiver circuit has inputs +12 volts, +5 volts, ground, the 1 MHz signal from the crystal oscillator 66 in the common circuit 60, and the sound signal from the transmitter received by the underwater transducer.

The outputs of the clock and detector circuit, designated generally by the reference numeral 160, are a 100 hertz signal, a 1 kilohertz signal, and a detected sound signal.

4 decimal counters 162, 164, 166° 168
is used to count down the 1 MHz signal to 1 kilohertz and 100 hertz.

These two types of frequencies are used in the decoder circuit.

Counter 1620 counts “0”, “5” provides clock inputs to two flip-flops 170.

The count "0" of counter 162, r5J, is i periods apart at 100 kilohertz.

This means that the output of the flip-flop 170 has a period of 10 cycles (
This means that it is a 50 kHz signal separated by 90 degrees.

A voltage follower 172 and its combination components are used to generate a noise independent +5 volt voltage.

This voltage is divided by a voltage divider consisting of resistors 174, 176, 178°180.

The voltage generated by this circuit is used as a reference voltage in other parts of the circuit.

The input sound signal from the transmitter is received through an underwater transducer and a capacitor 182 which acts as a voltage clipper circuit.
and diode 184 to pass a maximum of +9 volts and a minimum of -0.7 volts.

Large signals are limited to both of these limits.

The signal is then provided to voltage follower circuit 186.

Voltage follower circuit 186 is simply used as a single buffer amplifier.

This circuit also biases the converter signal to 5 volts.

The 50 kilohertz waveform then changes to approximately +5 volts.

Transistors 188 and 190 are each fed a 50 kilohertz square wave signal from flip-flop 170.

These 50 kilohertz signals are offset by 90 electrical degrees.

The time interval for the 50 kHz signal is 20 microseconds.

Each of the transistors 188 and 190 has a + of this period.
(10 microseconds) and conductive for another ten periods (10 microseconds).

For explanation, transistor 190, resistors 192, 194
, 198, and the circuit including the capacitor 196°200.

Components 194°196.198.200 form the low-pass filter section.

Transistor 190 acts as a single chopper.

The 50 kHz signal from follower circuit 186 is chopped at a rate of 50 kHz.

Thus, exactly ten periods of this input signal are applied to the input of the filter.

The phase relationship between the 50 kHz chopped signal and the 50 kHz signal from voltage follower 186 is random.

Therefore, during the sampling process, the selected samples will have an average voltage that is less than or equal to the 5 volt resting voltage from the follower 186.

If there is no signal from follower 186 (or if the sample average voltage is 5 volts), the chopper
Since it works with a duty factor of 0%, the voltage averaged by the filter (at the junction of 198 and 200) is 2
．． It is 5 volts.

For sampling where the sample has a net voltage greater than 5 volts, the output voltage of the filter will be 2.5 volts plus half the net applied voltage.

Conversely, if the sample has a net voltage of less than 5 volts, the output voltage of the filter will be 2.5 volts minus half the net reduced voltage.

If the input signal samples are at a voltage centered around 5 volts, the net change in the voltage samples is zero volts, and the output voltage of the filter is 2.5 volts plus zero volts, or 2.5 volts.

Therefore, in this case, the signal appearing at the output of the filter does not show any change in voltage.

For the above reasons, transistor 188 resistor 202.20
4.208, a circuit consisting of capacitors 206 and 210 is also included.

This circuit also samples the signal from voltage follower 186, but the sample is centered around a point 90 electrical degrees away from another circuit.

This means that with the circuit including transistor 190 sampling the signal from follower 186 near 5 volts, the circuit including transistor 188 will sample that signal at the greatest deviation from 5 volts.

The output of this filter (junction of 208 and 210) is then the possible firing excursion of this input signal plus or minus 2.5 volts.

If there is no signal at the input, the output of each filter will be 2.
It is 5 volts.

When the signal is present, the output of each filter either goes above, below, or remains at 2.5 volts.

However, when the signal is interrupted, the output of at least one of both filters is not maintained at the rest level of 2.5 volts.

Connected to the output side of each filter are non-inverting amplifiers 212 and 214, each having a gain of about 2.

This amplifier has three functions. First, the gain of the circuit is amplified from the center 2.5 volt signal from the filter to the center 5 volt signal.

Second, 2.5 volts from the filter (along with the signal)
Double the deviation of .

Third, the signal is buffered from the high impedance filter to the low impedance operational amplifier output.

Recall here that the signals received by this circuit occur during bursts of 10 milliseconds.

Note also that the outputs of amplifiers 212, 214 will be 5 volts in the absence of a signal, and when a signal is present, one or both of these outputs will be at some voltage different from 5 volts.

A 10 millisecond power input signal then moves the output of amplifier 212 (for example) from its resting 5 volt level for 10 milliseconds.

This signal is then passed through capacitor 216 to amplifier 21.
Applies to 8.

AC coupling through capacitor 216 allows DC level shifting.

The other half of the circuit is similar.

The circuit portions associated with amplifier 218 will be described below.

The circuitry associated with amplifier 220 is similar.

Amplifier 218 is used as an amplifier with a gain of -50 (the minus signifying inversion of the signal).

Additionally, the output of this amplifier is level shifted and varies around a 3.5 volt level rather than a 5 volt level.

The output of the amplifier 218 is connected to two voltage comparators 224, 226
connected to.

The comparison voltages of comparators 224 and 226 are set to 5.0 volts and 4.7 volts, respectively.

Therefore, the voltage of capacitor 222 is reduced to its resting voltage 4.
A change of more than 0.15 volts from 85 volts causes the output of one comparator to go low.

Since the outputs of the comparators are connected together, only one signal is required to vary more than 0.15 volts from the no signal level.

For reasons stated earlier, the signal at capacitor 222 does not change during the signal burst, but in this case capacitor 228
The signal at changes during this burst to operate one of the comparators 230 and 232 to generate a sense output.

8A and 8B, the receiver circuit 80 of FIG.
The decoder and synchronization pulse generator parts of are shown in detail.

Decoder and sync pulse generator circuit 234 has +5 volts as input, ground, clock and detector circuit 1
60 to 100 hertz square wave, 1 kilohertz square wave,
and detection signal output.

The output of this circuit is a synchronization signal to a light such as the 'l'F-3B flasher/lamp changer.

The synchronization signal generator portion of this circuit operates on a sequential basis and is synchronized with the synchronization signal generator of transmitter circuit 68 (FIGS. 3 and 6) upon receipt of the appropriate signal code.

The synchronization signal generator is a decimal counter 236°238.24
0 and a transistor 242.

Since these counters are connected in series, the 100 hertz signal to the first counter 236 is connected to the last counter 240.
generates a 0.1 Hz signal at the output of

This signal corresponds to a time interval of 10 seconds.

In this particular application, the light blink interval is 5 seconds, so the count "0", "5" from the last counter is 5 seconds.
Generates a synchronization signal every second.

The reset lines 244 of these counters are connected to the detector circuit so that these counters are reset when the transmitted pulse train has been sufficiently decoded.

The remaining part of this circuit is combined with the signal decoding process.

When the detector detects the presence of a signal, its output is low (0
Bolt) I want you to remember that.

An inverter 246 at the input of this circuit reverses the polarity of this signal.

The output of inverter 246 goes high when a signal is detected and remains low when no signal is detected.

The first part of this circuit, called the noise closure circuit, includes a set-reset type flip-flop 248.

The sensing signal applies a positive voltage to set terminal 250.

The mutual terminal continues to be low (and the decimal counter 252.2
54 to start counting them.

The input to these counters is a 1 kilohertz square wave.

When the counter finishes counting the decimal number 01 (after one count), the diodes 256 and 258 become reverse biased (not conductive) and a high level voltage is applied to the transistor 2.
Transmitted to 600 base.

The signal is then passed from the emitter of transistor 260 to the rest of the circuit.

This signal (from the emitter of transistor 260) generated each time an input signal is sensed is then processed by the decoding circuit portion.

When counter 252.254 reaches decimal number 99,
Diodes 262, 264 are reverse biased and a high level voltage is transmitted through line 266 to the reset input of flip-flop 24B.

Flip-flop 248 is now reset, allowing the next sense signal to set it.

This circuit performs two functions.

First, any noise (spurious signals) that occurs after the sense signal sets flip-flop 248 is not transmitted to the rest of the decoding circuitry.

Second, this circuit requires 1 before the transmitted signal is received.
00 Mi! Requires that there be a J second quiet period.

If such noise precedes the appropriate signal, the pulse transmitted to the circuit by transistor 260 will reach the decode circuit at an inappropriate time, causing the decode circuit to reset.

The signal from the emitter of transistor 260 is inverted by inverter 270 and subsequently applied to gate 272.

Gates 272 and 274 form a set-reset type flip-flop.

In this application, this flip-flop serves to control the operation of subsequent circuit sections.

A low input to gate 272 sets the flip-flop (
If the output of gate 272 is high and the output of gate 274 is low), then a low input to gate 274 resets the flip-flop (the output of gate 272 is low and the output of gate 274 is high).

The reset state of this flip-flop is the ready state of the circuit.

Decoding begins as soon as the flip-flop is set.

A flip-flop is resettable in one of two states.

First, it resets when decoding is complete.

Second, it resets when one of the transmitted pulses disappears (or is obscured by noise).

The code shown in FIG. 9 transmitted to the receiver circuit consists of nine bursts of a 50 kilohertz signal.

The detection signal consists of nine DC pulses.

Assuming that the flip-flop formed from the two Nant gates 272, 274 is in the reset state, the first signal pulse sets the flip-flop.

(Subsequent pulses have no effect on the set flip-flop.

) When the output of gate 274 goes low, counter 276 can begin counting.

Counter 276 divides the 1 kilohertz input signal down to 100 hertz.

(Counter 276 is used to clock counter 278, allowing only an undefined period of 1 millisecond.

) The 100 Hz signal from counter 276 is stored in memory 28.
It is fed to a binary counter 278 that addresses zero.

A circuit that performs a specific function is provided between the counters 276 and 278.

This circuit adds one clock pulse to the clock pulse train transmitted from counter 276 for reasons explained later.

If the flip-flop formed by gate 272 and gate 274 is in the reset state, the output of gate 272 is low.

This low level voltage is applied to gate 282 to hold the flip-flop formed by gates 282 and 284 in a reset state.

(The output of gate 282 is high and the output of gate 284 is low.

) The counts "7" and "8j of the counter 276 are low respectively when this system is in the reset state.

When the flip-flops of gates 272 and 274 are set by the first pulse of the input code, gates 274
output will be lower.

When the count "7" of counter 276 goes high (after 7 milliseconds), it is communicated through gate 286 to the clock input of counter 278.

When count 8j goes high (1 millisecond later), the output of gate 288 goes low and
The flip-flop formed by 282.284 is set.

Gate 286 is therefore blocked and all subsequent clock pulses to counter 278 must come from the carry output of counter 276.

The carry output of counter 276 changes state at a rate of 100 hertz.

The first flip-flop of binary counter 278 is not used (it generates a 50 hertz signal for the remaining flip-flops).

A 50 hertz time interval is 20 milliseconds.

The remaining flip-flops therefore receive clock pulses every 20 milliseconds.

The flip-flop from Q2 of counter 278 is used to address memory 280.

This memory is programmed with similar code to the memory of the transmitter circuit.

Outputs 1, 2, and 3 of memory 280 are the three types of programmed codes shown in FIG. 9, and output 4 is a service line.

This service line resets the decode circuit when the complete code is read from memory 280.

The next circuit compares the input code to the code stored in receiver memory.

(For proper decoding to occur, the same code must be selected at both transmitter and receiver.

) The first pulse to the flip-flop formed by gates 272, 274 begins decoding.

This pulse (and subsequent pulses) is also applied to one input of gate 290.

Memory 280 output is high (as programmed)
From then on, gate 290 is opened, allowing input pulses to be transmitted towards the trigger input of monostable multivibrator 292.

Counting started at this point.

The output of memory 280 remains low until the next location where a signal pulse occurs.

At this position the output of memory 280 goes high again.

This high level at gate 290 opens gate 290.

The next input pulse (if it occurs) is transmitted to the trigger input of monostable multivibrator 292.

This sequential operation continues through all nine pulses of the code.

Gate 290 functions as an admission window for signal human pulses.

Detection pulses occurring outside this window interval are not transmitted to monostable multivibrator 292.

Here, the characteristics of the closed circuit and the circuit described above are
It is important to understand the reason for adding one clock pulse (one count) to 78.

Please refer to FIG.

A transmission burst from the transmitter is shown as 300.

However, due to diffraction and reflection, the signal 302 that reaches the receiver has large irregularities.

The detector responds only to signals above the set amplitude.

The output of the detector therefore consists of several signal pulses 305.

The closure circuit is responsive to the first pulse 306, followed by a closure pulse.

One of the composite signals from the closed circuit is formed as a pulse 306.

Note that because of this received signal, the detector does not respond to the received signal at its onset.

In fact, the detector can only respond in a small fraction of the received burst.

If the detector output is only of known characteristics, it will exhibit undefined conditions when the signal burst begins and ends.

(The detector only responds at the beginning of the burst, or only at the end of the burst, or only somewhere in the middle of the burst.

) So if the detector responds to a burst with one of its very short output pulses, the burst can start 10 milliseconds before its response, or end 10 milliseconds after its response.

To tolerate the undefined condition associated with the first received burst, the circuit must look for subsequent bursts over 20 milliseconds.

For example, burst 2 is detected at the exact programmed time from burst 1, or 10 milliseconds before the programmed time, or 10 milliseconds after the programmed time.

Additional clock pulses to counter 278 limit the acceptance window to 10
Open before milliseconds.

(One count at a rate of 100 counts/second is 10 milliseconds.

) When the gate 290 is opened and the signal from the detector is transmitted to the gate 290 (the pulse window is open and a pulse is received), the trigger signal is transmitted to the monostable multivibrator 29
2.

The operating time of monostable multivibrator 292 is approximately 30
It's milliseconds.

The output of monostable multivibrator 292 is high when triggered.

This output is inverted by inverter 294 and connected to the clock input of counter 296.

At the end of the trigger time of monostable multivibrator 292, the output of inverter 294 goes high.

This transition clocks counter 296 (counts 1).

If there are 9 pulses per code and each of these pulses triggers a monostable multivibrator, counter 2
96 will have received nine clock pulses by the time it reaches the end of the code.

When the ninth clock pulse is received, counter 29
Count 9 of 6 goes high.

This high level is the counter 236 for the synchronization signal generator.
238.

240 reset terminals, respectively.

A high level applied to the reset terminals of these counters resets them and synchronizes the receiver synchronization pulse generator with the transmitter synchronization pulse generator.

Whether the pulse window is open and no pulses are being received (whether the scheduled pulses are not being received)
Further circuitry is provided for determining.

If monostable multivibrator 292 is triggered by the signal from gate 290 (gate 290
When opened by 80, a pulse is led to the trigger input of monostable multi-bi break 292 1111. ), the output will be low for 30 milliseconds.

A low level to the input of gate 298 shuts off the gate.

However, the monostable multivibrator 292
Unless triggered by a pulse from 0, the output of inverter 294 remains high.

Gate 298 is opened.

Inverter 310 inverts the output of memory 280.

After a window interval of 20 milliseconds, the output of inverter 310 goes high.

This high level is differentiated into short pulses and transmitted to the gate 298.

If gate 298 is open (monostable multipipe rake not triggered), the pulse (inverted) is transmitted from gate 272, 274 to the main control flip-flop formed.

This pulse resets the flip-flop.

Therefore, the device becomes sluggish when a detector pulse is expected and nothing arrives to reset the device.

The device also resets upon completion of the decoding process.

At count 206, memory 280 is programmed to generate an output (positive pulse) at output 4.

This pulse is reversed by inverter 312.

This pulse then becomes a negative pulse suitable for resetting the flip-flop formed from gates 272,274.

The present invention is therefore well suited to carry out the foregoing objects and achieve its advantages and others.

Although the embodiments of this invention have been described for the purpose of explanation, those skilled in the art will readily understand that various modifications and changes can be made to this invention without departing from its spirit and the scope of the claims. There will be.

[Brief explanation of drawings]

FIG. 1 is a perspective view showing a plurality of waterway marker buoys using the wireless marine navigation system of the present invention, and FIG. 2 shows a circuit common to the transmitter and receiver, including a solar switch circuit, a voltage adjustment circuit, and a timing circuit. An electrical block diagram, FIG. 3 is an electrical block diagram of the transmitter circuit, FIG. 4 is an electrical block diagram of the receiver circuit, FIG. 5 is an electrical schematic diagram of the common circuit of FIG. 2, 6 is an electrical schematic diagram of the transmitter circuit of FIG. 3; FIGS. 7A and 7B are electrical schematic diagrams of the clock and sensing circuit of FIG. 4; and FIGS. 8A and 8B are electrical schematic diagrams of the decoder circuit of FIG. An electrical schematic diagram of the circuit, FIG. 9 is a timing diagram for three typical transmission codes, and FIG. 10 is a signal diagram used to illustrate the closed circuit. 10... Radio maritime navigation device, 16...
・・Waterway, 18.28.32.34.46.48...
... Buoy, 20, 40, 54... Transmitter, 22, 26, 36° 38, 50, 52...
- Route lighting, 24,44°58...Sound signal, 3
0, 42, 56...Receiver, 60...
Common circuit, 62...Photosensitive switch, 64...
...Voltage adjustment circuit, 66...Crystal oscillator, 6
8...Transmitter circuit, 70, 82, 84,
94...Digital counter, 76.96...
...Memory circuit, 78...Code selection switch, 80...Receiver circuit, 86...
Amplifier, 88...Detector, 90...Closed circuit, 92...Flip-flop circuit, 98
...Digital comparator, 106, 212, 21
4゜218, 220...Amplifier, 122,
124. 126.128, 162, 164, 166°168.2
36,238,240,252°254.276...
... Decimal counter, 132°170.248...
...Flip-flop, 134°27B...
Binary counter, 136.280...Memory, 1
60... Clock and detector circuit, 172.
186...Voltage follower circuit, 224°226
．． 230, 232... Voltage comparator, 234...
...Detector and synchronous pulse generator circuit, 292.
...Monostable multivibrator, 296...
··counter.

Claims (1)

[Scope of Claims] 1. A marine navigation light system having a transmitter and at least one receiver for controlling the operation of a marine navigation light coupled to a transmitter and a receiver, the system comprising: (5) transmitting. The machine includes a crystal oscillator, a digital counter coupled to the output of the crystal oscillator, and a coded acoustic signal consisting of time-related pulses of less than one second duration. (B) a digital memory connected to the digital counter and receiving an activation signal from the counter;
The receiver includes a crystal oscillator, a first digital counter coupled to the output of the crystal oscillator for providing a timing signal, and a seaway connected to the first digital counter and receiving an actuation signal from the counter. a detector for detecting a coded audio signal from the transmitter; a second digital counter for receiving the coded audio signal; a digital memory having a code memory providing an output equal to the acoustic signal, coupled to the detector and the digital memory, and determining whether the activation code received by the receiver is appropriate and coupled to a first digital counter; and a digital comparator for resetting the first digital counter when the receiver receives a correct signal from the transmitter. 2. Radio maritime navigation device according to claim 1, wherein the code provided by the digital memory of the transmitter and the receiver comprises a plurality of signal pulses with non-uniform spacing from each other. 3. The wireless maritime navigation device according to claim 1, wherein the receiver includes a closed circuit that stops the control of the receiver by the transmitter when the external sound exceeds a predetermined level. 4. A wireless maritime navigation system as claimed in claim 2, including a closed circuit having a member for resetting the receiver when there is no noise between signal pulses.