JPS59216376A - Extracting system of start point of vertical synchronizing signal - Google Patents

Abstract

PURPOSE:To extract a vertical synchronizing signal stably with a high precision by setting a time window about one field after the trailing edge of the just preceding vertical synchronizing signal and defining a point of time, when the level exceeds a threshold in this time window, as the start point of a vertical synchronizing signal. CONSTITUTION:A demodulated television signal 12 is divided into two; and when the trailing edge of a vertical synchronizing signal is detected by an extracting circuit 13 of the trailing edge of the vertical synchronizing signal, a one-field delay circuit 15 counts clocks inputted from a terminal 16 and outputs leading edge information 18 to a DC level clamping circuit 19 and a vertical synchronizing signal start point extracting circuit 21 after the elapse of a one-field time. When leading edge information 18 is inputted, the DC level clamping circuit 19 clamps it to 0V and outputs a clamp output 20. The vertical synchronizing signal start point extracting circuit 21 is set to the holding state when receiving leading edge information 18; and since the time window is set, the circuit 21 outputs a vertical synchronizing signal start point pulse 22 corresponding to a certain number of clocks when the clamp output 20 exceeds the threshold.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a vertical synchronization signal start point extraction method for stably extracting timing information from a television signal, particularly a vertical synchronization signal start point that serves as a time reference for operation in a ghost removal device, etc. Regarding the method.

[Technical background of the invention and its problems] Conventionally, synchronization signal extraction from television signals involves determining the level of the television signal at a certain threshold level that is close to the pedestal level, separating and extracting the composite synchronization signal, and
A commonly used method is to integrate this signal using an integrating circuit and extract the vertical synchronizing signal. However, with this method, if the S/N of the input television signal is poor or the waveform is degraded due to waveform distortion such as ghosting, the composite synchronization signal separation is not performed correctly, and the vertical synchronization signal extracted by integration is There were problems in that accuracy deteriorated and it became impossible to extract the vertical synchronization signal itself.

Figure 1 (a) shows N with good S/'N and little waveform distortion.
The video signal of the TSC video signal and a part of the waveform of the vertical retrace period are shown, and the level of this signal is determined using a level slightly smaller than the pedestal level V1)1 as the threshold level, which is a binary code, that is, a composite synchronization signal separated from synchronization. The signal waveform is shown in the same figure (b), and the waveform obtained by integrating this composite synchronization signal with an appropriate time constant is shown in the same figure (c).
The extracted vertical synchronization signal is shown in the same figure (d).
Shown below. Note that 1 is a horizontal synchronization signal, 2 is a color burst, 3 is a video signal, 4 is an equalization pulse, and 5 is a vertical synchronization signal, and to and tB are the leading edge (starting point) and trailing edge of the vertical synchronization signal. . As shown in FIG. 1(d), in a vertical synchronizing signal extracted by level judgment based on a threshold level, which is an integral signal, its starting point lags behind the starting point of the input television signal, resulting in a decrease in time accuracy.

On the other hand, FIGS. 2(a) and 3(a) show waveforms of a video signal and part of the vertical retrace period when a ghost exists in the input television signal.

Figure 2 (a) shows that the amplitude ratio of the ghost to the main signal is 0.
．． 5. In the case of an in-phase ghost with a delay time of 12 μsec; FIG. 3(a) shows a case where the amplitude ratio of the ghost to the main signal is 0.5 and an anti-phase ghost with a delay time of 12 μsec. If a ghost exists in this way, the pedestal level MDI may fluctuate with respect to the minimum value Vmin of the signal, so even if the level is judged at a certain threshold level, the correct composite synchronization signal may not be extracted. . Here, in Fig. 2 <a> the same phase 1~
If there is, the composite synchronization signal waveform obtained by level judgment will be affected by the ghost as shown in (1) in the same figure, and if this waveform is integrated, it will become the waveform in (C) in the same figure, indicating that a ghost exists. The vertical synchronization signal obtained by level judgment at a certain threshold level is shown in the same figure (d,
), the delay time of the start point of the extracted vertical synchronization signal with respect to the start point of the vertical synchronization signal of the input television signal becomes even larger, and the time accuracy becomes even worse than when Goth 1 ~ does not exist. If there is a ghost with an opposite phase as shown in Figure 3(a), the composite synchronization signal obtained by level judgment at a level lower than the pedestal level will be as shown in Figure 3(b), and the vertical blanking line will be Even the period cannot be detected. Therefore, a vertical synchronizing signal cannot be obtained even if the waveform shown in FIG. 3 (b) is integrated and judged based on a certain threshold level.

This kind of problem is caused by the fact that Goth 1- attempts to judge the level at a constant threshold level despite fluctuations in the DC level, and the waveform whose level is judged at a constant threshold level of the integrated waveform is used as the vertical synchronization signal. There is a reason for this.

[Object of the Invention] An object of the present invention is to extract the starting point of a vertical synchronization signal with high accuracy and stability over a wide operating range even when the waveform of an input television signal is significantly degraded due to noise or distortion such as ghosting. The purpose of this invention is to provide a vertical synchronization signal starting point extraction method.

[Summary of the Invention] The present invention extracts the trailing edge of a vertical synchronizing signal, and measures a time interval of about one field from the trailing edge of the vertical synchronizing signal by, for example, counting locks with high precision and high stability. A time window is set near the leading edge of the vertical sync signal of the field next to the field from which the trailing edge of the vertical sync signal was extracted, and the point at which the input television signal first crosses a certain threshold level within that FR window is set vertically. The feature is that it extracts the synchronization signal starting point.

[Effects of the Invention] According to the present invention, the true vertical synchronization signal starting point can be detected using a time window set based on vertical synchronization signal trailing edge information that can be stably extracted regardless of waveform distortion such as noise, goose, etc. , it is possible to extract the vertical synchronization signal starting point with high precision and stability over a wide operating range without being affected by these waveform distortions.

[Embodiments of the invention] FIG. 4 shows a block diagram of an embodiment of the present invention.

A demodulated television signal 12 is input to the input terminal 11 . In the following explanation, the input television signal will be explained as an NTSC signal, but PAL, SEC
The present invention is also effective for other television signals such as AM. This input television signal 12 is split into two branches, one of which is input to a vertical synchronizing signal trailing edge extraction circuit 13 . In this embodiment, the vertical synchronizing signal trailing edge extraction circuit 13 is the fifth
The configuration is as shown in the figure.

The configuration and operation of this vertical synchronization signal trailing edge detection circuit 13 are explained in the sixth section.
This will be explained using the diagram and FIG. In Figure 6(a), S/
The vertical synchronizing signal (= near J) during the vertical blanking period when N is good and there is no waveform distortion such as ghosting.
a>, the amplitude ratio of the goth l- to the main signal is 0.5,
The waveform near the vertical synchronizing signal during the vertical retrace period when an in-phase ghost with a delay time of 12 μsec is present is shown. In FIG. 5, the input television signal 12 as shown in FIG. 6(a) input from the input terminal 11 is inverted and amplified several times by the inverting amplifier 51 as shown in FIG. 6(1)). , the high-frequency components are suppressed in order to avoid the influence of noise in the subsequent stage, resulting in a waveform as shown in FIG. 6(0). The output of this inverting amplifier 51 is input to an integrator 52. The output of the integrator 52 is compared with a certain threshold level vth lower than the peak value by a comparator 53, and a TTL level signal as shown in FIG. Output i.

The output of the comparator 53 is input to one input terminal of the Nandogoos 1 to 54, and is also input to a low pass filter (LPF) 56 via an inverter 55. The signal input to the LPF 56 is outputted as a waveform as shown in FIG. 6<e> by removing high frequencies with a certain time constant. The output of this LPF 56 is compared with the DC level VS, which is slightly higher than the minimum value Vm of the output of the LPF 56, by the Schmidts 1~1~Riga comparator 57, and becomes the HIT level during the period 11 when the output of the PF 56 is lower than the DC level VS. It becomes a TTL level gate signal as shown in FIG. 6 and is input to the other input of the Nantes gate 54. As a result, Nandogoo 1-54 to Compa Lake 53
A signal 14 (hereinafter referred to as
(referred to as vertical synchronization signal trailing edge information) is output.

By the way, when an anti-phase ghost exists in the input television signal 12 as shown in FIG. 7(a), the energy of the signal decreases, so it is generally not possible to accurately determine the vertically identical signal using only integration and level determination. It becomes impossible to extract. However, according to the configuration shown in FIG. 5, the input television signal 12 in which an anti-phase ghost as shown in FIG.
When this is integrated by the integrator 52 and the level is determined by the comparator 53 at a certain threshold level yth lower than the peak value, the energy of the signal becomes smaller, so the peak value also becomes smaller, and the output of the comparator 53 becomes
As shown in FIG. 7(d), a narrow rectangular wave is placed before a wide rectangular wave. The output of this comparator 53 is given to one input terminal of a Nant gate 54, and is passed through an inverter 55 and an LPF 56 as shown in FIG. 7(e).
The waveform becomes as shown in FIG.
) as a TTL level signal, Nandogoo 1.
54 is input to the other input terminal. At this time, as in the case of FIG. 6, the output of the Nant gate 54 is as shown in FIG.
), the trailing edge of the wide rectangular wave, that is, the trailing edge of the vertical synchronization signal, is shown at the rising point in FIG. Even if there is no goth i,
The vertical synchronization signal trailing edge information 14 can be extracted stably. Furthermore, in the case of an in-phase ghost, since the signal energy does not become small, the vertical synchronization signal trailing edge information 14 can be extracted in the same way as in the case where the ghost does not exist.

The vertical synchronizing signal trailing edge information 14 extracted in this way is input to a one-field delay circuit 15 in FIG. The 1-field delay circuit 15 receives a high-precision, high-stable clock 17 input from the clock input terminal 16 at a time interval of about 1 field from the rising point of the vertical synchronization signal trailing edge information 14.
The leading edge information 18 of the vertical synchronizing signal is outputted for each thread after the elapsed time. This information 18
is applied to the DC level clamp circuit 19 and the vertical synchronization signal start point extraction circuit 21. DC level clamp circuit 1
9 inverts and amplifies the input television signal 12 by slightly suppressing the high frequency amplification factor to avoid the influence of noise, and then clamps the DC level to Ov at the time when the vertical synchronizing signal leading edge information 18 is input. , outputs a clamp output 20. The clamp output 20 is input to a vertical synchronization signal start point extraction circuit 21 at the next stage.

The vertical synchronization signal start point extraction circuit 21 has a configuration as shown in FIG. 8, for example. This configuration will be explained with reference to FIGS. 9 to 11. FIG. 9(a) shows the waveform near the leading edge of the vertical synchronization signal when the input television signal has a good S/N ratio and there is no waveform distortion due to ghosts or the like. This input television signal 12 is inverted and amplified in one DC level clamp circuit with a slight groove in the high frequency range as shown in FIG. At the time of information 18, the DC level is clamped to OV, resulting in a lamp output of 20 as shown in FIG. The Schmitt trigger comparator 81 compares the DC level VOO, which is smaller than OV, with the clamp output 20, and compares it with the clamp output 20 as shown in FIG.
), the portion of the waveform at a level higher than Vco is output and supplied to the next counter circuit 82. The counter circuit 82 changes from a resting state to a standby state by the output 18 of the one-field delay circuit output 15, and sets a time window, and when the output of the comparator 81 is given, the first rising point of the output The circuit starts its operation at 1, and counts the highly stable clock 17 inputted from the clock input terminal 16 in the same way as the 1-field delay circuit 15. The numbers 1 to 1 of the counter circuit 82 are input to the decoder circuit 83 as they are. The decoder circuit 83 outputs to the output end 23 a vertical synchronizing signal starting point pulse 22 having a width corresponding to the opponent's pulse, with the starting point of the counter 82 as the vertical synchronizing signal starting point. That is, after the output 18 of the 1-field delay circuit 15 is generated, the clamp output 20 outputs the vertical synchronizing signal starting point pulse 22 with the rising point at which it first crosses the minute DC level Vco as the vertical synchronizing signal starting point. After outputting the vertical synchronization signal start point pulse 22, the decoder circuit 83 outputs a stop signal 84 to the counter circuit 82, whereby the counter circuit 82 suspends its operation until the next field.

FIGS. 10(a) and 11(a) show waveforms near the leading edge of the vertical synchronization signal when waveform distortion such as ghosting exists in the input television signal 12.

Fig. 10(a) shows a ghost signal with respect to the main signal when there is an in-phase ghost signal with an amplitude ratio of 0.5 and a delay time of 12 μsec. The case where there is an anti-phase ghost with an amplitude ratio of 0.5 and a delay time of 12 μsec is shown. Figure 10 (a,
) even if a ghost exists, the vertical synchronization signal trailing edge information 14 is stably extracted from the input television signal by the vertical synchronization signal trailing edge extraction circuit 13, so that the information shown in FIG. 10 is the same as when no ghost exists. The DC level of the inverted amplified waveform of FIG. 10(b) is clamped by the vertical synchronizing signal leading edge information of (C,), resulting in a waveform as shown in FIG. 10(d). Therefore, the first rising point where this waveform crosses the minute DC level Vco is taken as the starting point of the vertical synchronization signal, as shown in the same figure (e).
The vertical synchronization signal starting point pulse can be extracted.

Further, even when an anti-phase ghost as shown in FIG. 11(a) exists, the vertical synchronizing signal trailing edge information 14 is extracted by the vertical synchronizing signal trailing edge extraction circuit 13. In this way, in the case of this embodiment, unlike the conventional method in which the vertical synchronization signal is extracted after extracting the composite synchronization signal from the input television signal, the method is stable even when there is a negative phase goth 1~. Vertical synchronization signal trailing edge information 14 can be extracted. Therefore, based on the extracted vertical synchronization signal trailing edge information 14, the DC level is clamped with the vertical synchronization signal leading edge information as shown in FIG. 11(C) at a time interval of one field, as shown in FIG. 11(d). From the waveform, the first point that crosses a certain minute DC level Vco can be extracted as the vertical synchronization signal starting point, as in the case where there is no ghost like <e> in the same figure.

As described above, according to the method of the present invention, it is possible to extract a vertical synchronization signal starting point with high accuracy and stability over a wide operating range even in an input television in which noise and waveform distortion such as Goose 1- are present. In addition, if a high-accuracy, high-stability lock is used as in the embodiment, the higher the clock frequency is, the smaller the time interval can be used to set the value to Run 1. Another advantage is that it can be performed with high precision.

[Brief explanation of drawings]

Figures 1 to 3 are signal waveform diagrams for explaining the conventional vertical synchronization signal extraction method, Figure 4 is a configuration diagram of an embodiment of the present invention, and Figure 5 is a diagram showing the vertical synchronization signal output in the same embodiment. A detailed configuration diagram of the edge extraction circuit, FIGS. 6 and 7 are diagrams showing waveforms of each part to explain the operation of this vertical synchronization signal trailing edge extraction circuit, and FIG. 8 is a diagram showing the vertical synchronization signal in the same embodiment. The detailed configuration diagrams of the start point extraction circuit, FIGS. 9 to 11, are diagrams showing waveforms of various parts for explaining the operation of this vertical synchronization signal start point extraction circuit. 11... Television signal input terminal, 13... Vertical synchronizing signal trailing edge extraction circuit, 14... Vertical synchronizing signal trailing edge information, 15... 1 field delay circuit, 16... High precision and high stability Clock input terminal, 18... Vertical synchronization signal leading edge information, 19... DC level clamp circuit, 20...
Clamp output, 21... Vertical synchronization signal start point extraction circuit,
22... Vertical synchronization signal start point pulse. Applicant's agent Patent attorney Takehiko Suzue (9) '' Figure 8 Figure 9 t. ↓

Claims (1)

[Scope of Claims] (1) Means for extracting the trailing edge of the vertical synchronization signal from the incoming horn television signal, and means for setting a predetermined time window after a time interval of about one field from the trailing edge of the vertical synchronization signal. , comprising means for determining the input television signal at a predetermined threshold level, and extracting a time when the input television signal first crosses the threshold level within the time window as a vertical synchronization signal starting point. Vertical synchronization signal start point extraction method. (2) The means for extracting the trailing edge of the vertical synchronization signal is to vertically extract the trailing edge of the vertical synchronization signal by determining the level of the waveform integrated with the input television signal, and resetting the binarized code obtained by using a gate signal that delays the binarized code. The vertical synchronization signal starting point extraction method according to claim 1, characterized in that the extraction is performed as a trailing edge of the synchronization signal. 2. The vertical synchronization signal starting point extraction method according to claim 1, wherein the vertical synchronization signal starting point extraction method measures a time interval of approximately one field by performing the steps of 1 to 1.