JPS59215772A - Multi-emitter type transistor - Google Patents
Multi-emitter type transistorInfo
- Publication number
- JPS59215772A JPS59215772A JP9119383A JP9119383A JPS59215772A JP S59215772 A JPS59215772 A JP S59215772A JP 9119383 A JP9119383 A JP 9119383A JP 9119383 A JP9119383 A JP 9119383A JP S59215772 A JPS59215772 A JP S59215772A
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- base
- region
- electrode
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 abstract description 13
- 229920006395 saturated elastomer Polymers 0.000 abstract description 2
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 6
- 239000000969 carrier Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Abstract
Description
【発明の詳細な説明】
イ、産業上の利用分野
この発明はマルチエミッタ形（メツシュエミッタ形）ト
ランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application This invention relates to a multi-emitter type (mesh emitter type) transistor.
口、従来技術
トランジスタの特性、特にｈｐｇ（直流電流増幅率）特
性やＶ（Ｊ （ＳＡＴ ＞ （飽和状態におけるコレ
クターエミッタ間電圧）特性はエミッタ領域の周囲長を
長くする程良好なものが得られる。そこで一般にトラン
ジスタはエミッタ領域の周囲長をより長くするため各種
の工夫がなされ、その−工夫のトランジスタとしてエミ
ッタ領域を１つのベース領域内の複数箇所゛に分散させ
て複数個形成したマルチエミッタ形トランジスタがある
。The characteristics of conventional transistors, especially the hpg (direct current amplification factor) characteristics and the V(J (SAT > (collector-emitter voltage in saturated state) characteristics), are better as the circumference of the emitter region becomes longer. Therefore, in general, transistors have been devised in various ways to increase the circumference of the emitter region, and as an innovative transistor, a multi-emitter type transistor is formed in which multiple emitter regions are distributed at multiple locations within a single base region. There's a transistor.
第１図乃至第３図にマルチエミッタ形トランジスタの従
来例を示すと、（１）は半導体基板（１”）に例えばＮ
型不純物を拡散して形成したコレクタ領域、（２）はコ
レクタ領域（１）にＰ型不純物の選択拡散で形成したベ
ース領域、（３）＜３）−はベース領域（２）の複数箇
所にＮ型不純物を選択拡散して形成した基盤の目状のマ
ルチエミッタ領域である。（４）は基板（１”）の下面
に形成したコレクタ電極、（５）は基板（１゛）上に選
択的に形成した絶縁膜、（６）及び（７）は基板（１″
）上に選択的に形成したくし形のベース電極及びエミッ
タ電極である。この両電極（６）、（７）は次の要領で
形成される。Figures 1 to 3 show conventional examples of multi-emitter transistors.
Collector region formed by diffusing P-type impurities, (2) is a base region formed by selectively diffusing P-type impurities in collector region (1), (3) < 3 - is at multiple locations in base region (2) This is a multi-emitter region in the shape of a base formed by selectively diffusing N-type impurities. (4) is a collector electrode formed on the bottom surface of the substrate (1''), (5) is an insulating film selectively formed on the substrate (1''), (6) and (7) is a collector electrode formed on the bottom surface of the substrate (1'').
) are selectively formed on the comb-shaped base electrode and emitter electrode. Both electrodes (6) and (7) are formed in the following manner.
先ず基板（１゛）上全面に絶縁膜（５）を形成してから
、この絶縁膜（５）の各エミッタ領域（３）（３）−上
の一部に窓孔（８）（８）−・を、同時にベース領域（
２）上の各エミッタ領域（３）（３）−の近傍に基盤の
目状に窓孔（９）（９）−をＰ、Ｒ法で選択的に形成す
る。First, an insulating film (5) is formed on the entire surface of the substrate (1), and then window holes (8) (8) are formed in a part above each emitter region (3) (3) of this insulating film (5). −・ at the same time as the base area (
2) Window holes (9) (9)-- are selectively formed in the vicinity of each of the upper emitter regions (3) (3)-- in the shape of a grid on the substrate using the P, R method.
次に基！ （１”）上全面に例えばアルミニウム蒸着膜
を形成してから、これをＰＲ法で部分的に除去してくし
形のベース電極（６）とエミッタ電極（７）を形成する
。ベース電極（６）は幅広部（６ｍ）と幅広部（６ｍ）
から横に延びるくし歯状の幅狭部（６ｎ）（６ｎ）−・
−で形成され、幅広部（６ｍ）は外部からアルミニウム
線等の電極引出し用ワイヤ（図示せず）がポンディング
されるポンディングパッドとして利用され、幅狭部（６
ｎ） （６ｎ） −−一−−は前記窓孔（９）（９）
−・を開始ベース領域（２）に電気的接続される。エ
ミッタ電ｆｉ （７）もポンディングパッドとして利用
される幅広部（７ｍ）と、幅広部（７ｍ）から横に延び
て前記各窓孔（８）（８）・−・を介し各エミッタ領域
（３） （３） −に電気的接続されるくし歯状の幅
狭部（７ｎ）（７ｎ）−で形成される。Next is base! For example, an aluminum vapor deposition film is formed on the entire surface of (1"), and then this is partially removed using the PR method to form a comb-shaped base electrode (6) and emitter electrode (7).Base electrode (6) ) are wide part (6m) and wide part (6m)
A comb-shaped narrow part (6n) (6n) extending laterally from
The wide part (6m) is used as a padding pad to which an electrode lead wire (not shown) such as an aluminum wire is bonded from the outside, and the narrow part (6m) is
n) (6n) --1-- is the window hole (9) (9)
- is electrically connected to the starting base region (2). The emitter electric field fi (7) also has a wide part (7 m) used as a bonding pad, and extends horizontally from the wide part (7 m) to each emitter region ( 3) (3) Formed with comb-like narrow parts (7n) (7n)- electrically connected to -.
ところで、トランジスタの特性で重要なものの１つにス
イッチング特性があるが、この特性では、特にオン状態
からオフ状態に変化する際の降下時間Ｔｆが上記マルチ
エミッタ形トランジスタにおいて問題があった、即ち、
エミッタ接地で定常ベース電流ＩＢを与えてオン状態に
した時、各エミッタ領域（３） （３）−・のキャリ
アはベース領域（２）からコレクタ領域（１）へと流れ
、このオン状態から定常ベース電流ＩＢを遮断して逆に
ステップベース電流−ＩＢを与えるとベース領域（２）
内に残留していたキャリアが引き出されるとオフ状態に
なり、このターンオフ時のベース領域（２）内のキャリ
ア流出速度がＴｆを決める。ところがベース領域（２）
の各エミッタ領域（３）（３）−・の中央部真下のキャ
リアが少数キャリアとして残って引出しがどうしても遅
れるｆ頃向にあり、これがＴｆを長くしてスイッチング
特性を悪（する要因になっていた。Incidentally, one of the important characteristics of a transistor is the switching characteristic, and in this characteristic, the above-mentioned multi-emitter transistor has a problem particularly in the fall time Tf when changing from an on state to an off state.
When the emitter is grounded and a steady base current IB is applied to turn it on, carriers in each emitter region (3) (3) flow from the base region (2) to the collector region (1), and from this on state When the base current IB is cut off and the step base current -IB is applied conversely, the base region (2)
When the carriers remaining in the base region (2) are pulled out, it becomes an OFF state, and the carrier outflow speed in the base region (2) at this turn-off time determines Tf. However, the base area (2)
The carriers directly under the center of each emitter region (3) (3)-- remain as minority carriers and are at the point where extraction is inevitably delayed, and this is a factor that lengthens Tf and deteriorates the switching characteristics. Ta.
ハ０発明の目的
本発明は特性の特にスイッチング特性の改善を目的とす
る。OBJECT OF THE INVENTION The present invention aims to improve characteristics, particularly switching characteristics.
二１発明の構成
本発明はマルチエミッタ形トランジスタの各エミッタ領
域内に部分的に非エミッタ領域としてのベースコンタク
ト部を形成すること、及びベースコンタクト部上を含め
てベース電極を形成することを特徴とする。このように
すると特ニスイッチンク特性の］ｆは、上記ベースコン
タクト部のキャリアバイパス効果で向上する。21 Structure of the Invention The present invention is characterized in that a base contact portion as a non-emitter region is formed partially in each emitter region of a multi-emitter transistor, and a base electrode is formed including on the base contact portion. shall be. In this way, the switching characteristic [f] is improved due to the carrier bypass effect of the base contact portion.
また各エミッタ領域内にベースコンタクト部を形成する
ことによりエミッタ領域の合計周囲長が長くなり、ｈＦ
Ｅ特性やＶＣＥ （ＳＡＴ ）特性もより向上させるこ
とができる。Furthermore, by forming a base contact portion in each emitter region, the total circumference of the emitter region becomes longer, and hF
E characteristics and VCE (SAT) characteristics can also be further improved.
ホ、実施例
第１図と同様なマルチエミッタ形トランジスタに本発明
を適用した実施例を第４図乃至第６図から説明すると、
（１０）は半導体基盤（１０′）に例えばＮ型不純物を
拡散して形成したコレクタ領域、（１１）はコレクタ領
域（１０）にＰ型不純物を選択拡散して形成したベース
領域、（１２）（１２） −はベース領域（１１）にＮ
型不純物を選択拡散して形成した基盤の目状の複数のマ
ルチ型エミッタ領域、（１３） （１ｓ）−は各エミ
ッタ領域（１２） （１２）・−の中央部近傍に形成
したベースコンタクト部で、これはエミッタ領域（１２
）（１２） −の形成時に部分的に非エミッタ領域を選
択形成する要領で形成される。この各ベースコンタクト
部（ｉ３） （１３）−はベース領域（１１）に連通
ずる。（１４）は基盤（１０”）の下面に形成したコレ
クタ領域、（１５）は基盤（１０”）の上面に選択的に
形成した絶縁膜、（１６）及び（１７）は基盤（１０°
）上に選択的に形成したくし形のベース電極及びエミッ
タ電極である。ベース電極（１６）はボンディングバン
ドとして用いられる幅広部（１６ｍ）と、幅広部（１６
ｍ）から横に延びてベース領域（１１）上に部分的に電
気的接続されたくし歯状の第１幅狭部（１６ｎ ）（１
６ｎ）−一・と、各第１幅狭部（１６ｎ ） （１６
ｎ ）−から横に枝状に延びて各先端部が各ベースコン
タクト部（１３） （１３）−・上に電気的接続され
た第２幅狭部（１６ｎ’） （１６ｎ’）−を有する
。エミッタ電極（１７）はポンディングパッドとして用
いられる幅広部（１７ｍ）から横に延びて横一列に並ぶ
各列のエミッタ領域（１２） （１２）−上に電気的
接続されたくし歯状の幅狭部（１７ｎ）（１７ｎ ）・
−・とを有する。E. Embodiment An embodiment in which the present invention is applied to a multi-emitter transistor similar to that in FIG. 1 will be explained with reference to FIGS. 4 to 6.
(10) is a collector region formed by, for example, diffusing N-type impurities into the semiconductor substrate (10'), (11) is a base region formed by selectively diffusing P-type impurities into the collector region (10), (12) (12) - is N in the base region (11)
A plurality of eye-shaped multi-type emitter regions of a substrate formed by selectively diffusing type impurities, (13) (1s) - is a base contact portion formed near the center of each emitter region (12) (12). And this is the emitter region (12
)(12) - is formed by partially selectively forming a non-emitter region when forming -. Each base contact portion (i3) (13)- communicates with the base region (11). (14) is a collector region formed on the bottom surface of the substrate (10"), (15) is an insulating film selectively formed on the top surface of the substrate (10"), (16) and (17) are the collector region formed on the bottom surface of the substrate (10"), and (16) and (17) are the collector region formed on the bottom surface of the substrate (10").
) are selectively formed on the comb-shaped base electrode and emitter electrode. The base electrode (16) has a wide part (16 m) used as a bonding band and a wide part (16 m) that is used as a bonding band.
a first narrow part (16n) (16n) extending laterally from the base region (11) and partially electrically connected to the base region (11);
6n) - 1, and each first narrow portion (16n) (16
n )-, each tip part having a second narrow part (16n') (16n')- electrically connected to each base contact part (13) (13)-. . Emitter electrodes (17) extend laterally from a wide part (17 m) used as a bonding pad and are lined up horizontally in each row of emitter regions (12) (12) - comb-shaped narrow strips electrically connected above. Part (17n) (17n)・
- and has.
上記ベース電極（１６）とエミッタ電極（１７）の形成
は従来と同様の工程で行えばよい。例えば先ず第７図に
示すように基盤（１０’ ）上全面に絶縁膜（１５）を
形成してから、絶縁膜（１５）に各エミッタ領域（１２
） （１２）・−・上の一部と、各ベースコンタクト
部（１３） （１３）・−と、ベース領域（１１）上
の横一列で複数列並ぶ複数箇所とが覗く窓孔（１８）
（１Ｂ）−一をＰＲ法で形成する。次ニＭＩＩｆｉ
（１０”）上全面にアルミニウム蒸着膜を形成してから
、これをＰＲ法で選択的に除去して第８図に示す如きパ
ターンのベース電極（１６）とエミッタ電極（１７）を
形成する。The base electrode (16) and the emitter electrode (17) may be formed by the same steps as in the prior art. For example, as shown in FIG. 7, an insulating film (15) is first formed on the entire surface of the substrate (10'), and then each emitter region (12') is formed on the insulating film (15).
) (12)... A window hole (18) through which a part of the top, each base contact part (13) (13)..., and multiple locations lined up in multiple horizontal rows on the base area (11) can be seen.
(1B)-1 is formed by the PR method. Next MIIfi
(10'') After forming an aluminum vapor deposition film on the entire surface, this is selectively removed by the PR method to form a base electrode (16) and an emitter electrode (17) in a pattern as shown in FIG.
上記実施例において、スイッチング特性のＴｆ特性を考
えると、この場合ターンオフ時におけるベース領域（１
１）内の各エミッタ領域（１２）（１２）・・・・真下
の少数キャリアは近くのベースコンタクト部（１３）
（１３）・−からベース電極（１６）に穣極的に引か
れて流出するのでオフ状態に到る時間Ｔｆが短縮され、
スイッチング特性が良好になる。また各エミッタ領域（
１２） （１２）−・・の周囲長だけ従来に比べ長く
でき、これによりｈＦＥ特性、ＶＣＥ （ＳＡＴ ）特
性が向上する。In the above embodiment, considering the Tf characteristic of the switching characteristic, in this case, the base region (1
Each emitter region (12) (12) in 1)...the minority carriers directly below are connected to the nearby base contact part (13)
(13) Since it is attracted to the base electrode (16) and flows out, the time Tf to reach the off state is shortened.
Switching characteristics become better. Also, each emitter area (
12) The peripheral length of (12)-- can be made longer than in the past, thereby improving the hFE characteristics and VCE (SAT) characteristics.
尚、本発明は上記実施例に限らず、例えば図面ではマル
チ形エミッタ領域を矩形にしたが多角形、円形、環形な
どの形状にしてもよく、この形状変更に対応させてベー
スコンタクト部は最適形状に選択される。Note that the present invention is not limited to the above-mentioned embodiments. For example, although the multi-type emitter region is rectangular in the drawings, it may be made into a polygonal, circular, or annular shape, and the base contact portion may be optimally adapted to accommodate this shape change. The shape is selected.
へ０発明の効果
以上の如く、本発明によればマルチエミッタ形トランジ
スタのｈＦｎ特性、ＶＣＥ （ＳＡＴ ）特性、スイ・
２チング特性の改善が容易になり、高性能のトランジス
タが提供できる。Effects of the Invention As described above, the present invention improves the hFn characteristics, VCE (SAT) characteristics, and SW characteristics of multi-emitter transistors.
This makes it easy to improve the switching characteristics, and provides a high-performance transistor.
第１図は従来のマルチエミッタ形トランジスタの一例を
示す平面図、第２図及び第３図は第１図のＡ−Ａ線及び
Ｂ−Ｂ線に沿う断面図、第４図及び第５図は本発明の一
実施例を示す平面図及びＣ−Ｃ線に沿う拡大断面図、第
６図は第５図のＤ−Ｄ線に沿う断面図、第７図及び第８
図は第４図のトランジスタの電極製造過程を説明するた
めの平面図である。
（１１）−ベース領域、（１２） −・エミッタ領域（
１３）・・−・ベースコンタクト部、（１６） 曲ベー
ス電極。
３３
第１圀
３
か２図
か４「■
か５のFIG. 1 is a plan view showing an example of a conventional multi-emitter transistor, FIGS. 2 and 3 are cross-sectional views taken along lines A-A and B-B in FIG. 1, and FIGS. 4 and 5. 6 is a plan view and an enlarged cross-sectional view taken along the line C-C showing an embodiment of the present invention, FIG. 6 is a cross-sectional view taken along the line D-D in FIG. 5, and FIGS.
This figure is a plan view for explaining the electrode manufacturing process of the transistor shown in FIG. 4. (11) - base region, (12) - emitter region (
13)...Base contact part, (16) Curved base electrode. 33 1st area 3 or 2 or 4 "■ or 5"
Claims (1)
したトランジスタにおいて、各々のエミッタ領域内に部
分的に非エミッタ領域としてのベースコンタクト部を形
成すると共に、当該ベースコンタクト部上を含めてベー
ス電極を形成したことを特徴とするマルチエミッタ形ト
ランジスタ。(1) In a transistor in which emitter regions are formed dispersedly at multiple locations in the base region, a base contact portion as a non-emitter region is partially formed in each emitter region, and the base electrode including the top of the base contact portion is formed. A multi-emitter type transistor characterized by forming.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9119383A JPS59215772A (en) | 1983-05-23 | 1983-05-23 | Multi-emitter type transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9119383A JPS59215772A (en) | 1983-05-23 | 1983-05-23 | Multi-emitter type transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59215772A true JPS59215772A (en) | 1984-12-05 |
Family
ID=14019601
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9119383A Pending JPS59215772A (en) | 1983-05-23 | 1983-05-23 | Multi-emitter type transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59215772A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4862253A (en) * | 1988-07-20 | 1989-08-29 | Welch Allyn, Inc. | Apparatus for converting a video processor |
| US5296732A (en) * | 1988-03-02 | 1994-03-22 | Kabushiki Kaisha Tokai Rika Denki Seisakusho | Bipolar transistor |
| US8213676B2 (en) | 2006-12-20 | 2012-07-03 | Ge Inspection Technologies Lp | Inspection apparatus method and apparatus comprising motion responsive control |
| US9621808B2 (en) | 2006-12-20 | 2017-04-11 | General Electric Company | Inspection apparatus method and apparatus comprising selective frame output |
| US10291850B2 (en) | 2006-12-20 | 2019-05-14 | General Electric Company | Inspection apparatus method and apparatus comprising selective frame output |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5190575A (en) * | 1975-02-06 | 1976-08-09 |
-
1983
- 1983-05-23 JP JP9119383A patent/JPS59215772A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5190575A (en) * | 1975-02-06 | 1976-08-09 |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5296732A (en) * | 1988-03-02 | 1994-03-22 | Kabushiki Kaisha Tokai Rika Denki Seisakusho | Bipolar transistor |
| US5594271A (en) * | 1988-03-02 | 1997-01-14 | Kabushiki Kaisha Tokai Rika Denki Seisakusho | Load current detecting device including a multi-emitter bipolar transistor |
| US4862253A (en) * | 1988-07-20 | 1989-08-29 | Welch Allyn, Inc. | Apparatus for converting a video processor |
| US8213676B2 (en) | 2006-12-20 | 2012-07-03 | Ge Inspection Technologies Lp | Inspection apparatus method and apparatus comprising motion responsive control |
| US9621808B2 (en) | 2006-12-20 | 2017-04-11 | General Electric Company | Inspection apparatus method and apparatus comprising selective frame output |
| US10291850B2 (en) | 2006-12-20 | 2019-05-14 | General Electric Company | Inspection apparatus method and apparatus comprising selective frame output |
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