JPS59206962A - Data storage processing device - Google Patents

Abstract

PURPOSE:To eliminate the waiting time of a CPU, by giving a signal indicating the boundary of data to an FIFO (first-in first-out) memory at the time of termination of data writing and utilizing the signal at the time of data reading out. CONSTITUTION:By means of the 1st CPU15 which performs data writing, a boundary signal is given to an FIFO memory 170 at the time of termination of each data writing and the FIFO memory 170 gives the boundary signal to the 2nd CPU16 which performs data readout at the time of termination of each data readout. When such an arrangement is made, the data writing side can write data continuously even though the data are of non-fixed length and the reading out side can discriminate the boundary of data without adding any special circuit. Moreover, the writing and reading out sides can operate independently without retrieving the condition of the other side.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides first-in-first-out (abbreviated as FIF) data that outputs data in the order in which they are input.
The present invention relates to a data storage processing device that performs transfer processing of control data and the like using a memory called O).

A conventional FIFO memory for this type of device is shown in FIG. In the figure, (1) is a data input terminal, (2a) to (2d) are data lines that carry data,
Each of these consists of eight terminals and eight wires. (3a) to (3C) are latch circuits that store 8-bit data in parallel, and (4) is a data output terminal.

In addition, (5a) and (5b) are two-man AND gates, (6
) is a three-person AND gate, (7) is a delay flip-flop circuit that sets the output at the rising edge of the clock (hereinafter referred to as a D flip-flop), (8a) to (8
C) is a set/reset flip-flop circuit (PJ, later referred to as SR flip-flop). (9) is an inverting circuit, 00 is a write terminal that inputs the clock for writing data into the memory, (11) is a write enable display terminal that indicates whether writing is possible, (the function is an initialization signal for the internal circuit) (13 is a readable display terminal that indicates whether the memory contents can be read or not. (14) is a read terminal that inputs a clock for reading the memory contents. The circuit shown in FIG. 1 All the signals handled by the system are digital signals, and an electrical high level is simply referred to as a high level, and an electrical low level is simply referred to as a low level.

In addition, the latch circuits (3a) to (3C) capture data on the data lines (2a) to (2d) at the change point of the strobe signal (hereinafter referred to as STB) from low level to high level, and simultaneously output the data. do. In Figure 1, the left side is the input side,
The right side is the output side, and data is sent from left to right in the diagram. AND gates (5a) (5b) +61 have a logic 1 when both the input and output are at high level.

The D flip-flop (7) enters the set state at the rising edge of the clock (CLK in the figure). The set state is a state in which the output Q is at a high level and the output Q is at a low level, and the reset state is a state in which the output Q is at a low level.

This is a state in which the output q is at a high level. The definitions of set state and reset state are also the same for SR flip-flops (8a) to (8C).

Next, the operation will be explained.

First, before using the FIFO memory 0η, input a pulse signal from the initialization terminal O4, thereby clearing the data stored in the latch circuits (3a) to (3C), and clearing the data stored in the SR flip-flops (8a) to (8C) is set to a reset state. As a result, the writable display terminal 0D
is a high level, a readable display terminal (131 is a low level), a writable display terminal (11J, a high level indicates that writing is possible, a low level indicates that it is not possible to write, and a readable display terminal OJ, a high level indicates that it is readable) , a low level indicates that reading is not possible.

Next, when writing data to the FIFO memory IJ Q7+, input the data 8 to be stored into the data input terminal (1).
After transmitting the bit at high level or low level, the write clock is input to the write terminal fl (11).The D flip-flop (7) is set at the point where the write clock changes from low level to high level. At this time, SR
A because the flip-flop (8a) has been reset.
The ND gate (5a) outputs logic l. At the point where the output of the AND gate (5a) changes from logic 0" to logic 1, the latch circuit (3a) connects the data input terminal (1)
data is taken in through the data line (2a). Also,
The output of the above AND game (5a) is connected to the reset terminal of the D flip-flop (7) and the SR flip-flop (
8a), and at the above change point, the D flip-flop (7) goes into the reset state, and the SR
The flip-flop (8a) becomes set. At this time, the writing-enabled display terminal αυ indicates that writing is not possible.

Also, now that the SR flip-flop (8b) is in the reset state, when the SR flip-flop (8a) is set, both inputs to the AND gate (5b) become logic '1', and the output becomes logic '1'. It becomes ゛. Therefore, the latch circuit (3b) takes in the data on the data line (2b), but at this time, the data on the data line (2b) is input to the data input terminal (1) and is taken in by the latch circuit (3a). This is the data obtained.

The output of the AND game) (5b) is connected to the set terminal of the SR flip 70 tube (8b) and the Sit flip-flop (8b).
It is connected to the reset terminal of the latch circuit (3).
At the same time as b) takes in data, the SR flip-flop (8b) goes into the set state, and the SR flip-flop (8a) goes into the reset state.

When the SR flip-flop (8a) enters the reset state, the writable display terminal (11) indicates writable. In this way, the data input from the data input terminal (1) is taken into the latch circuit (3b).

Furthermore, in the same manner as above, the data of the latch circuit (3b) is transferred to the latch circuit (3C), and the SR flip 7
The 0 tube (8b) is in the reset state and the SR flip-flop (8C) is in the set state. At this time, when the next data is input to the data input terminal (1) and the write clock is input to the write terminal 00, the data is taken into the latch circuit (3b) in the same procedure as above, but the SR
Since the flip-flop (8C) is in the set state, the output of the AND gate (6) remains at logic 0. Therefore, the data sent to the latch circuit (3b) is not transmitted to the latch circuit (3C) as is, and the SR flip-flop (8b) also continues to be set. on the other hand,
Since the Sλ flip-flop (8C) is set, the readable display terminal (13) displays readable.

Next, we will explain the case of reading data from the FIFO memory (1η). When the data is taken into the latch circuit (3C), the data will be output to the data output terminal (4), and the SR flip-flop ( 8C) is set, the readable display terminal (13)
When the display indicates that reading is possible, the reader inputs a read clock from the read terminal side. This read terminal (14) is normally at a low level and is at a high level during readout. When the read terminal (14J) becomes a high level, the SR flip-flop (8c) goes into a reset state, and the read-enabled display terminal (131 indicates that reading is not possible).Subsequently, when the read terminal (141) returns to a low level, the SR flip-flop (8c) (8b) is in the set state and the next data is taken into the latch circuit (3b), all the inputs of the AND gate (6) are in the logic
1", and the output becomes logic "1". Therefore, the latch circuit (3C) receives and receives data from the latch circuit (3b), and at the same time sets the SR flip-flop (8c).
Reset the R flip-flop (8b). In this way, the readable indicator (13) again indicates readable.

Furthermore, when the data is captured in the latch circuit (3a) and the SR flip-flop (8a) is in the set state, the output of the AND gate (5b) becomes a logic
1, and the data in the latch circuit (3a) is transferred to the latch circuit (3b). In this way, when all three internal SR flip-flops (8a) to (80) are in the reset state, the readable display terminal 03I remains stable while displaying readable.

In this way, when reading data in the FIFO memory αη, by changing the read terminal 0 from high level to low level, the data is read out in the order in which it was written.

Conventional FIFO memory was configured as described above, so on the data writing side or the data reading side,
It was only informed whether it was writable or readable.

For this reason, for example, in the processing device B shown in FIG.
is a FIFO memory having the configuration described above as the conventional example.

Now, arithmetic processing unit A (from 1ω, arithmetic processing unit B06
), data of variable length (hereinafter referred to as non-fixed length data) is sent. Arithmetic processing unit A (15) writes data while searching for writable display terminal 01), and arithmetic processing unit B (161) cannot know when the data ends because it has a readable display terminal. The readable display terminal 09 is an SR flip-flop (
8C) is in the set state, and also always indicates that reading is not possible when the read terminal side becomes high level. Just because it is displayed, it cannot be determined that the contents of the FIFO memory 1171 are empty.

Also, if you try to send multiple blocks of non-fixed length data, that is, certain data whose length is not constant, from the arithmetic processing unit 'A Q51 to the arithmetic processing unit B (161), the block After writing the previous block to the FIFO memory (171) to indicate the boundary of It becomes necessary, and the arithmetic processing unit A,
The usage efficiency of B (151f16) was reduced.

The present invention was made in order to eliminate the drawbacks of the conventional ones as described above, and includes a FIFO memory and a first memory for writing and reading data to and from the FIFO memory. a second central processing unit, the first central processing unit applies a boundary signal indicating a boundary between each data and the next data to the memory at the end of writing each data; By applying the boundary signal to the second central processing unit at the end of reading each data, the first . It is an object of the present invention to provide a data storage/processing device that can eliminate the need for waiting time for a second central processing unit, thereby greatly improving usage efficiency.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 shows a data storage processing device according to an embodiment of the present invention, and FIG. 3 shows its FIFO memory (170).

In Fig. 3, (1) to (]41 are exactly the same as the conventional one shown in Fig. 1. (18) is a boundary input terminal into which a boundary signal indicating a data boundary is input, and 0ω is an input terminal. D flip-flops (20a) to (20C) are S flip-flops that become set when the clock changes from low level to high level.
R flip-flops, (21a) to (21C) are AND
gate, ■ is the boundary output terminal that outputs the boundary signal, (c)
is an AND gate.

In FIG. 4, Q51 is the FIFO memory (1
70), a first central processing unit that writes data and inputs boundary signals; (IF5 is a FIFO memory (1
70).

Next, the operation of the device of this embodiment will be explained.

The latch circuit (3a) ~ until the data input to the data input terminal (1) is transmitted to the data output terminal (4)
(3c), AND gate (5a) (5b) (61,D
-y IJ The operations of the tube flop (7) and the SR flip-flops (8a) to (8C) are exactly the same as in the conventional case. Furthermore, the operations of the write terminal (1e), the readable display terminal (1 (to)), and the read terminal Oa are completely the same as those of the conventional device.

FIFO memo IJ (1
70), a boundary signal that changes from low level to high level and returns to low level is input to the first central processing unit (formerly known as boundary input terminal (181). Then, the D flip-flop +191 This pulse (
The set state is reached at the point where the boundary signal) changes from low level to high level. This subsequently creates an SR flip-flop (
20a) is set, the D flip-flop α
(G) enters the reset state, and the output of the AND gate (21 becomes logic O), which causes the writable display terminal (1
1) indicates that writing is not possible. Note that the state in which the signal input from the boundary input terminal (18) sets the SR flip-flop (20a) in this manner will be referred to as a boundary mark state.

Subsequently, when the Sk flip-flop (8a) enters the reset state in the write-disabled state, that is, when the contents of the latch circuit (3a) are transmitted to the latch circuit (3b), the AND gate (21a) 02 becomes the logic state.゛1
', and its output becomes logic 1°. This allows S
The R flip-flop (20b) is in the set state, the SR flip-flop (20a) is in the reset state, and the boundary mark state is transferred from the SR flip-flop (20a) to (20b).

At the same time, both the AND gates are connected to the logic display terminal (111) indicating that writing is possible.At this time, even if the next data is written, the data reading side
That is, in the second central processing unit t (161), it is possible to distinguish the data from the previous data by the boundary signal.The boundary mark state transmitted to the SR flip-flop (20b) is
In the same way, the information is transmitted to the SR flip-flop (20C), and when the SR flip-flop (8C) is in the reset state, that is, when all the data up to the data break intended by the writing side has been read, the second central processing Equipment (1
As for ω, a pulse signal, that is, a boundary signal can be obtained from the boundary output terminal @.

Furthermore, when the writing of the last data to the FIFO memory (170) is completed, the first central processing unit (151) sends a data end signal indicating the end of data to the memory (170).
), and the data end signal is applied to the memory (170).
is given to the second central processing unit αe at the end of reading the last data, and as a result, the second central processing unit (
16) can know the end of data.

In the above embodiment, the FIFO memory capacity was set to three latch circuits (3a) to (3c), but this capacity may be set to any number of latch circuits. In addition, the data input terminal (
The number of months, data output terminals (4), and data terminals is not limited to eight, but may be any number. Furthermore, the boundary signal indicating the data boundary may be input any number of times, that is, a plurality of boundary mark states may exist within the apparatus of this embodiment at the same time.

As described above, according to the present invention, the first central processing unit that performs data writing gives the boundary signal to the FIFO memory at the end of writing each data, and the vFIFO memory sends the boundary signal to the FIFO memory at the end of reading each data. Since the data is fed to the second central processing unit that performs reading, the data writing side can continuously write even non-fixed length data, and the reading side can also write data without adding any other special circuit. Being able to know the boundaries
Therefore, during data transfer, the writing side and reading side can operate independently without mutually searching the circuit status of the other device, which has the effect of greatly improving the usage efficiency of the device.

[Brief explanation of drawings]

Figure 1 shows the conventional (y) First -In -Fir
A configuration diagram of the st-0ut memory, FIG. 2 is a configuration diagram showing an example of use when using the above-mentioned conventional FIFO memory,
FIG. 3 is a block diagram of a FIFO memory of a data storage processing apparatus according to an embodiment of the present invention, and FIG. 4 is a block diagram of the apparatus of the above embodiment. 115)...first central processing unit, f16)...second
Central processing unit, (170)...FIFO memory. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa

Claims (1)

[Claims] (1) A data storage comprising a memory that outputs data in the order in which it is written, a first central processing unit that writes data to the memory, and a second central processing unit that reads data from the memory. In the processing device, the first central processing unit provides the memory with a boundary signal indicating a boundary between the data and the next data following each data upon completion of writing of each data to be stored in the memory; A data storage processing device characterized in that said memory provides said boundary signal to said second central processing unit following said data when said second central processing unit finishes reading each data from said memory.