JPS59202550A - Debugging device - Google Patents

Abstract

PURPOSE:To improve the debugging efficiency by breaking the processor of an active machine prior to the execution of instruction of an address detected as a break point. CONSTITUTION:A bit map memory 5 is brought into the write state prior to the execution of break to clear this memory 5 into zero. Then, a prescribed value of data (e.g., 1) is written in an address of the memory 5 corresponding to the address desired to be subject to break in a program memory 22 via an address bus 13 and a data bus 14 of a processor 2 according to the command of the debugging operator. Then, when an active machine 20 runs, the memory 5 is addressed by a value on the address bus 24 and its read output is applied to one terminal of an AND gate 11. Since a fetch timing signal is applied from a circuit 9 to the other terminal of the AND gate 11, a processor 21 is subject to break only when an output of the memory 5 is at level ''1''.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to a debugging device that is connected to a device equipped with a processor, that is, an actual device, and debugs the program of this actual device. This invention relates to a debugging device which stops the operation of a processor, ie breaks, before executing an instruction at an Indian instruction address.

(Background of the invention) Debugging is the process of repeatedly running and stopping the program being debugged, and removing bugs in the program by referring to the contents of memory and registers at the point of stop, and by changing these contents. . During this time, changes to the program itself called patches are also involved. Since debugging is generally a task like this, the debugging device must have a function to break the execution of the program. A break occurs when a certain event occurs, and events can be broadly divided into (1) when a certain program is executed, and (2) when certain data is referenced. The debugging device of the present invention executes the break used in this case (2).

Furthermore, a problem with breaks is the timing at which they actually stop. There are three timing cases:

8. Stop B immediately before execution of a designated instruction, C stop immediately after execution of a designated instruction, and other stop cases A to C that do not occur at regular intervals pose no particular problem if the debug operator directly recognizes them and uses them over and over again.

However, when executing a break in high-level language debugging, a break in changing the program execution order, displaying memory, etc. without using an operator, B
A break mechanism of this type is required.

By the way, in the conventional hardware-based break method, when breakpoints 1 to 1 are detected, a break is performed using a ``ntf-]-alt'' signal such as NMi interrupt-ul-1alt. there was. In this case, the halt generally occurs after the instruction at the specified instruction address is executed. This suspension after execution is difficult to use when changing the program execution order or as a break method used in high-level language debuggers.

(Object of the Invention) The present invention has been made in view of the above-mentioned problem in the conventional form,
In a debugging device, the purpose is to set breakpoints 1 to 1 and cause an actual break to occur before execution of the instruction at the detected address.

(Structure and Effects of the Invention) The present invention provides a debugging device that is connected to an actual machine and performs program debugging, which includes a processor and a program memory storing a control program for the processor.1. When the data of the predetermined value (1n) is read out from the map memory from the pin 1 to the map memory using a hit map memory which stores data of a predetermined value in a bit corresponding to the address to be broken and a trap instruction code setter, a trap instruction code setter is used. Before executing the instruction at the break address, the output of the program memory is prohibited in synchronization with the instruction timing of the processor, and the trap instruction code 1 to the setter is sent to the data bus of the actual machine. This invention is based on the concept of executing a break when the specified program is executed.According to the present invention, program execution is stopped exactly before the specified program is executed, so it can be effectively used when changing the execution sequence. Even in cases where a set of machine words is made into a single sentence, such as in a language, it is possible to accurately stop at a sentence break.Furthermore, since the state before execution is clear, debugging can be performed efficiently. be able to.

(Explanation of Examples) Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 schematically shows a debugging device according to an embodiment of the present invention. The debug device 1 in the figure is a processor (CPU)
2>2, multiplexer 4, pin-map memory 5,
It is provided with a trap instruction code 1 to a setter 6, a group 1 circuit 7, an inverter 8, a timing control circuit 9, a control circuit 10, an AND gate 11, and the like. A real device 20 that executes a program to be debugged includes a processor (CPUI) 21 and a program memory 22 in which a control program for the processor 21 is stored. Processor 21 and memory 22 are connected to control bus 2
3, a system bus including an address bus 24 and a data bus 25. The address bus 24 of the real 1fi 20 is connected to the multiplexer 4 of the debug device 1. In addition, the control bus 2 of the actual machine 20
3 is the output of the timing control circuit 9 of the debugging device 1, and the output of the gate circuit 7 of the debugging device 1 is actually 1.
20 data buses 25.

The bitmap memory 5 is a memory that stores the number of bits corresponding to the address space of the program memory 22 of 20. For example, if the program memory 22 has a capacity of 64 bytes, the bitmap memory 5 has a capacity of 64 bytes.
has a capacity of .

The multiplexer 4 is used to switch and connect either the address bus 24 of the actual device 20 or the address bus 13 of the debugging device 1 to the address input of the bitmap memory 5. Timing control circuit 9 is the actual controller 1
~〇- Generates a fetch timing signal synchronized with the instruction fetch signal on the bus 23.

Next, the operation of the debugging device shown in FIG. 1 will be explained with reference to the flowchart shown in FIG.

In the circuit of FIG. 1, the multiplexer 4 of the debugging device 1 is connected to the processor
The address bus 13 of the bitmap memory 5 is switched to be connected to the address input of the bitmap memory 5, and a write signal W is applied from the control circuit 10 to the bitmap memory 5 to put the bitmap memory 5 into a write state. Then, while addressing all the addresses of the bitmap memory 5 by the address of the processor 2, the data path controller 1
Apply the input signal I N = ``O'' from 1) to clear the memory 5, and then (2) follow the instructions of the debug operator to clear the program memory 22 from the address bus 13 and data bus 14 of the processor 2. A predetermined value of f is written to the address of the bitmap memory 5 corresponding to the address at which the break is desired (3). As the predetermined value data, for example, 1'' is written to the address corresponding to the address where the break is desired.

In this way, when the data of the predetermined value of C is written to all the addresses of the instruction to cause a break in the bitmap memory 5, the processor
After applying a read signal instead of a write signal via the bitmap memory 5 to the read state, and setting the multiplexer 4 to connect the address bus 24 of the entity 20 and the address input of the bitmap memory 5. , gives a run signal to the processor 21 of the real 1m20, and causes the real 1m20 to execute the program (4).

At this time, data according to the program appears on the control bus 23, address bus 24, and data bus 25 from the 20 processors 21 (5).The address data input to the memory 22 on the address bus 24 is It is applied via the multiplexer 4 to the address input of the C bitmap memory 5, so that the bitmap memory 5 is addressed by this address data and its successive outputs are applied to one of the AND gates 11 via the terminal OUT. Applied to the input (6).Andoo 1~
Since the fetch timing signal from the timing control circuit 9 is applied to the other input of 11, when the output of the bitmap memory 5 is at a position indicating a break point, that is, at level "1" (7), the above fetch timing signal is applied. At the timing of , the output of the AND gate 11 becomes level "1". As a result, the use of the program memory 22 is prohibited via the inverter 8, the gate circuit 7 is turned on, and the trap instruction code set in the trap instruction setter 6 is changed to the actual f! 20 data bus 25 (8), ] No. 21 executes this trap instruction and breaks (9).

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a general configuration of a debugging device according to an embodiment of the present invention, and FIG. 2 is a diagram 70-112 for explaining the operation of the debugging device shown in FIG. DESCRIPTION OF SYMBOLS 1...Debug device, 2...Processor,...Pi 1~Map memory, 6...Trap instruction go 1: Setting device, 20...Actual machine, 21...Processor, 22...
...Program memo 1c23-...Control bus,
24...address bus, 25...data bus. Patent applicant Tateishi Electric Co., Ltd. Agent Patent attorney Tatsuo Ito Agent Patent attorney Tetsuya Ito

Claims (1)

[Claims] 1.10 Program debugging by extracting address signals, data signals, and controller 1 to roll signals from the system bus or read terminal of the processor of the actual machine equipped with a 1-gram memory that stores the control program of the controller. The debugging device is a debugging device that stores data of predetermined values in bits corresponding to the address space of the program memory and corresponding to addresses to be broken, and a trap instruction code. and a trap instruction code setter that generates a trap instruction code setter, and by operating the actual machine, the bitmap memory is accessed in response to an address signal that accesses the program memory, and the predetermined value is read from the pin 1 to map memory. When the data is read, the output of the program memory is prohibited at +1JI (, which is the same as the instruction fetch timing of the processor), and a break operation is performed by sending a 1~lap instruction code to the data bus of the actual machine. A debug device characterized by: