JPS59184561A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable to ensure the withstand voltage of a peripheral circuit while contriving to increase the read-out voltage by alleviating the floating capacitance CB of a bit line by making the impurity concentrations of the channel stopper layers of the bit line part and the peripheral circuit part different from each other. CONSTITUTION:Regarding the peripheral circuit part 13 of a semiconductor memory chip 12, the amount of ion implantation to form a channel stopper layer is increased as conventional. While, regarding a bit line part 14, the amount of ion implantation to form the channel stopper layer is reduced. This method enables to increase the read-out voltage of the bit line while maintaining the withstand voltage of the peripheral circuit in a large amount.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor memory device, and particularly relates to an improvement in which a large read voltage can be obtained while maintaining a high breakdown voltage in a peripheral circuit section.

[Prior art]

Figure 1 shows a semiconductor Rand that has been commonly used.
o: Equivalent circuit diagram of basic memory cell of Access MWry (RAM), fi+ is field effect transistor (FET), (21 is one electrode is FF, T(1)
The memory capacitor is connected to the source of FET and the other electrode is connected to the reference potential point (3), (4) is the bit line to which the drain of FETfl is connected, and (5) is the word line to which the gate of ygT (11 is connected). It is a line.Reference potential point (3)
is held at power supply potential or ground potential.

In this circuit, if the capacitance of the bit line (4) is CB1 and the capacitance of the memory capacitor (2) is Cs, then when the word line (6) is selected and the FET (11 is conductive), the bit line (4)
The amount of potential change is proportional to C8/. In a semiconductor memory device, potential changes on the bit line (4) must be detected with good reproducibility even if there are variations in characteristics between cells and electrical noise. Therefore, making the amount of potential change read to the bit line (4) as large as possible is a basic requirement for realizing a semiconductor memory device that is resistant to variations in characteristics and has stable operation. There are two ways to increase this read 1 potential: reducing the capacitance CB of the bit line (4) or increasing the capacitance C8 of the memory capacitor (2). However, since there are restrictions on chip size, a method of reducing the bit line capacitance CR is practical.

FIG. 2 is a sectional view showing a bit a portion of a general semiconductor memory cell using a diffusion bit line method, and shows a case where an n-channel MO6) transistor is used. In the figure, (6) is a p-type semiconductor substrate with a low impurity concentration, (7) is an oxide film for element isolation, (8) is a bit line formed by diffusing n-type impurities, and (9) is an oxide film. An inversion layer is formed under the film (7) to prevent conduction between elements.
Channel stopper layer implanted with a high concentration of type impurities (
10) is a wiring, and (11) is an interlayer insulating layer.

The stray capacitance CE of the bit line (8) consists of three components. That is, the capacitance C□ between the wiring (10) and the substrate (6
) and the junction capacitance C2 between the chimanel stopper layer (
It is known that among these components, the junction capacitance C3 between the channel stopper layer (9) and the channel stopper layer (9) is the largest. Generally, the width W of the depletion layer formed at the pn junction is expressed as: Here, ε8 is the dielectric constant of silicon, q is the elementary charge, NA and ND are the concentrations of the p-type impurity and n-type impurity, respectively, and vbi is the built-in potential. N,
〉〉NA and since the junction capacitance is inversely proportional to the width W of the depletion layer, the junction capacitance C3 is the channel stopper layer (9)
It can be seen that it is proportional to the A power of the impurity concentration.

However, in conventional semiconductor memory devices, the impurity concentration of the channel stopper layer is applied to the entire chip, which is determined by standards that guarantee the withstand voltage of the parts to which high voltage is applied in the peripheral circuitry formed within the same semiconductor chip. Therefore, the impurity concentration of the channel stopper layer is unnecessarily high for the bit line part to which a very high voltage is not applied, and the stray capacitance CB of the bit line (8) increases, causing the read voltage from the bit line (8) to increase. had the disadvantage of being small.

[Summary of the invention]

This invention was made in view of the above points, and by making the impurity concentrations of the channel stopper layers of the bit line section and the peripheral circuit section different from each other, the stray capacitance CB of the bit line is reduced and the readout is improved. The present invention provides a semiconductor memory device that can guarantee the withstand voltage of the peripheral circuitry while increasing the voltage.

[Embodiments of the invention]

FIG. 3 is a plan view showing an embodiment of the present invention. (1
2) is a semiconductor memory chip, (13) is its peripheral circuit section, and (14) is a bit line section. In this embodiment, the amount of ion implantation for forming the stopper layer in the channel for the peripheral circuit area (la) was increased as before, and the bit line area (la) was increased as before.
Regarding I4), the amount of ion implantation for forming the channel stopper layer is reduced. By doing this, it is possible to increase the read voltage of the bit line while maintaining a high breakdown voltage of the peripheral circuit. The manufacturing process for this requires only one additional photomask.

The case of an n-channel MOS device using a p-type substrate has been explained above, but a p-channel MOS device using an n-type substrate has been described.
The present invention can be similarly applied to both OS devices and complementary MOS devices.

〔Effect of the invention〕

As explained above, in the semiconductor memory device of the present invention, the amount of ion implantation for forming the channel stopper layer is small in the bit line part and large in the peripheral circuit part, so that the readout can be performed while keeping the withstand voltage high. By increasing the voltage, it is possible to read information stably even when there are variations in characteristics and external noise.

[Brief explanation of drawings]

FIG. 1 is an equivalent circuit diagram of a basic memory cell commonly used in the past, FIG. 2 is a cross-sectional view showing the bit line portion of a diffused bit line method of a general semiconductor memory cell, and FIG. FIG. 2 is a plan view showing an example. In the figure, (6) is a semiconductor substrate (first conductivity type), (7
) is an oxide film, (8) is a second conductivity type region (bit line), (
9) is a channel stopper layer, (12'l is a semiconductor memory chip, (13) is a peripheral circuit section, and (14) is a bit line section. In addition, the same reference numerals in the figure indicate the same or equivalent parts. Person Masuo Oiwa (7) Figure 1 Figure 8

Claims (1)

[Claims] +11 A semiconductor substrate of a first conductivity type, a plurality of memory elements each having a plurality of second conductivity type regions selectively formed on a surface portion of the semiconductor substrate as bit lines, and a plurality of memory elements formed on the semiconductor substrate. a bit line portion having an oxide film separating the memory elements; and a channel stopper layer formed under the oxide film so as to be in contact with the bit line and having a first conductivity type impurity concentration higher than that of the semiconductor substrate; In addition, in the semiconductor substrate including a peripheral circuit section formed in a portion other than the bit line section, the impurity concentration of the channel stopper layer of the bit line section is set as the impurity concentration of the channel stopper layer formed in the peripheral circuit section. A semiconductor memory device characterized by having a density smaller than that of a semiconductor memory device.