JPS59169177A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59169177A JPS59169177A JP4347183A JP4347183A JPS59169177A JP S59169177 A JPS59169177 A JP S59169177A JP 4347183 A JP4347183 A JP 4347183A JP 4347183 A JP4347183 A JP 4347183A JP S59169177 A JPS59169177 A JP S59169177A
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- noise
- polycrystalline silicon
- type
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 17
- 239000012535 impurity Substances 0.000 abstract description 5
- 238000005215 recombination Methods 0.000 abstract description 5
- 230000006798 recombination Effects 0.000 abstract description 5
- 238000011109 contamination Methods 0.000 abstract description 2
- 150000004767 nitrides Chemical class 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 不発明は半導体装置Ｖこ関する。[Detailed description of the invention] The invention relates to a semiconductor device V.
従来、プレーナ形バイポーラトランジスタは基板表面の
酸化膜を選択的にエツチングして不純物全拡散していた
。しかるに、トランジスタの高速化、高集積化の要求か
ら窒化膜をマスクＶＣした選択酸化やポリシリコンを利
用したトランジスタの形成が行なわれている。Conventionally, in planar bipolar transistors, impurities were completely diffused by selectively etching the oxide film on the substrate surface. However, in response to demands for higher speed and higher integration of transistors, selective oxidation using a nitride film as a mask VC and the formation of transistors using polysilicon are being carried out.
第１図に従来のトランジスタの構造断面図を示す。ｌは
Ｐ形シリコン基板、２はｔｉｌｉｌｊｋ度ｉＱ形埋込層
、３はＮ形エピタキシャル層、４はフィールド酸化膜、
５はＰ形ベース領域、６はＮ形エミッタ領域、７はＰ形
多結晶シリコン領域、ＢｆｌＮ形多結晶シリコン領域、
９は多結晶シリコン酸化膜、１０はベースアルミ電極、
１１はエミッタアルミ電極をそれぞれ示す。第１図の構
造のトランジスタは素子の周囲を酸化膜で囲まれている
ため、寄生容量が小さく高周波デジタル動作に適してい
る。FIG. 1 shows a cross-sectional view of the structure of a conventional transistor. 1 is a P-type silicon substrate, 2 is a tililjk iQ-type buried layer, 3 is an N-type epitaxial layer, 4 is a field oxide film,
5 is a P-type base region, 6 is an N-type emitter region, 7 is a P-type polycrystalline silicon region, BflN-type polycrystalline silicon region,
9 is a polycrystalline silicon oxide film, 10 is a base aluminum electrode,
Reference numeral 11 indicates an emitter aluminum electrode. Since the transistor having the structure shown in FIG. 1 is surrounded by an oxide film, the parasitic capacitance is small and it is suitable for high-frequency digital operation.
一方、近年デジタル信号処理とともにアナログ信号処理
をワンチップ集積回路で同時に行なう要求が強まってい
る。この場合、トランジスタの雑音特性が、特にアナロ
グ信号処理で問題になる。On the other hand, in recent years there has been an increasing demand for simultaneously performing analog signal processing as well as digital signal processing on a single-chip integrated circuit. In this case, the noise characteristics of the transistor become a problem, especially in analog signal processing.
第１図の構造のトランジスタ”の場合、ベースエミ、り
接合は、厚い酸化膜に接しているため、歪音うけており
、ベース−エミッタ接合孕乏内でのキャリヤの発生、再
結合に起因する雑音が大きく実用上問題がある。In the case of the transistor with the structure shown in Figure 1, the base-emitter junction is in contact with a thick oxide film, so it receives distorted noise, which is caused by the generation and recombination of carriers within the base-emitter junction. The noise is large and poses a practical problem.
本発明の目的は、かかるトランジスタの欠点を解決し、
雑音の小さくなる構造全提供することりこある。The object of the invention is to overcome the drawbacks of such transistors,
The entire structure provides reduced noise.
かかる目的全達成するために、不発明は、トランジスタ
のエミッタベース接合をエミッタ多結晶シリコン電極で
おおった構造全特徴とするものである。To achieve all of these objects, the invention features a structure in which the emitter-base junction of the transistor is covered with an emitter polycrystalline silicon electrode.
以下、実施例すこもとづき、本発明の詳細な説明する。Hereinafter, the present invention will be described in detail with reference to Examples.
第２図は本発明の一実施例である。１は比抵抗１０〜５
０ΩｃｍのＰ形シリコン基板、２ｉ−を層抵抗１０〜５
０Ω／口の高濃度埋込層、３は比抵抗１０ｃｍのＮ形エ
ピタキシャル層、４は厚さ約１．３μのフィールド酸化
膜、５はＰ形ベース領域、６はＮ形エミッタ領域、７は
Ｐ形多結晶シリコン層で厚さは約０．５μ、 ８はＮ形
多結晶シリコン層、１９は多結晶シリコン酸化膜、１０
はベースアルミ電極、１１はエミッタアルミ電極、１２
は窒化膜のパッド酸化膜で厚さは約５０ＯＡ、１３は厚
さ０，１μの窒化膜をそれぞれ示す。FIG. 2 shows an embodiment of the present invention. 1 is specific resistance 10-5
0Ωcm P type silicon substrate, 2i- layer resistance 10~5
3 is an N-type epitaxial layer with a specific resistance of 10 cm, 4 is a field oxide film with a thickness of about 1.3 μm, 5 is a P-type base region, 6 is an N-type emitter region, 7 is a high concentration buried layer of 0 Ω/hole. 8 is an N-type polycrystalline silicon layer, 19 is a polycrystalline silicon oxide film, and 10 is a P-type polycrystalline silicon layer with a thickness of approximately 0.5μ.
is the base aluminum electrode, 11 is the emitter aluminum electrode, 12
1 is a nitride pad oxide film with a thickness of about 50 OA, and 13 is a nitride film with a thickness of 0 and 1 μm, respectively.
第２図において、エミッタ、ベース接合は窒化膜１３で
おおわれており、キャリヤの発生再結合の原因となる外
部からの汚染を防ぐことができる。In FIG. 2, the emitter and base junctions are covered with a nitride film 13, which can prevent contamination from the outside that causes generation and recombination of carriers.
しかもこの窒化膜１３は、４のフィールド緻化膜１゜
全形成するための窒化膜を残せばよく、特にこのための
工程全必要としない。さらに、この窒化膜１３の上ｒこ
は、エミッタ不純物拡散源となるＮ形多結晶シリコン８
が電極として存在し、この多結晶シリコン８（ｌ″ｊ常
ＶＣペース５ ＶＣ対して負の電位が与えられており、
エミッタ、ベース接合空乏層のひろがり全おさえる働き
をする。このため、キャリヤの発生、再結合が小きくで
き、このため、雑音、特にいわゆる１／ｆ雑音を小さく
できる。また、上記窒化膜１３及び、エミッタ接合をお
おう多結晶シリコン８は同時に電流利得ｈＦＥ を上
げる効果も同時に生じる。Moreover, this nitride film 13 only needs to leave the nitride film for completely forming the field densified film 1° of No. 4, and no particular process is required for this purpose. Further, on the upper surface of this nitride film 13, an N-type polycrystalline silicon 8 which becomes an emitter impurity diffusion source is formed.
exists as an electrode, and a negative potential is given to this polycrystalline silicon 8 (l''j normal VC pace 5 VC,
It works to suppress the expansion of the emitter and base junction depletion layers. Therefore, generation and recombination of carriers can be reduced, and therefore noise, especially so-called 1/f noise, can be reduced. Further, the nitride film 13 and the polycrystalline silicon 8 covering the emitter junction simultaneously have the effect of increasing the current gain hFE.
以上説明したように、不発明ＶＣよれば、窒化膜を用い
た選択酸化技術と多結晶シリコンを用いた不純物拡散技
術において、特に工程を追加することなく、選択酸化に
用いた窒化膜１３’！ｌｉ−一部残して多結晶シリコン
８葡成長させ、この多結晶シリコン８中の不純物を単結
晶シリコン中に拡散させてエミッタ６を形成する時、エ
ミッタベース接合金おおうようＶこ多結晶シリコンエミ
、り電極を形成することによってＮＰＮ）ランジスタの
雑音を改善することができ、アナログ半導体集積回絡め
低雑音化に及ぼす効果は著しいものがある。As explained above, according to the uninvented VC, the nitride film 13' used for selective oxidation can be used without any additional process in the selective oxidation technology using a nitride film and the impurity diffusion technology using polycrystalline silicon! When forming the emitter 6 by growing polycrystalline silicon 8, leaving a portion of the li-li, and diffusing the impurities in the polycrystalline silicon 8 into the single crystal silicon, the polycrystalline silicon emitter is grown to cover the emitter base junction gold. By forming the electrodes, the noise of the NPN transistor can be improved, and the effect on reducing noise in analog semiconductor integrated circuits is significant.
第１図は従来例のトランジスタの断面図。第２図は本発
明の一実施例の断面図である。
１・・・Ｐ形シリコン基板、２・・山Ｎ形埋込層。
３・・・・・Ｎ形エピタキシャル層、４・・・・フィー
ルド酸化膜、５・・・・・Ｐ形ペース領域、６・・・・
・・Ｎ形エミッタ領域、７・・・・・Ｐ形多結晶半導体
層、８．−Ｎ形多結晶半導体層、９・・・多結晶半導体
酸化膜、１０・・・・・ベース電極、１１・・・・エミ
、り電極、１２・・・・・酸化膜、１３・・・・・蟹化
膜全それぞれ示す。
（
旨
）
乙
午２ 口FIG. 1 is a cross-sectional view of a conventional transistor. FIG. 2 is a sectional view of one embodiment of the present invention. 1... P-type silicon substrate, 2... Mountain N-type buried layer. 3...N-type epitaxial layer, 4...Field oxide film, 5...P-type space region, 6...
. . . N-type emitter region, 7. . . P-type polycrystalline semiconductor layer, 8. -N type polycrystalline semiconductor layer, 9... polycrystalline semiconductor oxide film, 10... base electrode, 11... emitter electrode, 12... oxide film, 13... ...All crab membranes are shown. (To that effect) Otogo 2 mouths
Claims (1)
た不純物添加多結晶半導体層をエミッタ電極とするバイ
ポーラトランジスタを含む半導体装ｆｆ１ｔＦこおいて
、エミッタ・ベース接合表面を前記不純物添加多結晶半
導体層でおおったこと？特徴とする半導体装置。[Claims] In a semiconductor device ff1tF including a bipolar transistor formed on a 2° single-crystal semiconductor substrate and having as an emitter electrode an impurity-doped polycrystalline semiconductor layer separated by a selective oxide film, an emitter-base junction is formed. Did you cover the surface with the impurity-doped polycrystalline semiconductor layer? Characteristic semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4347183A JPS59169177A (en) | 1983-03-16 | 1983-03-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4347183A JPS59169177A (en) | 1983-03-16 | 1983-03-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59169177A true JPS59169177A (en) | 1984-09-25 |
Family
ID=12664631
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4347183A Pending JPS59169177A (en) | 1983-03-16 | 1983-03-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59169177A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6379244B1 (en) | 1997-09-17 | 2002-04-30 | Konami Co., Ltd. | Music action game machine, performance operation instructing system for music action game and storage device readable by computer |
| US6410835B2 (en) | 1998-07-24 | 2002-06-25 | Konami Co., Ltd. | Dance game apparatus and step-on base for dance game |
| US6582309B2 (en) | 1998-07-14 | 2003-06-24 | Konami Co., Ltd. | Game system and computer-readable recording medium |
| US6645067B1 (en) | 1999-02-16 | 2003-11-11 | Konami Co., Ltd. | Music staging device apparatus, music staging game method, and readable storage medium |
| US9769908B2 (en) | 2013-12-18 | 2017-09-19 | Sony Corporation | Audio reproduction device |
-
1983
- 1983-03-16 JP JP4347183A patent/JPS59169177A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6379244B1 (en) | 1997-09-17 | 2002-04-30 | Konami Co., Ltd. | Music action game machine, performance operation instructing system for music action game and storage device readable by computer |
| US6582309B2 (en) | 1998-07-14 | 2003-06-24 | Konami Co., Ltd. | Game system and computer-readable recording medium |
| US6410835B2 (en) | 1998-07-24 | 2002-06-25 | Konami Co., Ltd. | Dance game apparatus and step-on base for dance game |
| US6645067B1 (en) | 1999-02-16 | 2003-11-11 | Konami Co., Ltd. | Music staging device apparatus, music staging game method, and readable storage medium |
| US9769908B2 (en) | 2013-12-18 | 2017-09-19 | Sony Corporation | Audio reproduction device |
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