JPS59167059A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59167059A JPS59167059A JP4090083A JP4090083A JPS59167059A JP S59167059 A JPS59167059 A JP S59167059A JP 4090083 A JP4090083 A JP 4090083A JP 4090083 A JP4090083 A JP 4090083A JP S59167059 A JPS59167059 A JP S59167059A
- Authority
- JP
- Japan
- Prior art keywords
- film
- type
- region
- wiring layer
- adhered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 29
- 229910052737 gold Inorganic materials 0.000 claims abstract description 21
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 20
- 239000010931 gold Substances 0.000 claims description 20
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 16
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 12
- 238000000034 method Methods 0.000 abstract description 9
- 238000005530 etching Methods 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 238000002955 isolation Methods 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 238000000992 sputter etching Methods 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- GOQFGEHFZBDYEC-UHFFFAOYSA-N [AlH2+] Chemical compound [AlH2+] GOQFGEHFZBDYEC-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000053 physical method Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ） 発明の技術分野
本発明は半導体装置に係り、特に金又は白金の配線層を
有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor device, and particularly to a semiconductor device having a gold or platinum wiring layer.
（至）技術の背景
半導体集積回路（ＩＣ）は多数の能動素子や受動素子が
半導体基板に設けられて、これら素子相互間は導電配線
層で接続される。その導電配線層としてアｌレミニウム
（ｉ）膜がよく用いられるがＡ４より導電性がよく、か
つ極めて化学的に安定な信頼度の高い金（Ａｕ）又は白
金（）’ｔ）を用いて信頼性が高く、かつ高集積度の構
造を有する半導体装置の検討が行なわれており本発明は
これに関するものである。(To) Background of the Technology A semiconductor integrated circuit (IC) has a large number of active elements and passive elements provided on a semiconductor substrate, and these elements are connected to each other through conductive wiring layers. Aluminum (i) film is often used as the conductive wiring layer, but gold (Au) or platinum ()'t), which has better conductivity than A4 and is extremely chemically stable and reliable, is used for reliability. Semiconductor devices having high performance and highly integrated structures have been studied, and the present invention relates to this.
（（３） 従来技術と問題点
第１図は従来のアＩＶミニウム配線層を用いた半導体装
置の断面例であるが、たとえば図示のようなバイポーラ
形半導体素子が形成された半導体基板ｌ上に接続窓を有
する絶縁膜２を介してアｌレミ。 ニウム金属膜を
被着しパターンニングしてアＩレミニウム配線層３を形
成し、該アＩレミニウム配線層８上に、保護膜たとえば
燐シリケートグラヌ（ＰＳＧ）よりなる絶縁膜４を被覆
して半導体装置が形成される。しかしながらかかる構造
の半導体装置における前記アルミニウム配線層３は絶縁
膜で保護されているものの水分などに対して変質しやす
く化学的に不安定な材料である。((3) Prior Art and Problems Figure 1 shows a cross-sectional example of a semiconductor device using a conventional AIV wiring layer. An aluminum metal film is deposited and patterned via an insulating film 2 having a connection window to form an aluminum wiring layer 3, and a protective film such as a phosphorus silicate film is formed on the aluminum wiring layer 8. A semiconductor device is formed by covering an insulating film 4 made of PSG.However, although the aluminum wiring layer 3 in a semiconductor device having such a structure is protected by an insulating film, it is easily deteriorated by moisture. It is a chemically unstable material.
このようなアルミニウム配線層の代りに金又は白金の金
属膜を配線層として用うれば極めて化学的に安定となり
、かつ導電性もアｌレミニウム配線層より向上する。If a metal film of gold or platinum is used as the wiring layer instead of such an aluminum wiring layer, the wiring layer will be extremely chemically stable and have better conductivity than the aluminum wiring layer.
しかし前記金又は白金の金属膜を単独に配線層として用
いる場合には、前述したように極めて化学的に安定のた
めに、金又は白金の金属膜の配線層形成には通常イオン
ミリングのような物理的な方法によってパターンニング
が行なわれるが所望寸法の微細パターンの形成が難かし
く高集積度の構造を有する半導体装置の形成が難かしい
という問題があった。However, when using the gold or platinum metal film alone as a wiring layer, as mentioned above, due to its extremely chemical stability, ion milling or other methods are usually used to form the wiring layer of the gold or platinum metal film. Patterning is carried out by physical methods, but there are problems in that it is difficult to form fine patterns of desired dimensions and it is difficult to form semiconductor devices having highly integrated structures.
（イ）発明の目的
本発明の目的はかかる問題点に鑑みなされたもので導電
性がよく、極めて信頼度の高い配線層を有し、かつ高集
積度の半導体装置の提供にある。(A) Purpose of the Invention The purpose of the present invention was made in view of the above problems, and is to provide a highly integrated semiconductor device which has good conductivity and extremely reliable wiring layers.
（ｅ） 発明の構成
その目的を達成するため、本発明の半導体装置は上面に
窒化チタン膜が形成された金、又は白金の配線層が設け
られたことを特徴とする。(e) Structure of the Invention In order to achieve the object, the semiconductor device of the present invention is characterized in that a wiring layer of gold or platinum with a titanium nitride film formed on the upper surface is provided.
（ｆ） 発明の実施例 以下本発明の実施例について図面を参照して説明する。(f) Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.
第２図は本発明の一実施例の半導体装置の断面図である
。同図において前述したと同様にバイポーラ形半導体素
子が形成された半導体基板１０上に接続窓を有する絶縁
膜１１を介してたとえば巾２μｍ、厚さ５０００Ａの金
配線層１２が設けられ、該金配線層１２の上面に厚さ約
１０００Ａの窒化チタン（Ｔｉ、Ｎ ）膜１３が被覆さ
れてなる。更に該窒化チタン膜１３を含む半導体基板１
０上に保護膜たとえば燐シリケートグラス（ＰＳＧ ）
よりなる絶縁膜１４が被覆されて半導体装置が形成され
る。FIG. 2 is a sectional view of a semiconductor device according to an embodiment of the present invention. In the same figure, a gold wiring layer 12 having a width of 2 μm and a thickness of 5000 Å, for example, is provided on a semiconductor substrate 10 on which a bipolar semiconductor element is formed, via an insulating film 11 having a connection window, as described above. The upper surface of the layer 12 is coated with a titanium nitride (Ti,N) film 13 having a thickness of approximately 1000 Å. Further, a semiconductor substrate 1 including the titanium nitride film 13
For example, phosphorus silicate glass (PSG)
A semiconductor device is formed by covering the semiconductor device with an insulating film 14 made of the following.
かかる上面に窒化チタン膜１３を被覆した金配線層１２
が設けられた半導体装置においては後述するように前記
窒化チタン膜１３の被覆が金配線層１２形成のためのイ
オンミリング工程におけるエツチングのストッパとして
作用し所望の微細金配線パターンを設けることが可能と
なり、導電性がよく極めて信頼度の高い配線層を有し、
かつ高集積度の半導体装置となる。A gold wiring layer 12 whose upper surface is coated with a titanium nitride film 13
In the semiconductor device provided with the gold wiring layer 12, as will be described later, the coating of the titanium nitride film 13 acts as an etching stopper in the ion milling process for forming the gold wiring layer 12, making it possible to provide a desired fine gold wiring pattern. , has a highly conductive and extremely reliable wiring layer,
In addition, the semiconductor device has a high degree of integration.
次に上記構造の半導体装置の金配線層の形成方法につい
て第８図乃至第５図の要部断面図を用いて説明する。第
３図においてたとえば半導体基板２０上に通常のスパッ
タ法により全面に厚さ約５００ＯＡの金の金属膜を被着
した後、同じく窒化チタンターゲットを用いてスパッタ
法ニより全被着膜２１上に窒化チタン膜２２を約１００
０人の厚さに被覆する。次いで該窒化膜２２上に約１．
５μｍ程度の厚さのレジスト膜をスピンコード法によっ
て塗布し、該レジスト膜をフォトプロ七ス技術によって
所望のパターン、たとえば幅２１１ｍのレジヌト配線パ
ターンマスク膜２８を形成する。上記のように構成され
た半導体基板２０を通常のイオンミリング方法によって
イオンミリングする。かかる場合においてイオンミリン
グによるエツチングｖ−）はレジスト膜２３及び全被着
膜２１はほぼ同一で約１０００人／ｍ１ｎ、窒化チタン
膜２２は約１００〜１４０人／ｍ１ｎであるため窒化チ
タン膜２２はエツチングのヌトツバーの作用として働き
、第４図に示すように変形のないほぼレジヌトパターン
と同じ寸法の金酩線層得ることができる。次いで所定の
イオンミリング後残存せるレジスト膜２８を除去すれば
第５図に示す上面に窒化チタン膜２２金、白金のみをイ
オンミリングエッチを用いる場合でも、金、白金に変形
のない配線層を得ることができる。Next, a method for forming a gold wiring layer in a semiconductor device having the above structure will be described with reference to main part sectional views shown in FIGS. 8 to 5. In FIG. 3, for example, after a gold metal film with a thickness of about 500 OA is deposited on the entire surface of a semiconductor substrate 20 by a normal sputtering method, a titanium nitride target is also used to deposit a gold metal film on the entire deposited film 21 by a sputtering method. The titanium nitride film 22 is approximately 100%
Coat to a thickness of 0 people. Next, about 1.
A resist film having a thickness of about 5 μm is applied by a spin code method, and a desired pattern, for example, a resin wiring pattern mask film 28 having a width of 211 m is formed using the resist film by a photopross technique. The semiconductor substrate 20 configured as described above is subjected to ion milling using a normal ion milling method. In such a case, etching v-) by ion milling is almost the same for the resist film 23 and the entire deposited film 21, about 1000 etching/m1n, and for the titanium nitride film 22, about 100 to 140 etching/m1n. This works as an effect of the etching nut, and as shown in FIG. 4, it is possible to obtain a gold wire layer with substantially the same dimensions as the resin pattern without deformation, as shown in FIG. Next, by removing the resist film 28 remaining after a predetermined ion milling process, a wiring layer with no deformation of the titanium nitride film 22 on the top surface as shown in FIG. 5 is obtained even when using ion milling etching of only gold and platinum. be able to.
（ロ）発明の詳細
な説明したごとく本発明の一実施例によれば上面に窒化
チタン膜を被覆した金配線層が精度よく設けられた構造
を有し、導電性よく極めて信頼性が高く、かつ高集積度
の半導体装置となる。尚本実施例については金の配線層
が設けられた半導体装置について説明したが白金の配線
層についても同様な効果をうろことは勿論である。(b) As described in detail, one embodiment of the present invention has a structure in which a gold wiring layer coated with a titanium nitride film is provided on the upper surface with high precision, and has good conductivity and extremely high reliability. In addition, the semiconductor device has a high degree of integration. Although this embodiment has been described with reference to a semiconductor device provided with a gold wiring layer, it goes without saying that similar effects can be obtained with a platinum wiring layer.
第１図は従来の半導体装置の断面図、第２図は本発明の
一実施例の半導体装置の断面図、第３図乃至第５図は本
発明の一実施例の半導体装置の配線層の形成方法を説明
するための要部断面図である。
図において、１２・２１は金の配線層、１３・２２は窒
化チタン膜を示す。
第１図
第２図
第３図
第４図
第５Ｂ０FIG. 1 is a cross-sectional view of a conventional semiconductor device, FIG. 2 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, and FIGS. 3 to 5 are cross-sectional views of a semiconductor device according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of a main part for explaining a forming method. In the figure, 12 and 21 indicate gold wiring layers, and 13 and 22 indicate titanium nitride films. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5B0
Claims (1)
設けられたことを特徴とする半導体装置A semiconductor device characterized by having a gold or platinum wiring layer on which a titanium nitride film is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4090083A JPS59167059A (en) | 1983-03-11 | 1983-03-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4090083A JPS59167059A (en) | 1983-03-11 | 1983-03-11 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59167059A true JPS59167059A (en) | 1984-09-20 |
| JPH056342B2 JPH056342B2 (en) | 1993-01-26 |
Family
ID=12593384
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4090083A Granted JPS59167059A (en) | 1983-03-11 | 1983-03-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59167059A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61256654A (en) * | 1985-05-09 | 1986-11-14 | Nec Corp | Formation of multilayer interconnection |
| US4920071A (en) * | 1985-03-15 | 1990-04-24 | Fairchild Camera And Instrument Corporation | High temperature interconnect system for an integrated circuit |
| US5535843A (en) * | 1993-12-20 | 1996-07-16 | Nippondenso Co., Ltd. | Traveling carriage |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57133683A (en) * | 1981-02-12 | 1982-08-18 | Nec Corp | Semiconductor device |
-
1983
- 1983-03-11 JP JP4090083A patent/JPS59167059A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57133683A (en) * | 1981-02-12 | 1982-08-18 | Nec Corp | Semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4920071A (en) * | 1985-03-15 | 1990-04-24 | Fairchild Camera And Instrument Corporation | High temperature interconnect system for an integrated circuit |
| US5414301A (en) * | 1985-03-15 | 1995-05-09 | National Semiconductor Corporation | High temperature interconnect system for an integrated circuit |
| JPS61256654A (en) * | 1985-05-09 | 1986-11-14 | Nec Corp | Formation of multilayer interconnection |
| US5535843A (en) * | 1993-12-20 | 1996-07-16 | Nippondenso Co., Ltd. | Traveling carriage |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH056342B2 (en) | 1993-01-26 |
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