JPS59165285A - Semiconductor storage element - Google Patents

Abstract

PURPOSE:To support plural kinds of high speed operating modes having different read data bit number in the same chip constitution by providing a circuit outputting continuously a data having the designated bit number by control information by means of a storage circuit of the control information and data latch. CONSTITUTION:When the control informatin set to a register 5c at a phase T3 is ''11'', data in total 8-bit are outputted in high speed one by one bit from the data latch 3 at phases T2-T9. Simiarly, when the information is ''10'', data in total 4-bit are outputted sequentially at phases T2-T5, and when ''01'', data in total 2-bit are outputted sequentially at phases T2, T3. When ''00'', the mode is selected as the normal operating mode and only the data in 1-bit are outputted at the phase T2. Thus, in the high speed mode, the timing of data output at the 2nd-bit and succeeding is controlled by a count pulse generating circuit 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device capable of handling a high-speed operation mode.

[Prior art]

There is a semiconductor memory element that has a high-speed operation mode called nibble mode. This method accesses multiple memory blocks simultaneously, reads 4 consecutive bits of stored data into the data latch, and pulls the data from the data latch into 1,000 consecutive bits without repeatedly accessing the memory blocks. It is configured to output one bit at a time at high speed.

Second, this 'Nibble' mode can significantly reduce memory access time compared to the normal mode; however, depending on the application, it may be possible to read 2-bit or 8-bit data continuously at high speed. is sometimes preferable.

However, it is generally disadvantageous in terms of productivity and production cost to produce semiconductor memory elements with different numbers of bits of continuous read data as separate memory chips.

[Purpose of the invention]

SUMMARY OF THE INVENTION In view of the problem of soft soil, it is an object of the present invention to provide a semiconductor memory element that supports various types of high-speed operation modes in which the number of consecutively read data bits differs with the same chip configuration.

[Summary of the invention]

The present invention provides a semiconductor memory element configured to simultaneously access a plurality of memory blocks and simultaneously read stored data from each of the memory blocks into a data latch.
A circuit that holds control information, and a circuit that controls data output from the data latch according to the control information and continuously outputs data for the number of bits specified by the control information from the data latch. It is characterized by this.

[Embodiments of the invention]

FIG. 1 is a block diagram of a 256KRAM which is an embodiment of the present invention, and FIG. 2 is a timing diagram showing its operation.

In FIG. 1, 1 is a memory block in which memory cells are arranged in a matrix of 256 rows by 128 columns, and there are 8 blocks. Each memory block 1 has 128 sense amplifiers 2, and each memory block 1a is provided with one data latch 3. 4 is a selector,
5a is an 8-bit register, and 5c is a 2-bit register.

5b is a 3-bit register which also operates as a modulo 80 counter. 6a to 6c are decoders, 7 is a timing generation circuit, 8 is a count pulse generation circuit, and 9 is an OR circuit.

A, -As is address No. 4m, RA input from the outside.
S, CAS, and WE are timing signals input from the outside, Dout is a 1-bit data cutoff signal, and Din is a 1-bit data input signal.

The timing generation circuit 7 generates a timing signal group 10 to each part and a count pulse 11 in accordance with the timing signals RUQ, SHINISHI, and SERI. The count/9-less generation circuit 8 continuously generates count pulses 12 of a number corresponding to the output No. 48 of the decoder 6c. current pulse 11
, 1:l:l: is supplied to the clock input of the register 5b through the OR circuit 9.

Next, the data read operation of this embodiment will be explained with reference to the timing diagram of FIG.

In phase T when the RAS signal falls, the contents of 8 bits (row address) of the address signals A to A8 are latched into the register 5a, and the contents of the remaining 1 bit are latched into the register 5b. The timing of this latch is controlled by a timing signal (10).The decoder 6a decodes the contents of the register 5a and drives the word line of the corresponding row of all memory blocks 1 (the timing of this drive is controlled by the timing signal 10). (controlled by αOj).

In phase T2 when the image signal rises, the address signal A,
~The 7-bit contents (column address) of A8 are stored in register 5a.
Then, the contents of the remaining 92 bits are latched in the register 5b (this latch timing is determined by the timing coefficient αQ).
]. The decoder 6b decodes the contents of the register 5a and drives the data line of one corresponding column of each memory block 1 (driving timing is controlled by timing signal 0Q). With this, each memory block 1
A total of 8 bits of data, 1 bit at a time, is output from the sense amplifier 2 and latched into the data latch 3 (the data latch 3 has been reset in advance before phase T2). Further, the selector 4 selects one data latch 3 specified by the contents (3 bits) of the register 5b, and outputs the 1-bit data held there as a data output signal.

Output as ut. The timing of each of these operations is controlled by a timing signal (10).

At the next need T3, the contents (control information) of two bits of the address signals A and o-As are latched into the register 5c. The decoder 6C decodes the control information latched in the register 5c, and the control information becomes "' o, o".
If the output line is tt O1j+, the output line is 1.
0", output line C, (11171, output line d, respectively. When a "1" signal appears on line a, it does not operate, but when a "1" signal appears on the output line, the Hooniz T3 sends out one count pulse of 12. Also, when the output line C receives a °'1 ``When the A word comes out, phase T3~T
A total of 3 clicks, one for each of 5) ノ4) When response 12 receives a 1" signal on output line d, phase T is activated.
A total of seven count pulses 12, one for each of T3 to T9, are sent out from the count pulseless generation circuit 8.

The register 5b uses the value latched in the phase T1+T2 as an initial value, and counts up by 1 each time a count pulse is applied through the OR circuit 9. In addition, register 5
b becomes '000' after reaching the full count '''111''
The count is restarted from ".The selector 4 selects the data latch 3 corresponding to the count value of the register 5b, and sends the held data to the data output signal.u.
Output as t.

Therefore, when the control information set in the register 5c in phase T3 is "P11", a total of 8 bits of data is sequentially transmitted 1 bit at a time from data latch 3 in phases T2 to T9 at high speed, as shown in FIG. Similarly, if the control information is 10'', a total of 4 outputs are output in phases T2 to T5.
The data of the j adjacent bits is output (phases T6 to T9)
), if the control information is °゛01'', phase T
At 2 1 T 3, M12 bit data is sequentially output (there are no phases T4 to T9. When the control information is “00n”)
In this case, in the high-speed operation mode (without d), the mode becomes normal operation mode, and only 1 bit of data is output in phase T2 (there are no phases T3 to T9).As shown above, in the high-speed operation mode, 2 bits of data are output. The timing of subsequent data outputs is controlled by the count pulse generation circuit 8.

Note that the write operation is also similar to the read operation, and the details will be omitted.

At this point, in the above embodiment, data is taken in from the control information tray address signals A, -A, and latched in the register 5c. You can also do this. If it is acceptable to fix the operation mode, the contents of the register 5c and the control information may be fixed by hardware. Furthermore, the number of bits read out continuously in the high-speed operation mode can be increased to 4ai' by increasing the number of pits in the register 5c.
It can be made more switchable than AA.

〔Effect of the invention〕

As described in detail above, according to the present invention, a semiconductor memory element that supports higher-speed operation modes with different numbers of read data bits can be produced using a circuit-configured memory chip.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing diagram for explaining the creation of the embodiment. 1...Memory block, 3...Data latch, 4...
...Selector, 5a to 5C...Register, 6a to 6C
... Decoder, 7... Timing generation circuit, 8...
- Currant noguru generation circuit. Part i 1. P-I!

Claims (1)

[Claims] In a semiconductor memory element configured to simultaneously access a plurality of memory blocks and simultaneously read stored data from each of the memory blocks to a data latch, a circuit that holds control information and data output from the data latch according to the control information are provided. 1. A semiconductor memory element, comprising: a circuit that controls the data latch and continuously outputs data for the number of bits specified by the control information from the data latch.