JPS5914955B2 - Time division multiplexed pulse code modulation communication system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time division multiplexed (TDM) communication system using pulse code modulation (PCM).

More particularly, the present invention relates to a novel method and apparatus for exchanging information between various user terminals of a TDMPCM system. TDM telephone systems operate on a time-sharing basis where many conversations divide a single communication path. Conversations are assigned to channels for short intervals that periodically cycle. The speech samples are encoded into corresponding binary words using pulse code modulation techniques. These binary words are transmitted over the channel during the assigned time slots and decoded into the original speech at the receiving terminal. A TDM switching system typically has two outgoing paths (0UtC01I1g
path) and two entrance paths (IncOmingpath
). A conversation between two user terminals is assigned to one time slot and transmitted via the incoming and outgoing paths.

Both the ingress and egress paths are used to keep each conversation going from one side to the other separate from the conversations going backwards. The switching network determines the ingress and egress of the two user terminals, and the signal on the ingress of one is transferred to the egress of the other. The user terminal is enabled by control of an interconnected memory within the switching system, which memory contains word positions corresponding to each of the time slots within a time slot frame. The memory word of each location contains not only the addresses of the two terminals to be connected, but also the identification of the transmission path that needs to be enabled in order to achieve the interconnection. When expanding the capacity of the system described above, additional ingress and egress pairs are required, and to enable and convert user terminals associated with these additional transmission path pairs. requires an exchange of space and time.

Additionally, it is necessary to expand the memory capacity to accommodate this. Furthermore, it would also be necessary to extend the length of the memory word itself. Each memory word contains time slot information to enable data memory to transfer sample values between time slots, and space switches to interconnect various input and output paths as needed. Space switch information shall be included. Therefore, the cost of memory capacity typically increases out of proportion to the increase in the number of user terminals. An example of a time division switching system is U.S. Pat. No. 3,573, issued April 6, 1971.
1TimeLivisi0nSwitch No. 381
It is described in ngSystemt1.

The system has a plurality of space exchange and data storage devices that displace data between various time channels when transmitting between multi-channel time multiplex paths.
Although this system is quite flexible and has high traffic capacity, it requires a significant amount of memory to control the operation of the switched network and to store the data being transmitted. Another example of a time division switching system is U.S. Pat.
ivisi0nSwitchingSystem1W.

This system exchanges individual information bits of pulse code modulated words between various time slots and time division buses. Figures 4A and 4B of this patent show a pulse shifter that includes two shift registers and a gate matrix connected between the shift registers. The gate matrix is controlled by the memory to select a new order of information bits within each frame. This system is relatively flexible and has high traffic capacity. However, a significant amount of memory is required to control the pulse shifter. Conventional TDMP
CM exchange systems generally require a large amount of memory,
It has high traffic processing capacity.

When only a few hundred telephones and relatively low traffic are required, the known PCMTDM system may not be practical as an alternative to other forms of TDM systems such as pulse amplitude modulation (PAM) or delta modulation systems. It's too expensive. On the other hand, telephone systems tend to expand over time. PAM or delta modulation system is
Despite its known drawbacks, it is used in small-scale systems due to its cost advantages. However, these have not been utilized in large scale systems where the price advantage is insignificant or non-existent. Currently, private branch exchange (PBX) users have to either initially install a TDMPCM system that is much larger and much more expensive than what they currently need, or they have to either install a TDMPCM system that is much larger and much more expensive than they currently need, or they can choose to install a TDMPCM system that is much cheaper but expensive to expand. They are faced with the choice of installing a system that is costly or cannot be expanded.

Sometimes a less expensive system is selected that meets the user's current requirements but cannot economically meet future requirements. However, once the system exceeds a certain size, the price of scaling increases rapidly.
However, at some point, the old system will have to be replaced with a new, larger system. Of course, purchasing and installing a new system involves considerable expense in addition to the inconvenience of removing and disposing of the old system.
The present invention has been made in view of the above circumstances, and is an expandable TDMPCM system that reduces costs without reducing its capacity, and which reduces the cost of adding additional transmission lines to the system. Provides a relatively low cost system compared to increasing the size of the system itself.

Interconnected memory within the network circuitry is coupled to the temporary user terminal. This memory only has as many word positions as there are time slots, and the word in each position must only be long enough to provide one user terminal address and one network circuit address. I need. When expanding the system, additional network circuits can be interconnected via network buses without any need to increase the word length of the interconnect memory. In the network circuit, a unique time slot switching circuit performs a sequential time slot switching function that limits conversations between user terminals using fixed time slot pairs. A plurality of user communication terminals are connected to one network circuit via a human transmission line and an output transmission line.

In the network circuit, a time slot exchange circuit for exchanging information bits between a fixed pair of time slots is connected in series between the two transmission lines. A memory having n word positions corresponding to n time slots is loaded with the user terminal address. A time slot address generator periodically generates a time slot address in response to the overcurrent signal. This time slot address causes the memory to output one user terminal address per time slot.
Each user terminal accepts information bits from the outgoing transmission path in response to a predetermined terminal address and transmits the information bits onto the human transmission path. To expand the system, multiple network circuits are interconnected via network buses. Each network circuit includes a space switch. The space switch has a plurality of input terminals connected to a plurality of transmission lines of the network bus.
The space switch transfers an information bit appearing on one of its input terminals to its output terminal in response to a plurality of bits in a terminal address from memory. According to the present invention, control for controlling the formation of a transmission path between a user terminal and a switching network in order to transfer information between a plurality of user terminals, the switching network, and a predetermined user terminal A TDMPCM communication system is provided having circuit means.

The incoming path carries information bits from the user terminal to the switching network, and the outgoing path carries information bits from the switching network to the user terminal. The switching network includes transfer means for transferring a single bit of information within one time slot period from ingress to egress. The transfer means includes exchange means for bidirectional exchange of information bits in a fixed pair of time slot periods, thereby periodically establishing an information bit transmission path between user terminals as determined by said control circuit means. It is formed. Further in accordance with the present invention, a method of operating a TDM PCM communication system as described above is also provided.

In this method, first, a sequence of n even numbered time slot addresses is successively generated. During the generation of each time slot address, information bits are accepted from the incoming path. The accepted information bits are exchanged bidirectionally between fixed pairs of time slots and transmitted to the outbound destination.
Two user terminals are each enabled during the occurrence of each time slot of a fixed time slot pair.

Each of the enabled user terminals accepts one of the information bits transmitted to the output path, and for the significant bits of the information bits received from this output path only one in the order of significant bits in PCM word format. Transmit the advanced information bits onto the input path. In this way, m-bit PCM words are exchanged bit by bit between enabled user terminals during a fixed pair of time slot periods. 1
In one arrangement, in each frame of an even number of n time slots, each fixed pair of time slots is n/
They are separated by 2-1 time slot periods.

Each bit transmitted from one user terminal is delayed by n/2 time slot periods before being accepted by another user terminal.

In another arrangement, the time slots of each fixed pair are adjacent to each other.

Each bit transmitted from one user terminal is passed through n+1 or n depending on whether the instantaneous time slot is even or odd before being accepted by another user terminal.
Delayed by one time slot period.

Next, the configuration and operation of a specific example of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the invention are illustrated in functional circuit blocks.

Its individual circuit functions are well known and may be provided by hand-able integrated circuits or other circuits well known to those skilled in the art. To explain with reference to FIG. 1, the central processing unit (CPU
) 200 is connected to the complex networks (NetwOrkcOplex) 0 to 4 and the network bus multiplex converter 100 via a system address bus 201, a system data bus 202, and a control bus 203.

System address bus 201 carries addresses from CPU 2OO to other parts of the system. The various parts of the system communicate with CPU 2OO via system data bus 202, each responsive to a unique address. The system data bus 202 is the CPU 2
It transports instruction data words from OO to other parts of the system, and also transfers data generated by various parts of the system to C.
Return to PU2OO. Control bus 203 is a group of conductors, each having a specific signal function. For example, several conductors within this bus may be connected to the CPU 2OO to complete various functions in the complex circuit and network bus multiplexer 100.
used to instruct. CPU 2OO may be a special purpose computer specifically designed for use in this system, or it may be an appropriately programmed general purpose computer. Each of the composite networks includes a group of network circuits 10 and a peripheral interface device 210.

In FIG. 1, eight (0-7) network circuits 10 are operated by one peripheral interface unit (PIU) 210. In FIG. The minimum system that can work effectively is one PIU2IO and one network circuit 1
0. A network bus 16 is provided for interconnecting network circuit 10 and one or more service circuits, such as those shown in FIG. 5, for example. This network bus 16 forms one output transmission line for each network circuit 10, providing a maximum of 16 transmission lines in this case. If there is more than one composite network, network bus multiplexer 100 is required to provide space and delay exchange between two or more network buses 16.

Figure 6 shows the PCM used in the system of Figure 1.
Indicates the format.

One main frame consists of m frames, each frame consisting of n single time slots, each time slot being divided into a front half and a back half.

Each transmission line within network bus 16 can carry 2n PCM words in one main frame. Each PC
An M word has one signal bit in a designated half-time slot within each frame. All of the network circuits 10 each transfer information bits to transmission lines within the network bus during the first half of one time slot;
One information bit can be accepted from the network bus either before or after a time slot. In the basic system, one PIU2IO generates the system clock and frame synchronization signals.

In an expanded system with one or more complex networks,
Network bus multiplexer 100 generates these signals and provides them to each composite network via system synchronous bus 204.

Communication between each PIU 2IO and the CPU 2OO occurs via a system address bus 201, a system data bus 202, and a control bus 203. Each PIU2lO is
They are individually called by CPU 2OO in response to a predetermined address transmitted on system address bus 201 by CPU 2OO. Next, since all of the above composite networks are identical, only one composite network will be described in detail.

Time slot synchronization and main frame synchronization for network circuit 10 is provided via synchronization bus 217 from PIU 210. In addition to this timing function, the PIU
2IO also provides a storage buffer for transferring signals and monitoring information between network circuit 10 and CPU 2OO. Signal information is conveyed to network circuit 10 in series via signal conductor 214 and via signal conductor 21.
3 from the network circuit 10 in series. Between PIU2lO and CPU2OO, the signal information is
It is exchanged in parallel via system data bus 202. PIU2IO also provides network circuit signal scanning functionality.

Each network circuit 10 is called in a circular manner under the control of a network address generated by the PIU 210. Network addresses are individually routed to network circuits 10 on network address bus 215. Network circuit 10, when called by its unique network circuit address, can provide signal information instructions to PIU 210 via signal conductor 213. In that case, the scanning function is stopped at that loop address until signal information is continuously transmitted via signal conductor 213. Each network circuit 10 in the composite network is connected to the CPU 2 via a system address bus 201, a system data bus 202, and a control bus 203.
Connected to OO.

Each network circuit 10 is also connected to input transmission equipment on transmission line 12 and output transmission equipment on transmission line 13. Transmission lines 12 and 13 carry PCM information bits between network circuit 10 and terminal control buffer circuit (TCB) 70. Each TCB transmits PCM information bits to a terminal interface device (TCB) via lines 12a and 13a.
IU) 301 and 302 or the transport interface device 400, or from these devices.
Further, a terminal address and an auxiliary control signal are transmitted from each network circuit 10 to each TCB 70 via a terminal control bus 14. TCB 7O decodes the terminal address and auxiliary control signals and enables the selected one of the TIUs via bus 71. Each of TIU3Ol and 302 has a user terminal coupled directly or indirectly thereto. The maximum number of user terminals that can actually be connected in this way is limited by the number of available time slots, but
The total number of user terminals is limited only by the minimum acceptance of service at the maximum expected traffic level. Each terminal interface device includes special types of communication equipment such as analog and digital trunks, subscriber telephones,
It is adapted to form an interface with communication terminal equipment such as key telephones and data terminals.

For example, the illustrated TIU 3Ol is connected to subscriber telephone 500 and central office trunk facility 313. Terminal interface unit (TIU) 302 and key telephone 311 have been developed to take advantage of the useful features in this embodiment. The key telephone 311 is connected to the T
Connected to IU3O2. However, this equipment is not the subject of description here, and is described in detail in Japanese Patent Application No. 123349/1983, filed by the same applicant as the present applicant. If two terminal interface devices are required to exchange information, the terminal address of each of them is provided simultaneously in adjacent time slots by the combined network circuit or circuits. Ru.

Thus, each TIU extracts information from transmission line 13 during its designated time slot and also sends information to transmission line 12. In a system with n channels, the network circuitry actually delays the information in each time slot by n±1 time slot periods. For example, information received during time slot 2 is sent to transmission line 13 during time slot 3, and information received during time slot 3 is sent to transmission line 13 during time slot 2. . Next, the network circuit will be explained in detail.

FIG. 2 is a block diagram of network circuit 10 of FIG. This network circuit performs time slot information, spatial switching, and terminal address exchange under instructions from the CPU 2OO. In this particular embodiment, network circuit 10 can be shown in two parts: a network control circuit and a network switching circuit. The control circuit portion includes a counter 20 for generating time slot addresses, a memory 23 and associated circuitry for generating terminal addresses in response to these time slot addresses.

Terminal addresses are written into memory 23 by CPU 2OO in response to changes in the status of user terminals associated with network circuitry 10. Counter 20 is driven by a system clock signal from synchronization bus 217 having a frequency of approximately 2 MHz and a main frame periodic signal having a submultiple frequency of approximately 8 KHz. The main frame synchronization signal ensures that all of the network circuits 10 are synchronized with each other. Counter 20 counts the system clock signal and generates 32 time slot addresses from that signal. The occurrence of 32 time slot addresses corresponds to one frame.

Eight frames occur in the interval between the two main frame synchronization signals to provide the transmission of an 8-bit PCM word.

Address match comparator 21 is connected to a fixed network address determined by the physical location of network circuit 10 within the system. This fixed address is provided in all cases by fixed address conductor 201a. The time slot address supplied from counter 20 via conductor 27 is combined with a fixed address;
It is compared with a portion of the system address on system address bus 201 by comparator 21 to determine if a match has occurred. Another portion of the system address is decoded within the input circuit of comparator 21 to determine whether the system address is acceptable to the network circuitry. If the system address is acceptable and a match has occurred, comparator 21 provides a match signal to memory enable logic 22. Further, the logic circuit 22 receives one bit from the system address bus 201 and also receives one bit from the CPU 2OO via the control bus 203.
Accepts read and write requests from. Next, writing to the network circuit will be explained.

Memory 23 stores terminal addresses necessary to control the operation of network circuit 10 and user terminals coupled thereto. This memory 23 has 32 word locations for storing terminal addresses. This memory is accessed sequentially from counter 20 to lead 2.
7. Matching signal from comparator 21 and control bus 20
When there is a write request from the CPU 2OO supplied via the enable logic circuit 22
to store the state of data bus 202 in the memory location determined by the time slot address. Immediately after the memory 23 is enabled, the enabling circuit 22 indicates that the memory has been loaded (10ad) by CP
Complete (
d dish-1t) Send a signal. This allows CPU 2OO to write data into the network circuit at a predetermined time and memory location determined by the time slot address. Also, to explain reading from the network circuit, there is a C
PU2OO. There are two sources that can be read directly by the memory 23 and the counter 33 described below. A read selection circuit 24 is connected to the memory 23 via a conductor 29, and this circuit is connected to the output of the counter 33. Logic circuit 22 generates a read memory signal or a read scan signal depending on the state of the one bit it receives from the address bus. Logic circuit 22 generates this signal in the presence of a match signal from comparator 21 and a read request provided from CPU 2OO via control bus 203. The read selection circuit 24 is connected to the memory 23
Logic circuit 22 responds to the generated read signal by transferring the output from or from counter 33 to system data bus 202 . As with writing,
Enabling logic circuit 22 sends a completion signal to the CPU as soon as output data from memory 23 or data from counter 33 appears on bus 201. In this case,
The completion signal indicates that data has appeared on bus 201.
Instruct PU. Next, scanning control will be explained.

PIU 2IO generates a network circuit address which is compared by comparator 30 to the fixed address of network circuit 10. If the fixed address and network circuit address match, comparator 3
0 sends an enable signal on conductor 35. While this enabling signal is present, signaling information is conveyed between the PIU 21O and the user terminals connected to the input path 12 and the output path 13.
Decoder 31 decodes the time slot addresses from counter 20 and generates a time slot zero signal on conductor 36 when each time slot address becomes zero. If no signal information is actually conveyed, logic gate 32 passes the time slot zero signal to counter 33.
send to Counter 33 generates a terminal scanning address. As mentioned above, the output of counter 33 is transferred to data bus 202 via read selection circuit 24. Next, regarding terminal paging, the conductor 29 from the output of the counter 33 and the output of the memory 23 is connected to the terminal address selection circuit 25.

The selection circuit 25 is controlled to select a scanning address from the counter 33 when the time slot zero signal is supplied to the selection circuit 25 via the inhibit gate 34.
When the time slot zero signal is not supplied from the inhibit gate 34, the selection circuit 25 selects an 8-bit terminal address from the memory 23. When signal information is being conveyed from the PIU 21O, the gate 34 connects the sequential conductor 21 to inhibit the time slot zero signal to the selection circuit 25.
6. Therefore, rather than the output of counter 33, the terminal address at the time slot zero address word position in memory 23 is selected. The selected address is transmitted from the output of the address selection circuit 25 via the terminal address bus 28 to the human power section of the control bus output buffer circuit 50.

Buffer circuit 50 drives terminal control bus 14, which includes terminal address bus 14e for conveying terminal addresses to terminal control buffer circuit (TCB) 70 shown in FIG. Buffer circuit 50 is supplied with a main frame synchronization signal and a double speed system clock signal via synchronization conductor 217. These signals are buffered and routed to T via conductors 14b and 14c.
Transported to CB7O. Test control conductor 14d is connected from the output of buffer circuit 50 to TCB 7O. Turning now to the switching portion of network circuit 10, this portion carries and manipulates all of the PCM signals appearing on transmission lines 12 and 13.

Output path 13 is driven by a buffer circuit 49 . Each terminal interface unit (TIU) responds to a mutually exclusive three-bit terminal address appearing on terminal address bus 14e. A TIU addressed during a particular time slot accepts information from outgoing path 13 and outputs information to incoming path 12. If a test control signal is present on test path 14d, the TIU simply transfers data from output path 13 to input path 12. This allows the network circuit 10 to confirm that the communication path is continuous. Additionally, a main frame synchronization signal and a symmetrical double-speed clock signal are transmitted to all stations via conductors 14b and 14c, respectively, to enable codes within the TIU to decode and encode PCM information in well-known manner. Supplied to TIU. However, the signal transmitted on input path 12 is advanced by one frame relative to the signal received from output path 13. The signal transmitted from the TIU to the input path 12 is received serially into the first stage of the shift register 40. This signal is serially shifted in shift register 40 by a system clock signal provided to register 40 via conductors 2170-. Shift register 40 is arranged such that the total time delay of the last stage of the shift register is one time slot period longer than the frame length of the system. Since one frame length is 32 time slot periods, shift register 4
The time delay of the nth stage of 0 is 33 time slot periods.

The information bits at the (n-1)th stage and the information bits at the (n+1)th stage of the shift register 40 are supplied to a time delay selection circuit 41. The time delay selection circuit 41 selects delays of 31 (n-1) or 33 (n+1) time slot periods depending on whether the time slot address is an even number or an odd number. The system clock speed is controlled by the least significant bit of the timeslot address. Thereby, a bidirectional exchange of information bits between a fixed pair of time slots is accomplished, for example, as shown in the following simplified table. Keeping pace with an even time slot address (Fal
llngin) The information bits are delayed by 33 time slot periods to match the odd time slot addresses, and the information bits keeping pace with the odd time slot addresses are delayed by 33 time slot periods to match the odd time slot addresses. It is delayed by 31 time slot periods to match.

Thus, time slots 2 and 3 are successively exchanged, time slots 4 and 5 are successively exchanged, and so on. For example, the terminal in time slot 2 is the terminal in time slot 3.
The terminal in time slot 3 accepts time slot information from the terminal in time slot 2. The actual user terminal has memory 2
3 and called as described above. Time slot delay selection circuit 41
The output section of is connected to one of the 16 communication paths in the network bus 16.

This network path interconnects terminals that are coupled to other network circuits. All 16 network paths enter space switches 43 within each network circuit.

This space switch 43 is controlled by four data word bits supplied directly from the output of memory 23. Since network bus 16 does not carry supervisory signal information, functions such as the address selection function provided by address selection circuit 25 are not required. Therefore, space switch 4
3 selects one communication path within the network bus 16 and supplies the information in the time slot to the half time slot selection circuit 51. This is necessary for the operation of network coupling multiplex converter 100, as will be described later. Time slot presence information appears at the output of selection circuit 51 and is provided to the input of normal/test selection circuit 44. This selection circuit 44 responds to two bits on conductor 29 and sends either time slot presence information or test information to selection gate 45. As previously mentioned, when the terminal interface device is tested by control of the test signal from line 14d, the terminal interface device simply sends test information from output path 13 to input path 12. The normal/test selection circuit 44 uses the generated test information along with appropriate time slot information to accept to ensure that the TIU's PCM audio path is continuous.
Selection gate 45 accepts time slot presence information from selection circuit 44 or system signal information from output signal conductor 214. The time slot zero signal is sent to the decoder 31.
Selection gate 45 produces system signal information at its output only if the enabling signal is decoded by and produced by comparator 30. In all other cases, the output of normal/test selection circuit 44 passes through selection gate 45 and is routed to output 13 via buffer circuit 49. In the foregoing description, signaling circuitry and signaling functions have been described only as necessary to illustrate the transfer of conventional time slot presence information between various terminal interface devices. Therefore, this signal function will be explained in more detail next. System data bus 2 is used to send signals from PIU2IO to the terminal interface unit (TIU).
desired terminal address from 02 to memory 23.

- is loaded (while the timeslot is zero, the memory address is zero). PIU2lO is system data bus 2
The data component of the signal from the CPU 2OO is accepted and stored via the CPU 02. Thereafter, a control signal generated within PIU 210 and provided to logic gate 34 via sequence conductor 216 causes logic gate 34 to prevent the time slot zero signal from reaching address selection circuit 25. Therefore, while time slot is zero, the terminal address is generated from the data at address location zero in memory 23. When each time slot is zero, select gate 45 supplies signal data to buffer 49 with the time slot zero signal. This signal data is transferred until all of it is transferred.
Via signal conductor 214 and output 13, it is fed sequentially from PIU 2IO to the addressed TIU. TIU to C
In order to send a signal to PU2OO, the TIU must first notify the PIU2IO to transmit the signal, and then the PIU2IO must send an indication to the TIU that the outgoing signal is enabled via a routine. Must be.

The called TIU gives notification by inserting one bit into the time slot zero signal on input path 12. This 1 bit is stored in the shift register 40. When it appears in the -1 stage, it is transferred via conductor 46 to logic gates 3,2. Logic gate 32 responsively inhibits the zero time slot signal from passing through counter 33. Therefore, the scanning function is interrupted and the same TIU is called continuously after each time slot zero, but no other TIUs are called. The called TIU continues to send one bit at each time slot zero until another action is taken by PIU2IO. PIU2
IO continuously generates a rotating example network address. When the network address and network circuit fixed address match, comparator 30 connects conductor 35.
A logic gate 32 and a gated buffer (Gat
edbuffer) 37.

When this enabling signal is sent, the gated two-factor
passes time slot zero information from the second final stage of shift register 40 onto incoming signal conductor 213. Therefore, one bit is accepted by the PIU 210, which stops the network address from rotating and momentarily maintains the network address for the duration of the next subsequent signal sequence. The enable signal from comparator 30 also causes select gate 45 to select signal conductor 2 during time slot zero.
It accepts signal data from PIU2IO via 14. PIU21OO enables the called terminal by sending a predetermined series of data bits onto output path 13 via signal conductor 214, gate 45 and buffer 49. In response, the TIU outputs P
Send continuous signal data to IU2IO. PIU2lO
accepts and stores signal data over a number of successive time slots, so that it is immediately available to the CPU when requested.
It can be called by 2OO. Once the data is stored, the PIU 2IO and network circuits return to normal scanning for signal functions until another signal input or output train is initiated. Next, the terminal interface device and the terminal control buffer circuit will be described in detail.

FIG. 3 shows the terminal control buffer circuit (TCB) shown in FIG.
) 70 and TIU3Ol in detail.

Each of the network circuits 10 is coupled with one TCB 7O. TCB7O has approximately 150 TIUs
3Ol provides PCM signal buffering, decoding and timing functions. TCB 70 includes a PCM signal buffer 72 that acts as a repeater for PCM signals. Between the buffer 72 and the network circuit 10, an output PCM path 13 and an input PCM path are connected, respectively, as shown in FIGS.
The output PCM signal and the human PCM signal are transmitted via the M path 12. The output PCM signal and the input PCM signal are sent to the buffer 72 and the TIU via respective transmission lines 13a and 12a.
The signal is transmitted between a code converter (COdec) 320 and a supervisory control circuit 330 in the 3Ol. The TCB 7O also includes a synchronization regenerator 75 and a terminal address decoding circuit 77. Terminal address decoding circuit 77 accepts terminal addresses from network circuit 10 via terminal address bus 14e in terminal control bus 14 and decodes the appropriate TIU 3O determined by the content of each terminal address.
1 via a single conductor in control bus 71. When an unindicated time slot occurs, the contents of the terminal address indicate that no enabling signal is to be sent. The synchronous regenerator 75 receives data from the network circuit via the conductors 14b and 14c in the terminal control bus 14.
The main frame synchronization signal and the system clock doubling signal are respectively accepted. This synchronization regenerator 75 is supplied with a system clock double signal rather than a system clock signal to enable accurate timing signal reproduction with relatively simple circuitry. This signal causes the synchronous regenerator 75 to:
System clock signal, time slot zero indication signal, phase 1
A main frame synchronization signal and a phase 2 main frame synchronization signal are generated and provided to the TIU 3Ol via respective conductors in the control bus 71. As shown in Figure 6, phase 2
is replaced by advancing phase 1 by one frame period. The signal from the synchronous regenerator 75 is supplied to a code converter 320 and a supervisory control circuit 330. However, the phase 2 main frame synchronization signal is provided only to code converter 320. In FIG. 3, TIU3Ol includes a line circuit 340 connected to telephone 500 via subscriber loop 501. In FIG. However, other TIU3Ol
For example, a modification of line circuit 840 is required to connect to a two-wire or four-wire analog trunk facility. Rice circuit 340 is connected to code converter 320 via outgoing analog audio lead 13b and incoming analog audio lead 12b. This line circuit 340 includes conductors 334 for station ringing (20Hz), station battery, and ground.
335 and 336 are connected. In operation, each time an enable signal appears on bus 71, a transcoder connected to that bus accepts a PCM information signal bit and transmits a PCM information signal bit. PCM transmitted
The order of significance of each of the information signal bits is determined by the phase 2 main frame synchronization signal. PCM received
The order of significance of each of the information signal bits is determined by the phase 1 main frame synchronization signal. This is two T
Compensates for the inherent delay in transmitting time slot presence information between IUs. At transcoder 320, the analog voiceband signal is transferred from telephone 500 to subscriber loop 5,
It is received via the line circuit 340 and the input wire 12b. This analog signal is encoded into a PCM word for transmission to transmission path 12a. PCM information signal bits are accepted from output 13a and assembled into PCM words. This PCM word is converted to a voice band signal and transmitted to the telephone via line circuit 340 and subscriber loop 501. Line circuit 340 can be implemented using well-known circuit elements. Line circuit 340 and supervisory control circuit 3
30 is via control lead 332. The line circuit 340 provides the supervisory control circuit 330 with a signal indicating the status of the subscriber loop 501, and supplies the supervisory control circuit 330 with a supervisory signal (for example, 20 Hz ringing) to apply a supervisory signal (for example, 20 Hz ringing) to the telephone 500 as necessary. Therefore, it can be controlled. The supervisory control circuit 330 responds to the enable signal while the time slot zero indication signal is supplied by transmitting successive signal bits over the transmission line 12a as previously described with respect to FIGS. 1 and 2. The data can be transmitted via the transmission path 13a, or received via the transmission path 13a.

During the time slot zero indication, transcoder 320 is inhibited from receiving or transmitting information bits. T
CB7O also includes a continuity test circuit 73.

This circuit causes buffer 72 to transfer information bits from output 13 to input 1 in response to a predetermined signal condition on test lead 14d.
2. As a result, the normal/test selection circuit 44 shown in FIG. 2 performs a continuity check to confirm the operation of the transmission lines 12 and 13 and the network circuit shown in FIG. In a typical system, T
CB7O serves 150 TIU3Ol and/or 302 depending on the traffic to be considered.

In FIG. 1, a seventh TCB 7O is connected to a transport interface device 400 forming an interface with a known terminal interface transport facility 314. In FIG. Transport facility 314 is illustrated merely to demonstrate the flexibility of the switching system of the present invention. Regarding this feature, the transport interface device 400 is simply a PC.
It will only be stated that the reframing of the M word is performed to make the exchange system and the transport equipment compatible. Next, the network bus multiplexing device 100 will be described, which is illustrated in detail in FIG.

If the system is large enough to require more than 15 network circuits 10, additional network buses will need to be added. This is illustrated in FIG. 1 as network bus lines NB1 through NB4.
A network bus multiplexing device is provided to form an information path that interconnects these network buses. Additionally, it has been found practical to perform all basic complex network timing functions from multiplexer 100. Therefore, when a multiplexer is added to the system, the timing source within each PIU 2IO is subordinated to the system synchronization source 110. System synchronization source 110 generates system clock, system clock double, main frame synchronization, and local clock inhibit signals on appropriate conductors in system synchronization bus 204. Each of the communication paths within each network bus is individually connected to one of the group of bit enlarger circuits 114. Each of the bit enlarger circuits clocks the system clock so that it accepts a bit of information in the first half of a time slot and outputs the information bit throughout the time slot.
Controlled by the double signal. The output terminal of each bit enlarger circuit is connected to a space switching circuit 116.

This circuit 116 is capable of transferring time slot presence information from any one information path in any one network bus to any one of four information paths in the other network bus. . For example, one information path within NBO can be switched to any one of the four designated information paths of each of NB1 to NB4. Alternatively, other arrangements may be used depending on the busbar traffic requirements between the networks. Space switching circuit 11
The six output terminals are each connected to one of the group of second half time slot selection circuits 118.

The selection circuit 118 is controlled by the system clock doubling signal from the system synchronization source 110 to transfer time slot presence information from the output of the space switch 116 to the network bus during the latter half of each time slot. be done. To accept information from user terminals coupled to other network buses, space switch 43 of FIG. 2 selects the requested information path within the network bus during the requested time slot, and The time slot existence information is transmitted from the information path to the half time slot selection circuit 51.
Send to the input section of. The selection circuit 51 is controlled by a signal sent over one of the conductors 29 and transfers the information present in the latter part of the time slot to the buffer 49.
Space switch 116 is controlled by data words generated by multiplex conversion controller 112.

This multiple converter control device includes buses 201, 202 and 2
It is similar to the control portion of network circuit 10 in that it generates time slot addresses to control calls to memory written by the CPU through 03. Next, in telephone systems, supervisory signals, dial tones, ring tones, etc. are typically required. In a PCM telephone system, these signals can be generated by a group of signal generators for generating analog signals, similar to typical analog telephone systems. The analog signal may be fed to one or more PCM encoders as needed and then inserted at the appropriate location in the system at the appropriate time. In the system of FIG. 1, any of the network circuits 10 can be replaced with various functional circuits.

Certain functional circuits may process time slot presence information signals appearing on the network bus or may transmit information signals to the network bus. One such circuit is the supervisory signal source shown in FIG. This supervisory signal source is a fixed memory (RO) of supervisory signal PCM words.
ROM 62 is controlled by a ROM controller 63 which is responsive to a main frame synchronization signal and a system clock signal provided via synchronization conductor 217. All supervisory signals such as dial tones and busy tones necessary for use in the system are stored in ROM 62 in PCM format. ROM62 is PCM on the PCM word bus line 64
It is controlled so that all the monitoring sound signals are generated one bit at a time. Each of the PCM supervisory signals appears on a designated conductor within busbar 64. Each information bit exists for the entire period of one frame, or n time slots. A supervisory signal controller 65, similar to memory 23 and associated circuit elements 20-24 in the network circuit of FIG. Generate above. The supervisory signal space switch 67 responds to an address provided by the controller 65 only during the first half of the time slot determined by the system clock doubling signal provided on one of the leads 217. By selecting the bits of the PCM word supplied from the word motherboard 64,
Generates a time slot presence information signal bit. Each of the selected information signal bits is transmitted to a predetermined information path within the network bus. Thus, the supervisory signal source of FIG. 5 produces a supervisory sound signal that is compatible with the system PCM word format shown in FIG. When operating as a TDMPCM telephone switching system, simple telephone calls are
evenis).

The TIU is a network circuit 10 combined with the TIU.
is addressed or scanned by time slot (TS) 101I. Phone answers (0ff-HOOk)
Then, the TIU connected to this becomes FWl in TSOOl.
1 bit, which stops scanning from the network circuitry the moment a particular TIU is scanned. In response to the cessation of scanning by the peripheral signal device 210Gζ network circuit, the 111 bits in the next
send to The subsequent TSllO[t-C-TIU continuously sends the answer status signal of the user telephone to the peripheral signaling device.
When the transmission of this signal is finished, the peripheral signal device starts scanning for other terminals again and sends an input interrupt signal to the CPU via the integrated line in the control bus 203. When you are ready to talk,
The CpU accepts signal data and terminal addresses from the PIU 2IO and its associated network circuitry in response to the interrupt signal. Next, the CPU operates as follows. That is, (a) the terminal address including the TIU address and the supervisory sound signal circuit network path address is loaded into the time slot address position of the network circuit memory 23, and (b) the same time slot address position of the supervisory signal control device 65 is loaded. Load the address of the tone PCM word into. Thereafter, while the time slot is occurring again, supervisory signal space switch 67 sends the PCM tone signal from the ROM to one transmission line in the network bus. T.I.
U is enabled during the playback of each time slot by control of the network circuit memory. A space switch controlled by the network circuit memory extends the appropriate network path from the network circuit to the outgoing path and
U receives the PCM dial tone signal and transmits an analog dial tone to the telephone. Upon receiving the dial tone, the telephone operates by the user dialing the desired telephone number in the usual manner.

The dialing signal is transmitted in the subsequent TSlOl. In the case of dial pulses, each dial pulse requires a series of consecutive TS8Olls for its transmission.
Finally, the CPU accepts all of the dialing information, verifies that the dialed subscriber is connected to the network circuit, and loads the called subscriber's 7 address into memory during TS8O1. According to instructions from the CPU, P
The IO is the called subscriber's 2 ↓ V God X during time slot zero;
'． ′;: enemy.゜? Sent from the monitoring signal circuit to the calling subscriber.

When the called party answers, the TIU stops providing ringing, and during time slot 1V0[t, an answer status signal is transmitted to the peripheral signaling device, which sends an interrupt signal to the CPU. When the CPU becomes ready to talk, it receives this information and responds to it. (i) cut off the ringer from the supervisory signal circuit; and load the terminal address and the network path addresses of both subscribers into a network circuit memory coupled to the terminal; The system is configured and operated to provide flexibility in that a variety of features can be added. For example, one of the network circuits can be provided with a music-on-hold characteristic or a conference characteristic by replacing one of the network circuits with the required characteristic circuit.Alternatively, these characteristics can be added to the network circuit. It can also be provided by a circuit connected via a path and an output path. One such circuit is described in Japanese Patent Application No. 51-44518 by the same applicant as the present applicant. The system utilizes time delays to exchange signal bits between time slots in a fixed pair of time slots.

A time delay of n/2 time slot periods is written,
Also listed is a time delay of n±1 time slot periods. The latter is compared to a time delay of n/2, and C
The idea is to simplify the software in the PU somewhat. Therefore, in the above specific example of the present invention, n±
A time delay of one time slot period has been described. still,
A supplementary explanation of the typical operation of the system of the present invention is as follows.

First, the user terminals 311 and 500 are enabled when each unique terminal address is sent to them, and send information bits to the input path 12 and receive information bits from the output path 13.

In the first aspect of the present invention, the terminal addresses of the two user terminals 311, 500 to be connected are CPU2OO
etc., in the even numbered positions of the memory means 23 and the following odd numbered positions, for example positions a and b.

Depending on the time slot address, the memory means 23:
During time slot period a, the user terminal 31 on the calling side
1, followed by the terminal address of the user terminal to be called in time slot period b. By receiving the terminal address, the calling user terminal 311 starts the time slot period a.
Then, the information bit is sent to the input path 12, and the used end of the called side is sent in the same way. The terminal 500 sends information bits to the input path 12 during time slot b.

These information bits are stored in the storage means 40 in this order.
is memorized. By means of the transmission means 41, information bits received during the occurrence of even timeslot addresses (e.g. the information bits of the user terminal 311) are delayed by n+1 timeslot address periods and sent to the output path 13.
Information bits transmitted to and accepted during odd time slot address occurrences (e.g., the terminal 500 used above)
information bits) are transmitted on output 13 with a delay of n-1 time slot address periods.

Here, n is an even number equal to the number of time slots in one frame. As a result, the information bits of the calling user terminal 311 sent to the input path 12 during the time slot period a are sent to the output path 13 during the time slot period b of the next frame, and similarly. The information bits of the called user terminal 500 sent to the input path 12 during the time slot period b will be sent to the output path 13 during the time slot period a of the next frame. A concrete explanation of this is as follows.

Assume that the number is n-32. It is assumed that respective information bits are stored in the memory means 23 at even-numbered positions followed by odd-numbered positions, for example positions 2 and 3. The information bits of the calling user terminal 311 sent to the entry path 12 in the time slot period 2 are 33 (-32 + 1).
), and output path 1 is delayed by the time slot period 3 (-2+33-32) of the next frame
Sent on 3rd. The information bits of the called user terminal 500 that are sent to the input path 12 in time slot period 3 are delayed by 31 (-32-1) time slot periods and are transferred to the time slot of the next frame. Period 2 (-3
+31-32) and sent out to outlet 13. The user terminal 500 on the called side is in time slot period b(3).
The calling user terminal 311 receives the information bits sent to the output path 13 during the time slot period a(2), that is, the information bits of the calling user terminal 311. That is, the information bits of the user terminal 500 on the called side are accepted, and thereby the information bits are exchanged between the two user terminals 311 and 500.

In the second aspect of the present invention, the terminal addresses of the two user terminals 311, 500 to be connected are CPU2OO
etc., are respectively stored in storage positions, position c and position d, of the memory means 23, which are separated by a position interval of n/2-1.

Here, n is an even number equal to the number of time slots in one frame, as in the embodiment described above. Based on the time slot address, the memory means 23 outputs the terminal address of the calling user terminal 311 in the time slot period c, and outputs the terminal address of the called user terminal 500 in the time slot period d. . Here, time slot period C and time slot period d are time slot periods separated by n/2-1 time slot periods. Calling side user terminal 31
The information bit of 1 is sent to the input path 12 during the time slot period c, and the information bit of the called user terminal 500 is sent to the input path 12 during the time slot period c, and is stored in the storage means 40. . These information bits are then sent from the storage means 40 to the output 13 with a delay of n/2 time slot periods. In this aspect,
Since all information bits are delayed by the same amount of time, i.e., n/2 time slot periods, there is no need for a transmission line 41 with a selective delay function. As a result, the information bits of the calling user terminal 311 sent to the input path 12 during the time slot period c are sent to the output path 13 during the time slot period d of the same frame. The information bits of the called user terminal 500 sent to the input path 12 at time d will be sent to the output path 13 during time slot period c of the next frame. A concrete explanation of this is as follows.

Assume that n=32. It is assumed that respective information bits are stored in the memory means 23 at storage locations, location 4 and location 20, which are separated by a location interval of n/2-1=15. The information bits of the calling user terminal 311 sent to the input path 12 in time slot period 4 are 16(-3
2/2) Delayed by the time slot period, output path 1 is delayed by the time slot period 20 (-4+16) of the same frame.
Sent on 3rd. Entry route 12 in time slot period 20
The information bits of the called user terminal 500 that are sent to the next frame are delayed by 16 time slot periods so that the information bits of the called user terminal 500 sent to
2) is sent to the outlet 13. The user terminal 500 on the called side starts the exit route 1 in the time slot period d(20).
3, that is, the information bit of the calling user terminal 311, the calling user terminal 311 receives the information bit sent out to the output path 13 during time slot period c(4), that is, the information bit of the calling user terminal 311. The information bits of the user terminal 500 on the called side are received, and thereby the information bits are exchanged between the two user terminals 311, 500.

The second aspect of the present invention is superior to the first aspect in that it does not require the transmission means 41.

As described above, in the first aspect of the present invention, it is necessary to use the transmission means 41 for selecting the delay time depending on whether it is an even number or an odd number. In contrast, in the second aspect of the present invention, all delay times are the same, so there is no need to use means such as the transmission means 41. On the other hand, the first aspect of the present invention is superior to the second aspect of the present invention in that the software used can be simplified, as described above. This is, for example,
In a second aspect of the invention, when connecting two user terminals, a search is made as to which of the pairs of storage locations separated by n/2-1 of the memory means 23 are available. In contrast, in the first aspect of the present invention, it is only necessary to search which pairs of adjacent storage locations are available.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a TDMPCM switching system according to the present invention. FIG. 2 is a detailed block diagram of a portion of FIG. 1. FIG. 3 is a detailed block diagram of a portion of FIG. 1. FIG. 4 is a detailed block diagram of a portion of FIG. 1. FIG. 5 is a detailed block diagram of a portion of FIG. 1. FIG. 6 shows a PCM format applicable to the system of FIG. 10... Exchange network, 12, 12a... Entry path, 13, 13a.
... Output, 70...Terminal control buffer circuit (T
CB), 100...Multiple transmission, 200...
...Central processing unit (CPU), 210...
Peripheral interface unit (PIU), 301, 302
...Terminal interface unit (TIU).

Claims (1)

[Claims] 1. A switching network 1 connected to a plurality of user terminals 311, 500 via input paths 12, 12a and output paths 13, 13a.
0 and P having m information bits each between
Central processing unit (CPU) for controlling the exchange of commercial words
200, a TDM PCM communication system comprising: means 20 for generating a sequence of n even timeslot addresses forming a frame; and memory means 23 having the n timeslot addressable word locations.
memory means 2 for storing terminal addresses from the CPU and transmitting terminal addresses to the user terminal in response to each occurrence of a time slot address;
3; storage means 40 for receiving information bits from said input path during each occurrence of said timeslot address; n+1 information bits received during occurrences of even numbered timeslot addresses; transmitting means 41 for transmitting information bits received during occurrences of odd time slot addresses with a delay of n-1 time slot address periods; means 320 responsive to transmitting, in association with each of the user terminals, each of its own terminal addresses;
means 320 for accepting information bits from the output path 13a and transmitting information bits onto the input path 12a;
, whereby the m-bit PCM word is transmitted to one of the user terminals to which the terminal address in the word position corresponding to the even timeslot address is transmitted and immediately following the even timeslot address. A TDM PCM communication system characterized in that a terminal address in an adjacent word position corresponding to the odd time slot address of is exchanged bit by bit with another one of the user terminals to which the terminal address is transmitted. . 2. The storage means is connected to an input terminal connected to the input path and to a stage for producing a delay of n+1 time slot periods and a delay of n-1 time slot periods in the communication system, respectively. a shift register 40 having first and second output terminals, and said transmission means outputs said first or second output in response to whether the instantaneous timeslot address is even or odd. The TDMPCM communication system according to claim 1, further comprising a selection circuit 41 for selecting information bits to be transmitted from the terminal. 3. A switching network 1 connected to a plurality of user terminals 311, 500 via input paths 12, 12a and output paths 13, 13a.
0 and P having m information bits each between
Central processing unit (CPU) for controlling the exchange of commercial words
200, a TDM PCM communication system comprising: means 20 for generating a sequence of n even timeslot addresses forming a frame; and memory means 23 having the n timeslot addressable word locations.
memory means 2 for storing terminal addresses from the CPU and transmitting terminal addresses to the user terminal in response to each occurrence of a time slot address;
3: in a TDMPCM communication system comprising: accepting information bits from said input path during each occurrence of said timeslot address;
storage means 40 for delaying transmission by two time slot address periods, and means 320 for being responsive to the transmission of each of its own terminal addresses associated with each of said user terminals; and comprises means 320 for accepting information bits from said output path 13a and transmitting information bits onto said input path 12a, whereby m
TDM characterized in that bit PCM words are exchanged bit by bit between the user terminals each enabled in two time slot periods each separated by n/2-1 time slot periods. PCM communication system.