JPS59146262A - System for deciding and processing binary/multi-value picture area - Google Patents

Abstract

PURPOSE:To offer a processing system of high speed specification exceeding the performance of an exclusive processor by performing the discriminating processing of binary/multi-value picture area by a local vicinity arithmetic exclusive processor for multi-value picture and by an external discriminating circuit, to realize easily the discrimination of the binary/multi-value picture area. CONSTITUTION:In the figure, 20-20' and 23-23' constitute a processing image buffer 24 having hour sets of 4-bit width as an alternate buffer form. 25-25''' are processors and they are controlled to obtain a maximum and a minimum value respectively, and a picture data for 4 picture elements' share of each scanning line is applied in parallel from the image buffer. The result of arithmetic is transferred among the processors via each linkage unit respectivey, and the maximum value and the minimum value in 4X4 picture elements are outputted as an output of the processor 25''' of the 4th stage. After the maximum value is latched once in a register 26, the difference with the minimum value outputted in the next timing is used at an arithmetic circuit 27 and the result is compared with a threshold value Po for binary/multi-value decision at an arithmetic circuit 28, allowing to obtain a command signal for separating the binary/ multi-value picture area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a binary/multilevel image area determination processing method, and particularly to a high-speed preprocessing method for encoding/decoding image data in facsimile and the like.

[Prior art]

When transmitting multivalued images such as photographs as digital signals using image data transmission devices such as facsimiles,
It is known that encoding efficiency can be improved if multi-level images and binary images are identified and encoded.

A known determination method will be explained using FIGS. 1 and 2. FIG. 1 shows the definition of screen coordinates, where the horizontal direction is the main scanning direction used in facsimiles and televisions, and is called the vertical direction or sub-scanning direction. 1) Each 1 in 1 figure means 1 pixel, and the above-mentioned binary/multiple images are judged in units of ↓ strokes x 4, which are surrounded by a thick frame.

The second one is the one extracted from the 1lj-th block (hereinafter referred to as 10 blocks) of this 4-way x4 image (, # in this printer).
Maximum value (Dmax) and minimum value (D m-i, m
) is calculated, and this difference P is calculated based on the standard and 7. J: concentration 1・
. If it is larger than Po, it is determined that the flock is binary, and if it is smaller than Po, it is determined that it is a multivalued image.

There is no known processing power formula suitable for making this determination.

FIG. 3 shows Ii! which is suitable for performing local neighborhood calculations. This processor is an 8-pin l-/il! Data unit 2 consists of four sets of shift registers 1 as the data path for Ij, and 8-bit x 1 [3 x 4-byte RAM (random access memory) for storing coefficients, template data, etc. for M ), an adder (A
Processor units 1-7 consisting of LU) 4 and multipliers (MU+t) and multipliers (MU+t), each consisting of processor units 1-7 consisting of LU) 4 and multipliers (MU+t); AI, (J) A linkage unit 10 composed of two stages 8 and 9, an evaluation unit 11 for binarization and clustering, and a control unit 12 for controlling the overall calculation results. In this processor, (↑)
' L, 4 P E 6 can be operated in parallel,
(2) It is structured so that each arithmetic processing in the processor units 1 to 7 and the linkage output unit 10 can be processed by vibrating, and real-time processing can be performed on input images up to 6 Mbps. In addition, control unit 1
You can change the contents of various control registers in 2.
This makes it possible to perform most of the basic local neighborhood operations in C. However, this 1. , S
There is a high demand for performance that exceeds the I specifications.

[Purpose of the invention]

A first object of the present invention is to provide a processing method that easily realizes binary/multi-valued image area determination, and another object of the present invention is to provide a processing method with high-speed specifications exceeding the performance of the dedicated processor. is to provide.

[Summary of the invention]

The present invention combines the processor with an image processor for preprocessing, an arithmetic circuit, a latch, and a timing circuit,
Performs binary/multivalued image area determination processing.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. Fourth
The figure shows the block configuration of this embodiment.

In FIG. 4, 20 to 20', 2] to 2t'.

22 to 22' and 23 to 23' constitute the processing image buffer 24 having a width of 4 sets of 4 pixels 1, and are in an alternating buffer format. Each memory has 4 pixels for one scanning line
- width and can store 16 gradations. That is, while an input image from the outside is sequentially stored in the image buffer 24 for one scanning line for four scanning lines, one memory for four scanning lines can be used. 25 to 25'' are the aforementioned processors, and each processor 25 is supplied with image data in parallel from the image processor. Each processor is controlled to obtain the maximum value and the minimum value, and each scanning Image data for 4 pixels of a line is supplied.Arithmetic results are sequentially transferred between the 71 processors via linkers 1 to 1, and processors 25-1 of 4 stages [1]
The maximum output is 111. within 4 pixels x 4 pixels. and output the minimum value. After this maximum value is latched into the register 26, the difference between the minimum values output at the next timing is taken by the arithmetic circuit 27, and this result is further used for binary/multi-value determination. Uj P. By comparing the values in the arithmetic circuit 28, a command signal for binary/'multivalued image region separation is obtained by 1ζ1. Since this signal changes with the input of the next image data, it is temporarily stored in the 2-notch 29, and is pre-processed through the area reservation circuit 31 provided with a counter 3θ so that its value can be updated at 1-pron.fi↓. to circuit 32. In this way, by using this processor in combination with several logics, ordinary MSI, SS
1-) It is possible to realize a 21-digit/multi-level image head area processing circuit with much simpler and fewer circuits than using I.
An example of the use of this output signal of order Q4 from C1 to Q will be described with reference to FIGS. 5 and 6. Figure 5. Binarization and dithering by region separation 4 scanning lines 1fiJ H4
Process to J.

As shown in the 51st one-stage block, U + 戊 for one scanning line is a dither threshold value and ζ registers 40 and 40' that hold the threshold values for z-value conversion, and their outputs are converted into binary values. /'Switch selected by the dither command signal, comparator circuit 42 that performs the ratio vJ)L between the human input data and the threshold value, and the shift register 43 that converts the output from serial to parallel in order to transfer it to the encoding circuit. It consists of 2 consisting of these
The value converting circuit is used for four scanning lines from 111 to 47. Note that the hit delay circuit 41 (ξ) is a circuit for synchronizing with the determination process. Note that a predetermined value is set in the threshold register when the system is initialized.

Figure 6 shows the above operation, and the linkage output for each image input is arranged as shown in the figure. At the fifth timing from the left, no image input is performed and the maximum value output operation is performed. At the next timing, the minimum value is output, and at the same time, the image data of the next block is input, and the next block is judged. This is due to the pipeline processing inside the processor.

As explained above, according to the present embodiment, the local neighborhood arithmetic processing processor can easily realize binary/multivalued image processing, and the capabilities of the processor can be It has the effect of increasing power.

Total ability = m body ability

〔Effect of the invention〕

According to the present invention, binary/multivalued area determination can be easily performed.
), it also has the effect of being applicable to high-speed specifications that exceed the capabilities of the processor used.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram showing the relationship between the screen, coordinates, and blocks, which are the premises of the area determination method for binary/multivalued images.
Explanatory diagram showing a known binary/multivalued image area determination method, 3rd
4 is a block diagram of an embodiment of the present invention. FIG. 5 is a block diagram of a binary/dither selection circuit to which the present invention is applied. FIG. 6 is an example of the operation timing diagram of FIGS. 4 and 5. 24...Image battle, 25...Processor,
26...Latch, 27...Arithmetic circuit, 28...Arithmetic circuit, 31...Block reservation amount drawing engraving (no change in content) Kaya 2 eyes P 2 I) 艷欅-p arcl bamboo PgPo Mehiki z4DirectP<f', Nohigi Polysulfur grass 3 Ward sheep 5. = Goose? () 25 34 No. 52 2-96 (/-Design Jγi Delusion No. Z B Procedure Correction Sound (Method) 1shi,・1() Long 1.1 I〒 Kazuo Sugi
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)−・″) Month 9↓ (1) Oath to prove authority of attorney (2) All of the specifications and drawings /−1゛/ 11゛・idi ll −′) Within 100

-"8 (1,1 Submit a power of attorney. (2) Engraving of the specification and drawings (no changes to Yamaya).

Claims (1)

[Claims] 1. A binary/multilevel image area determination processing method characterized by performing binary/multilevel image area determination processing using a processor dedicated to local neighborhood calculations for multilevel images and an external determination circuit.