JPS59144926A - Backup power supply circuit - Google Patents

Backup power supply circuit

Info

Publication number
JPS59144926A
JPS59144926A JP58018128A JP1812883A JPS59144926A JP S59144926 A JPS59144926 A JP S59144926A JP 58018128 A JP58018128 A JP 58018128A JP 1812883 A JP1812883 A JP 1812883A JP S59144926 A JPS59144926 A JP S59144926A
Authority
JP
Japan
Prior art keywords
power supply
analog switch
load
backup
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58018128A
Other languages
Japanese (ja)
Other versions
JPH059813B2 (en
Inventor
Minoru Machida
稔 町田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP58018128A priority Critical patent/JPS59144926A/en
Publication of JPS59144926A publication Critical patent/JPS59144926A/en
Publication of JPH059813B2 publication Critical patent/JPH059813B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Direct Current Feeding And Distribution (AREA)

Abstract

PURPOSE:To execute a backup operation so that load operation at the time of backup power supply can be guaranteed over a long period by always supplying so that the optimum power supply voltage originaly required by a load even at the power supply by a main power source or at the power supply by backup. CONSTITUTION:When a main current supply VCC is applied to a power supply terminal 1, the VCC is supplied to a load through a diode D1. Since the power is simultaneously supplied also to an analog switch element 4 through a line 41, the element 4 is turned to an operation enabled state. A high level signal is applied to a control terminal C2 through a resistor R1 under said state, so that an analog switch circuit SW2 is closed and a low level signal is applied to a control terminal C1. Consequently, the analog switch circuit SW1 is opened again and a battery 2 is disconnected from a power supply line.

Description

【発明の詳細な説明】 技術分野 本発明はバッテリー静音用いlζバンクアンプ給電回路
に関する。
DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a battery silent lζ bank amplifier power supply circuit.

従来技術 負荷に重力を供給する主電源が停電または障害によって
突然給電不能になっても別設したバッテリー等から主1
1゛こ代って電力を供給し、しかも負荷側から見れば給
電源がスムーズに入れ替ることによって連続して動作可
能であるところの、いわゆるバックアップ給電回路があ
る。
Conventional technology Even if the main power supply that supplies gravity to the load suddenly becomes unable to supply power due to a power outage or failure, the main power supply can be restored from a separately installed battery, etc.
There is a so-called backup power supply circuit that supplies power on behalf of the load and can operate continuously by smoothly replacing the power supply from the load side.

かかるバンクアップ給電回路には大型コンピュータ無停
電ンステムのCVCF電源に用いられるものから小型の
電子機器に内蔵されるもの等種々のものがあるが5いず
れにしても電力全スムーズに供給しつづけることによっ
て負荷に安定なる動作の継続を保障するだめのものであ
る。本発明は後者の電子機器に内蔵されるようなバック
アップ給電回路に関する。
There are a variety of such bank-up power supply circuits, from those used in CVCF power supplies for large computer uninterruptible systems to those built into small electronic devices. This is to ensure continued stable operation under load. The present invention relates to a backup power supply circuit built into the latter electronic equipment.

第1図は従来技術によるバックアンプ給電回路でおる。FIG. 1 shows a back amplifier power supply circuit according to the prior art.

主電源V。0は給電端子工に供給されダイオード”DI
’に介して負荷端子3に導ひかれる。負荷は例えばC−
MO8RAM から5y、υ記憶の保存を目的とする場
合が多い。主電源V。0が+5Vであればダイオードの
順方向電圧降下(以下vFと呼ぶ)は0.4 V〜0.
6Vであるから9荷端子3にはほぼ4.4Vが給電され
る。2はバックアンプ給電用の例えばリチウム電池でそ
の出力電圧は通常3.0V〜3.5vである。よってバ
ックアップ給電、路にあるダイオード”D2は逆方向に
バイアスされてOFF状態にある。この状態でダイオー
ド”D2にはわずかながら逆電流が流れるが、この量i
−i温度上昇に伴って急激に増大する。特にC−MOS
素子−の如き小電流負荷を非動する主電源−・Vccで
あれは電源容量も小をくこの逆電流の増大も無視し得な
い場合がある。
Main power supply V. 0 is supplied to the power supply terminal and the diode "DI"
' is led to the load terminal 3 via '. For example, the load is C-
MO8RAM to 5y, is often used for the purpose of preserving υ memory. Main power supply V. If 0 is +5V, the forward voltage drop of the diode (hereinafter referred to as vF) is 0.4V to 0.
Since the voltage is 6V, approximately 4.4V is supplied to the terminal 3. 2 is a lithium battery, for example, for powering the back amplifier, and its output voltage is normally 3.0V to 3.5V. Therefore, the diode "D2" in the backup power supply path is biased in the reverse direction and is in the OFF state. In this state, a small amount of reverse current flows through the diode "D2, but this amount i
-i Increases rapidly as temperature rises. Especially C-MOS
In the case of a main power supply Vcc that does not operate a small current load such as an element, the power supply capacity is small and the increase in reverse current cannot be ignored in some cases.

次に主電源vccが何らかの理由によって連断されると
給電路を失った負荷端子3の電圧も漸減する。この速度
は負荷回路に含まれるコンデンサや負荷電流にもよるが
、やがてダイオードD2が順方向にバイアスされるまで
重圧が下ると負荷端子3にはリチウム電池2からの給電
路が形成される。
Next, when the main power supply VCC is disconnected for some reason, the voltage at the load terminal 3 that has lost its power supply path also gradually decreases. Although this speed depends on the capacitor included in the load circuit and the load current, when the heavy pressure eventually decreases until the diode D2 is biased in the forward direction, a power supply path from the lithium battery 2 is formed at the load terminal 3.

これを経時的に見れは、電電1源Vcoによる給電から
リチウム電池2による給電に至って負荷端子3の重圧が
漸減し、かつこれら直電圧4.4v〜2.9■において
負荷回路は正常に動作可能である。とするものである。
Looking at this over time, we can see that the heavy pressure on the load terminal 3 gradually decreases from power supply from the power source 1 Vco to power supply from the lithium battery 2, and the load circuit operates normally at these direct voltages of 4.4V to 2.9V. It is possible. That is.

かかるバンクアップ給電回路社簡単なt@成でその目的
を達するものであるが、前述した如く主電源V。0によ
る給電時にターイオート’ D 2 ’に介して漏れる
逆−電流の温度依存性およびバンクアンプ給電時にダイ
オード”D2に生する比較的大きなVF(0,4V〜0
.6 V )は負荷回路の安定な動作を維持するために
は無視し得ない場合もある。これは、主電源給電路に比
べて常にこれより電圧の低いバンクアンプ給電路を併設
しなくてはならないというダイオード”D2を用いた従
来技術の本質的な欠点にも起因する。
This purpose can be achieved by simply constructing such a bank-up power supply circuit, but as mentioned above, the main power supply voltage V. The temperature dependence of the reverse current leaking through the terminal 'D2' when power is supplied by the bank amplifier and the relatively large VF (0.4 V to 0
.. 6 V) may not be negligible in order to maintain stable operation of the load circuit. This is also due to the essential drawback of the prior art using the diode "D2" that a bank amplifier feed line with a voltage lower than the main power supply line must always be provided.

目的 本発明は上述従来技術の欠点に鑑みてなされたものであ
ってその目的とするところは、上述欠点を無くし主電源
の給電時にもあるいはバックアンプ給電時であっても本
来負荷が要求するところの最適電源電圧を常に給電可能
とすることによシ、。
Purpose The present invention has been made in view of the above-mentioned drawbacks of the prior art.The purpose of the present invention is to eliminate the above-mentioned drawbacks and to solve the problems originally required by the load even when the main power supply is being supplied or when the back amplifier is being supplied. By making it possible to always supply power at the optimum power supply voltage.

判にバックブラダ給1時の負荷動作を長期間にわたって
保証し得るバックアップ給電回路を提案することにある
The object of the present invention is to propose a backup power supply circuit that can guarantee load operation during back bladder supply for a long period of time.

実施列 以下図ituに従って本発明の一実施例を詳細に説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the figures.

第2図は本発明に係る一実施例のバッファラフ給紙回路
図である。図において主電源Vccの給電路は給電端チ
ェからダイオードDht介して負荷端子3に至る。主電
源■。。が負であれは勿論ダイオード”DIの向きも反
転する。一方バツクアップ給亀路はアナログスイッチ素
子4により構成されている。例えはモトローラ社のC−
MOSアナログスインテ素子MC14066Bである。
FIG. 2 is a buffer rough paper feeding circuit diagram of an embodiment according to the present invention. In the figure, the power supply path of the main power supply Vcc extends from the power supply terminal Che to the load terminal 3 via the diode Dht. Main power ■. . If is negative, of course the direction of the diode DI is reversed.On the other hand, the backup supply path is constituted by an analog switch element 4.For example, Motorola's C-
This is a MOS analogue integer element MC14066B.

ここでアナログスイッチ素子4の概略を説明すると、第
3図にはその論理回路図が、また第4図には第3図の回
路動作の一理値表が夫々示されている。アナログスイッ
チ素子4の基本構成は第3図に示す3端子回路であり、
入力端子Iと出力端子Oおよび該入力端子1.O間に介
在するアナログスイッチ回路SWから成る。アナログス
イッチ回路swは制御端子Cからの信号によって開放ま
たは閉成状態に保たれる。第4図はこの関係を示すもの
であって、制御端子CにLOレベルが印加されれはアナ
ログスイッチ回路SWは開放0FFL、またHIレベル
が印711されれハhj成ONする。該アナログスイッ
チ回路SWはその開放B4VこはWtν線(1,抗を1
000MΩ以上とし、その閉成時には路線抵抗を300
Q以下とすることによって上述ス・fンテの動作を実現
するもので必る。開成時にアナログ信号をも低損失で通
過させるようなこの屯気的持性はリレー等による接点特
性にも匹敵し、かつ機械的な構造や動作を要しないし、
電気的特性にも劣化が無いから半永久的に高速、安定な
るスイッチ動作が得られるという効果がある。2はバン
クアンプ給電路の給電源である。各柚電池が使用可能で
ろり祉だ光が得られるならンーラバンテリでも良い、そ
してその転圧も上述従来技術にあるような制限を受ける
ものではない。
To give an overview of the analog switch element 4, FIG. 3 shows its logic circuit diagram, and FIG. 4 shows a logical value table for the operation of the circuit shown in FIG. 3. The basic configuration of the analog switch element 4 is a three-terminal circuit shown in FIG.
Input terminal I, output terminal O, and input terminal 1. It consists of an analog switch circuit SW interposed between the two terminals. The analog switch circuit sw is kept open or closed by a signal from the control terminal C. FIG. 4 shows this relationship; when the LO level is applied to the control terminal C, the analog switch circuit SW is opened 0FFL, and when the HI level is applied 711, the analog switch circuit SW is turned ON. The analog switch circuit SW has its open B4V connected to the Wtν line (1, resistive to 1
000MΩ or more, and the line resistance when closed is 300MΩ.
It is necessary to realize the above-mentioned operation by setting the value to be less than or equal to Q. This ability to pass analog signals with low loss when open is comparable to the contact characteristics of relays, etc., and does not require mechanical structure or operation.
Since there is no deterioration in electrical characteristics, there is an effect that high-speed and stable switch operation can be obtained semi-permanently. 2 is a power supply for the bank amplifier power supply path. As long as each Yuzu cell can be used and a bright light can be obtained, Nuravanteri may be used, and its compaction is not subject to the limitations as in the above-mentioned prior art.

以上の構成において以下にその動作、作用を説明する。The operation and effect of the above configuration will be explained below.

給電端子1に主電源v。0が印加されているときはこれ
か夕゛イオートl)1.’fi:介して負荷に給電され
る。lた同時にアナロクスづツテ紫子4もライン41(
こよって給電されるから動作b」能状態にある。この状
態で制御端子C2には抵抗RL f介してH■レベルが
印加されるから、アナログスイッチ回路SW2は閉眩し
制御端子CIにはLOレベルが印加される。よってアナ
ログスイッチ回路SW1は開放しバッテリ2をバンクア
ンプ給電路から遮断する。遮断時の路線抵抗は1001
00O以上でらるから負荷端子3からバッテリ2に向け
て漏n;b電流があってもその針は極めて小さい。
Main power supply V to power supply terminal 1. When 0 is applied, this is the default.1) 'fi: Power is supplied to the load via. At the same time, Analogs Zutsute Shiko 4 also line 41 (
Since it is supplied with power in this manner, it is in an operational state. In this state, the H level is applied to the control terminal C2 via the resistor RL f, so the analog switch circuit SW2 is closed and the LO level is applied to the control terminal CI. Therefore, the analog switch circuit SW1 is opened and the battery 2 is cut off from the bank amplifier power supply path. The line resistance at the time of interruption is 1001
Since the voltage is 000 or more, even if there is current leaking from the load terminal 3 toward the battery 2, the needle is extremely small.

まだC−MUSのアナログスイッチ素子4においては制
御端子CIに流れるバイアス電流も極めて小さい(nA
−pAオーダ)。さらにまたこの状態でアナログスイッ
チ回路SW2には抵抗R2t−介して電流が流れる。こ
の抵抗R2は後述するアナログスイッチ回路SW2のO
FF 時に制御端子CIにl(Iレベルを印加するだめ
のプルアップ抵抗であるが、前述した如く制御端子C1
に流れるバイアス電流は極めて小さいものであるからこ
の抵抗値を極めて大きなものとすることが可能である。
In the C-MUS analog switch element 4, the bias current flowing to the control terminal CI is still extremely small (nA
-pA order). Furthermore, in this state, a current flows through the analog switch circuit SW2 via the resistor R2t-. This resistor R2 is O of the analog switch circuit SW2, which will be described later.
It is a pull-up resistor that is used to apply the I level to the control terminal CI during FF, but as mentioned above, the control terminal C1
Since the bias current flowing through is extremely small, it is possible to make this resistance value extremely large.

いずれにしても抵抗R2の抵抗値、らるいは制御端子C
1に流れる電流の各温度依存性は前述ダイオート”D2
の逆電流のそれに比較して極めて小さいものであるから
、第2図において負荷端子3からバックアップ給電路に
供給される電流量はその温度依存性が極めて小さくかつ
予測可能である。
In any case, the resistance value of resistor R2, or the control terminal C
The temperature dependence of the current flowing through the diode "D2" described above is
2, the amount of current supplied from the load terminal 3 to the backup power supply path in FIG. 2 has extremely small and predictable temperature dependence.

よってこの電流量を見込んだ主電源VCeであればたと
え亀源容餡゛が節約された最少限なものであっても、動
作周囲温度の上昇によって本来負荷に供給すべき電流が
不足してしまうような状態を防ける利点がある。
Therefore, if the main power supply VCe takes into account this amount of current, even if the main power source VCe is the minimum one that saves power, the current that should normally be supplied to the load will be insufficient due to the rise in the operating ambient temperature. This has the advantage of preventing situations like this.

次に主電源VCCの供給が伺もかの理由によって断たれ
ると負荷端子3の電位も漸減する。例えはC−MO8R
AM等、低消費電力の負荷でおれば負荷端子3の電位の
漸減もゆつくシと進む。この間に給電端子lの電位は急
減し抵抗R1を介して制御端子C2の電位’kLOレベ
ルにする。アナログスイッチ回路SW2は開放されるか
ら制御端子C1にはプルアップ抵抗R2’を介してf(
Iレベルが印加される。よってアナログスイッチ回路S
Wlが閉成し代りのバッテリ2から給電されるバンクア
ップ給電路が形成される。バッテリ2の電圧は主電源V
ccの値と同一でも良い。アナログスイッチ回路SWl
の路線抵抗は300Q以下であるから例えば1mAkバ
ンクアップ給屯してもSWIにおける電圧降下は0.3
 V以下であってターイオードのVF(0,4V〜0.
6 V )よりも小きい。またこれ以上の給電電流であ
れは、より高い電圧のバッテリ2を用いれば良い。よっ
て負荷回路には、主電源給電時にもまたバックアップ給
電時にも、負荷回路が本来要求するところの最適定格電
源重圧が常に得られるという利点がある。
Next, when the supply of the main power supply VCC is cut off for some unknown reason, the potential of the load terminal 3 also gradually decreases. For example, C-MO8R
If the load is a low power consumption load such as an AM load, the potential at the load terminal 3 will gradually decrease. During this time, the potential of the power supply terminal 1 decreases rapidly and becomes the potential of the control terminal C2 at the 'kLO level via the resistor R1. Since the analog switch circuit SW2 is opened, f(
I level is applied. Therefore, analog switch circuit S
When Wl is closed, a bank-up power supply path is formed in which power is supplied from the battery 2 instead. The voltage of battery 2 is the main power supply V
It may be the same as the value of cc. Analog switch circuit SWl
Since the line resistance is less than 300Q, for example, even if a 1 mAk bank up supply is applied, the voltage drop at SWI is 0.3
VF of the third diode (0.4V~0.
6 V). Furthermore, if the power supply current is higher than this, a battery 2 with a higher voltage may be used. Therefore, the load circuit has the advantage that the optimum rated power supply load originally required by the load circuit can always be obtained both during main power supply and during backup power supply.

効果 以上述べた如く本発明によれは、主電源による給Ik時
にもあるいtユバンクアンプ給電時にも、負荷が4来要
求するところの最適定格電源重圧を常に与えることが可
能である。これは1屯にバックアップ給電時の負荷の正
常なる動作を保証する効果がある。例えばC−MO8R
AMの動作を保証する電源電圧の最小値が2■であると
すれば、従来技術ではバッテリ重圧が2V+Vp(0,
4〜0.6V)となったときに当該バッテリの寿命と式
れる。しかるに本発明によれは、バッテリ電圧の上限値
は伺ら主電源砥圧値によって制限されるものではない。
Effects As described above, according to the present invention, it is possible to always provide the optimum rated power supply load required by the load, whether when the main power supply is supplying power or when the bank amplifier is supplying power. This has the effect of guaranteeing normal operation of the load during backup power supply. For example, C-MO8R
If the minimum value of the power supply voltage that guarantees AM operation is 2■, then in the conventional technology, the battery pressure is 2V + Vp (0,
When the voltage reaches 4 to 0.6 V), the life of the battery is considered to have expired. However, according to the present invention, the upper limit value of the battery voltage is not limited by the main power supply grinding pressure value.

極言すれは、C−MO8RAMの動作を保証する電源電
圧のほぼ最高値を有するバッテリ重圧いても良いから給
電寿命の長いバンクアップ給電回路を容易に提供できる
。勿論、従来技術と同一のバッテリ金柑いたとしても給
電電流が小さければアナログスイッチ回路SWlで生ず
る電圧降下がダイオードD2のVFに比べて十分に小さ
い力)ら負荷の動作保証供給車圧にしめるノくンテリ屯
圧の余裕が増えることによって相対的にノくツテリの寿
命が延びるという効果もめる。
To put it simply, it is possible to easily provide a bank-up power supply circuit with a long power supply life, since it is possible to use a battery having almost the maximum value of the power supply voltage that guarantees the operation of the C-MO8RAM. Of course, even if the same battery as in the conventional technology is used, if the power supply current is small, the voltage drop caused by the analog switch circuit SWl is sufficiently small compared to the VF of the diode D2. The increase in tonnage pressure margin also has the effect of extending the life of the notch.

まだ本発明によれば、特にC−MOSアナログスイッチ
素子をバックアップ給電路に用いれば、主電源vccに
よる給電路にバンクアンプ給電回路に流れる電流量も小
さい。かつ該電流量の温度依存性も極めて小さいから当
該バックアップ給電路の動作周囲温度が上昇してもバッ
クアップ給電路に余分な電流を取られる心配がない。こ
れはC−MO8RAMの如き低消費電力の負荷全可動す
るために設けられた主電源V。0であれは、予め電源容
量を必要最少限に節約したものとして構成することも可
能であるから、主電源の効率向上も計れるので特に小型
の電子機器においては効果を発揮する。
Still, according to the present invention, especially if a C-MOS analog switch element is used in the backup power supply path, the amount of current flowing into the bank amplifier power supply circuit in the power supply path by the main power supply VCC is also small. In addition, since the temperature dependence of the amount of current is extremely small, there is no fear that excess current will be drawn into the backup power supply path even if the operating ambient temperature of the backup power supply path rises. This is the main power supply V provided to run all low power consumption loads such as C-MO8RAM. If it is 0, it is possible to configure the power supply capacity to be saved to the minimum necessary in advance, so it is possible to improve the efficiency of the main power supply, which is particularly effective in small electronic devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来技術のバックアップ給電回路図。 第2図は本発明に係る一実施例のバックアップ給l・・
・給電端子、2川バツテリ、3・・・負荷端子、4・・
・アナログスイッチ素子、sw・・・アナログスイッチ
回路、Dl、D2・・・ダイオード、R1、R2・・・
抵抗である。 第1図 第2図 第4図 手 糸売 ネ市 ■ヨ 書(方メつ 1不和58年 6月 2日 一長官殿 り表示 特願昭58−18128号 2、発明の名称 バックアップ給電回路 3、補正をする者 事件との関係 特許出願人 キャノン株式会社 東京都大田区下丸子3丁目30番2号 理   人    〒105 東京都港区虎)門1−11−10 7令の日付 1右利58年5月31日 の対象 明細書の図面の簡単な説明の欄 /、袖IJ−の内容
FIG. 1 is a diagram of a backup power supply circuit of the prior art. FIG. 2 shows a backup supply l of an embodiment of the present invention.
・Power supply terminal, 2 river battery, 3...load terminal, 4...
・Analog switch element, sw...analog switch circuit, Dl, D2...diode, R1, R2...
It is resistance. Fig. 1 Fig. 2 Fig. 4 Hand Itouri Neichi ■Yo Calligraphy (Hometsu 1 Discord June 2, 1958) Patent Application No. 18128-18128 2, Name of Invention Backup Power Supply Circuit 3. Relationship with the case of the person making the amendment Patent applicant Canon Co., Ltd. 3-30-2 Shimomaruko, Ota-ku, Tokyo Address: 1-11-10 Toramon, Minato-ku, Tokyo 105 Date of the 7th Order: 1 Right Brief description of drawings column/, contents of sleeve IJ- of subject specification dated May 31, 1958

Claims (1)

【特許請求の範囲】 ■、 タイオードから成る主電源給電路と、バッテリに
直列接続されるアナログスイッチ手段から成るバックア
ンプ給電路を有し、前記主電源給電路とバックアップ給
電路が負荷側で接続したバラ出したときは前記アナログ
スイッチ手段を開放し。 また前記検出手段が主電源無しを検出したときは前記ア
ナログスイッチ手段を閉成することを特徴とするバンク
アップ給電回路。 2 アナログスイッチ手段かC−MOS素子から成るこ
とを特徴とする特約請求の範囲第1項に記載のバンクア
ンプ給電回路。
[Claims] (1) A main power supply line consisting of a diode and a back amplifier power supply line consisting of an analog switch means connected in series to a battery, the main power supply line and the backup power supply line being connected on the load side. When the sample is taken out, the analog switch means is opened. Further, the bank-up power supply circuit is characterized in that the analog switch means is closed when the detection means detects the absence of a main power source. 2. The bank amplifier power supply circuit according to claim 1, characterized in that the bank amplifier power supply circuit comprises an analog switch means or a C-MOS element.
JP58018128A 1983-02-08 1983-02-08 Backup power supply circuit Granted JPS59144926A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58018128A JPS59144926A (en) 1983-02-08 1983-02-08 Backup power supply circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58018128A JPS59144926A (en) 1983-02-08 1983-02-08 Backup power supply circuit

Publications (2)

Publication Number Publication Date
JPS59144926A true JPS59144926A (en) 1984-08-20
JPH059813B2 JPH059813B2 (en) 1993-02-08

Family

ID=11962964

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58018128A Granted JPS59144926A (en) 1983-02-08 1983-02-08 Backup power supply circuit

Country Status (1)

Country Link
JP (1) JPS59144926A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5723123A (en) * 1980-07-16 1982-02-06 Fujitsu Ltd Semiconductor device having volatile memory

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5723123A (en) * 1980-07-16 1982-02-06 Fujitsu Ltd Semiconductor device having volatile memory

Also Published As

Publication number Publication date
JPH059813B2 (en) 1993-02-08

Similar Documents

Publication Publication Date Title
US5726562A (en) Semiconductor device and power supply controller for same
KR940010419B1 (en) Semiconductor integrated circuit
US4617473A (en) CMOS backup power switching circuit
JPH035063B2 (en)
WO2007127922A1 (en) Sram leakage reduction circuit
KR960004001B1 (en) Single chip semiconductor memory
US20090195234A1 (en) On-chip voltage supply scheme with automatic transition into low-power mode of msp430
JPS6238026A (en) Power only setting circuitry
JPH0115956B2 (en)
JP3195052B2 (en) Power supply switching circuit
KR910007128A (en) Programmable Logic Integrated Circuits, Power Supplies and Power Supply Methods
JPS59144926A (en) Backup power supply circuit
US5604709A (en) Persistent data storage which utilizes a shared power supply
US5815455A (en) Power supply interface circuit providing nonvolatile storage with suitable operating and standby voltage levels
RU2020613C1 (en) Storage with data save facility at de-energization
EP0902294B1 (en) A voltage monitoring circuit
JPS58114B2 (en) memory device
JPS60140412A (en) Memory backup circuit
US5708388A (en) Single current source current generating circit for periodically activating and deactivating portions of an IC
JPS63186314A (en) Memory back-up circuit
KR200142920Y1 (en) Memory backup circuit
JP2508085B2 (en) IC card
KR970006017B1 (en) Automatic backup circuit of personal computer
JP2655766B2 (en) Information card
JPH01128110A (en) Memory card