JPS59141848A - Data pass control circuit - Google Patents

Abstract

PURPOSE:To obtain a data pass control system with high efficiency and high reliability by transmitting only the data including a data packet or the parts before and after said data packet to the next station when the data is transmitted over the stations in a loop or bus form cascade connection. CONSTITUTION:If a false header X emerges before a real data packet for the output of a shift registe 20; a decoder 21 outputs a wrong header detection pulse N'2 in the form of a signal DSDT. Then a flip-flop 23 is set at a high level. Meanwhile, the pass data passed through an AND gate 32 is supplied to a memory 25. However, a pulse N2 is outputted when the header of a real data packet is supplied. An RS flip-flop 23 is kept at a high level, and the signal DSDT or FTDT is applied with OR through an OR gate 31 and is supplied to a clear terminal of the memory 25. Thus the data is cleared. In such a way, only the real data packet passes through stations.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a wireless communication system in which a plurality of stations are cascade-connected in a loop or bus-like manner via a transmission line.
At each station, the data bus control circuit takes in necessary data from among the data passing through the station.

Conventional configuration and its problems The conventional data bus control system is shown in Figure @1 and Figure @2. 1 is a shift register which is a data bus control circuit for passing data to the next station, 2 is a reception processing circuit including a reception bus sofa, 3 is a transmission processing circuit including a transmission buffer, and 4 is a station consisting of a microcomputer. The control circuit is a switching circuit that uses the output of the transmitter circuit 3 as station transmission data only when transmitting data from the terminal 6, which will be described later, and outputs the shift register 1 at other times. @Figure 2 [al is a data packet transmitted through the network, and indicates the beginning of the data packet, destination address, source address, and data.

and a chain indicating the end of the data package soto. Figure 2 tbl is an example in which a ``1 da H'' is lost due to a data error etc. immediately before the true data packet. show.

@1 As shown in FIG. 1, a received signal from an upper station is input to a shift register 1 and a reception processing circuit 2. In the reception processing circuit 2, if the destination address of the data packet shown at ta+ in @2 matches its own address, the reception processing circuit 2 takes it into the station and sends it out to the terminal 6 or the like. On the other hand, the received data propagates through the shift register 1 and is input to the switching circuit 5. The switching circuit 5 receives transmission data from the terminal 6 and uses the transmission processing circuit 3 as an input while the transmission processing circuit 3 is transmitting data, and otherwise inputs the shift register 1 and passes the received data.

However, since this conventional station simply passes the data packet through the shift register 1, as shown in FIG.
As shown in bl, +CI, even an erroneous data packet passes through the station as an erroneous data packet.When stations are connected in a cascade, the errors are added up, and especially when the stations are connected in a loop, the erroneous data packet is Since the data goes through the loop many times,
This had the disadvantage of delaying the return of non-sotowork to normal operation.

Purpose of the Invention This invention is an object of the present invention, when passing data over stations cascaded in a loop or a bus, passing only the data including the data packet or its surroundings to the next station, and preventing erroneous data or data to the next station. To provide a highly reliable and efficient data multi-stage transmission system by prohibiting the transmission of unnecessary data to prevent the accumulation and spread of errors, and especially by preventing the circulation of erroneous data packets in a loop network. purpose.

DESCRIPTION OF THE INVENTION The present invention includes a signal detection circuit that detects a tail, a tail, or a chain of a received data packet, and a control circuit that allows only the received data packet to pass based on the detection output thereof. As a result, when the data packet is passed through the data packet, only the true data or a portion including the parts before and after the true data is sent out, and it is possible to prevent sending erroneous data to the next station.

DESCRIPTION OF THE EMBODIMENTS An embodiment of the present invention is shown in FIGS. 3 to 7. First, since this data bus control method does not depend on the type of infrastructure, a loop-like network will be explained in detail. In Figure 3, 8 to 11 digit terminals, 12 to 15 digit terminals,
1 is a transmission line, and 16 to 19 are stations that interface the network and the terminal, and each station is connected in a loop via the transmission line. In this embodiment, a case will be described in which a token method is adopted as an access control method for NSOTOWORK, but the same applies to other access methods. In this token system, each station circulates a token consisting of a specific bit sequence as shown in FIG. 4 through the network when there is no need for data transfer.

A station with a request to transmit obtains the right to transmit by capturing a token that circulates around the loop, and transmits the data to the second station.
As shown in Figure 1, the data is sent as a data bucket with a destination address and a source address added to it and bound by a chain. When this data packet goes around the router and returns to the transmitting station, the token is sent to the lower station, giving up the right to transmit, thereby enabling data exchange between the stations.

FIG. 5 is a block diagram when the data bus control circuit of the present invention is applied to a token-based loop-free office station, and corresponds to the shift register 1 in FIG. 1 of the conventional system. In FIG. 5, 20 is a shift register which inputs the received data from the upper station; 21
1'l: Monitor the output of the front E shift register 20 and expose the header, chain, and token of the data packet; DSI)T.

A decoder that outputs signals DEDT and FTDT, 22
23 is an RS flip-flop, 24 is a D flip-flop, and 25 is a memory such as a shift register or first-in-first-out, which is the output side of data to the transmission line. 26 is a counter, and CK is a tally clock input terminal. When the load terminal is at low level (zero is input and the clear terminal CL is at high level, the counter 26 is cleared. CR is a carry terminal and becomes high level when there is a carry. 27 to 31 are A two-man powered OR circuit, 32.33H a two-man powered AND circuit.The shift register 20.The decoder 21 makes the signal emission circuit A1,
The circuits other than the signal emission circuit A1 and the memory 25 are the control circuit A.
Set it to 2.

FIGS. 6 and 7 are timing diagrams of each part for explaining the data bus control function of FIG.
The figure shows a case where a header is added before a data packet due to a transmission error or the like. In these figures, fat is the output of the shift register 20, (bl is FTDT, fcl
is DSDT, (di is DEDT, tel is RS
The Q output of the Furi 1 flop 22, tfl is the Q output 1 of the RS Furi 1 flop 22. , [j+ is memory 2
5 clear input, tk+ is the data output of memory 25. First, the operation will be explained based on the timing chart shown in Figure @6. Received data from the throne station is input to a shift register 20 and its output is applied to a decoder 21. When token Z1 in Figure 4 is received, @6
As shown in Figure tbl, the pulse Nl is output to the FTDT, and the flip-flop 22 becomes high level (@6 (e
)). As a result, the load terminal of the counter 26 becomes high level and becomes ready for counting. A certain number of received black
When counting the fakes, the carry terminal CR becomes high level (
@Figure 6 (1)), this clears 22 flip-flops, furthermore, the counter 26 becomes loaded state,
Carry signal -1jcR becomes low. While the Q output of FRI TBU FRO FRI” 22 is at a high level, the AND gate 32
becomes a pass state (FIG. 6 fhl), and the output of the shift register 20 is guided to the memory 25 and output to the transmission line.

Note that the counting of the counter 26 is necessary as shown in FIG.
This is because it is assumed that the FTDT detection pulse is generated at the beginning of the token as shown in FIG. When data packet node Z2 arrives following t-kun as shown in FIG. 6 tal, a pulse N2 is output to the DSDT upon detection of its header (FIG. 6 (C)), and this causes! The llR5 flip-flop 23 is set (FIG. 6 (fl)), and the load terminal Lu of the counter 26 becomes high level, but the free
77" Since the flow-free 24 has not been set, the output of the AND 33 is at a high level and the counter 26 remains in a clear state. When a chain of data packets is detected, a pulse N3 is output to DEDT 'l'L. (No. 61'J
td+), the flip-flop 24 is cleared, the clear terminal of the counter 26 becomes low level, and when counting is started and a certain number of received clocks are counted, the carry output CR becomes high level (FIG. 6(i)). , this resets the flip-flop 23 and clears the D flip-flop 24 and counter 26. RS free,
While the Tsubufuro-Furi 23 is set, the output of the shift register 20 passes the AND gate 32 and is stored in the memory 2.
5 and output to the transmission line. The reason why the pass is prohibited after counting the counter 26 from the time of inspection of the chain is that DEDT is detected at the beginning of the chain. In this manner, the data bus control circuit allows only tokens or data packets to be sent to lower stations, and formatting of tokens or data packets caused by transmission errors is removed at each station.

Therefore, next, the effect of inputting the output of the AND gate 32 into the memory 25, temporarily accumulating the output of the shift register 2o, and outputting the output to the next station is changed to the true one due to a transmission error etc. as shown in Fig. 7. Baka... I went to the wrong place before the throat header...
・Explain using the example of when Noda was hailed. Figure 7f
As shown at, a false header X appears before the true data packet due to a transmission error or the like at the output of the shift register 20.

As shown in FIG. but when the true data packet header arrives,
A header detection pulse N2 is output as shown in FIG. 7 fCIK. Although the RS flip-flop 23 maintains a high level state (FIG. 1 (fl), I), sDT or FTD
T I/i@ The OR gate 31 shown in FIG. Since the memory 25 is cleared when the rear terminal becomes high level, the data that was input to the memory 25 (C) just before the pulse N2 of tel in FIG. 7 is cleared. The memory 25 is reset every time,
If the amount of data between the false header caused by an error and the true header is smaller than the capacity of the memory 25, the false header is erased by the clearing, and the data after the DSDT detection pulse N2 is newly stored in the memory 25. is stored and output to the next station. When a chain is detected, the same process as shown in Figure @6 is performed, and finally, as shown in Figure @7, only the true data packet V) with the false tag and the fold removed passes through the station. becomes.

Effects of the Invention As described above, the data bus control circuit of the present invention is capable of converting each station into a packet in a network where a plurality of stations are cascaded in a loop or path through a transmission path. When passing the detected data to the next station, the distance between the start and end detection points of the data is
Since c allows only a predetermined length of data to pass from the beginning of the data, the probability of sending data other than the correct packet format to the next station is extremely reduced, and Since the data immediately before 7 is cleared, even if a false header is placed at the beginning of a packet due to a transmission error, only the correct packet can be passed. In this way, we detect passing packets and sotos at each station,
Since errors are erased, it is possible to suppress the accumulation of errors when stations are multi-staged, and in particular, in loop-type network work, it is possible to minimize the number of incorrect packets and data that go around the loop many times. This has the effect of shortening the time it takes for the system to return to normal.

[Brief explanation of drawings]

Figure @1 is a station program diagram to explain the conventional data bus function in a network, and Figure @2 shows the structure of a packet passing through the network.
is normal! , (bl is the transmission format diagram when a false header occurs due to a transmission error etc. before the positive header, tcI is the transmission format diagram when the header disappears, and Figure @3 shows one embodiment of this invention. The configuration diagram of the applied /L/-7-ne software, Figure 4 shows the token bi-do pattern in the access token system of Roof'ne software, @5
The figure is the data bus control circuit diagram, @6 figure and @7 figure are @5
In the timing chart of each part of the data bus control circuit shown in the figure, figure @6 shows when a regular data packet/soto is received after a token, and figure 7 shows a timing chart when a normal data packet/soto is received before the normal data packet... due to a transmission error, etc.・This is when soda was created. 20...Shift register, 21...Decoder f, 22
゜23...RS flip-flop, 7 blocks, 24-D flip-flop, 25...memory, 26...counter, 27-31...OR gate, 32.33...
AND gate, A-signal detection circuit, A2... control circuit-2) Figure 2] 0 Figure 3 Figure 4

Claims (1)

[Claims] +11 Incoming data brushing 1. ．． A data bus control circuit comprising: a signal detection circuit that detects a header or chain of packets; and a control circuit that removes erroneous data signals based on detection by the signal detection circuit and passes positive data packets. (2) The data bus control circuit according to claim 1, wherein the incoming data packet node is temporarily stored in a memory, and the memory is reset every time the signal detection circuit detects a header.