JPS5913769B2 - channel control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a channel control device that controls a plurality of channels, and particularly to an improvement in a circuit unit that controls the priority of interrupt requests from channels.

In a channel control device that controls a plurality of channels, a system is generally adopted in which a common microprogram control section is built in for each channel, and each channel uses the microprogram control section in a time-sharing manner.

In this method, when the microprogram control section issues an instruction to start a certain channel, it temporarily suspends the service of that channel and shifts to the service of another channel. This is because the response time of the input/output device is generally long, and if the response time is waited for, the operating efficiency of the microprogram arm will be reduced. Thereafter, when a response signal comes from the input/output device, the channel notifies the microprogram control unit using interrupt means. The channel control device resumes the service of the corresponding channel by accepting the interrupt from this channel. By the way, in the past, the priority order for accepting interrupt requests from channels was generally fixed and determined in advance. Therefore, for example, when high-speed processing is required, such as command chain processing, There were problems such as exceeding the specified time. The present invention has been made to eliminate the problems of the conventional art as described above.
Provided is a channel control device that allows urgent processing to be processed quickly by making it possible to raise the priority of any interrupt request based on microprogram instructions when a microprogram control unit determines that high-speed processing is necessary. It's about doing.

Hereinafter, the contents of the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows the overall configuration of an information processing device.

In the figure, 10 is an arithmetic processing unit (CPU) and 12 is a main memory MM. Reference numeral 11 denotes a channel control device °CHC, which centrally controls the four channels CH13.

Although not shown in FIG. 1, each CH13 is connected to an input/output device 1/O via an I/O interface 14. CHCll controls each CH13 by microprogram control.
Manages commands, counts, and data addresses of CP.
Start-up processing from UIO, interrupt processing to the CPUIO,
The main controls include data transfer with MMl2 and interrupt processing from CHl3.

CHl3 controls the I/0 interface. That is, C
Hl3 performs 1/O selection sequences, tab control, high-speed data transfer, etc. without the aid of CHCll. For example, after selecting one I/O in the selection sequence,
If the status in comes from , CHl3 is CHCll
issues an interrupt, receives instructions from CHCll, and determines control of the 1/O interface accordingly. Here,
As an example of operation, let us consider a case where an I/O start command is issued from the CPUIO.

An I/O start command is issued from CPUIO and CHCll
When started, the CH number, I/O device number, C
CW channel command word) address is CPUl
It is given to CHCll from O. The CHC checks the status of CH13 and the status of the subchannel using the CH number and I/O device number. Assuming that the CH number is 3, CHCl
The state of CH determined by is a copy of the state of CH3. It is determined whether the interrupt is pending/in use. If C
If the status of H and the subchannel is 1" and the interrupt is not pending/in use, a condition code for activation is returned to the CPUIO. The activation instruction for the CPUIO's CHCll does not return this condition code. The CPUO moves on to the next process until the end of the data transfer operation is notified by means of an interrupt from CHCll.On the other hand, if the CH and subchannel status is ``0'' and indicates idle. If so, CHCl is CH
Check the status of 3. This is because asynchronous I/O interrupts etc.
This is because it may have come to CH3 via the /O interface 14. If CH3 is just requesting an interrupt from CHCll, the startup processing routine of CHCll is 1.
Becomes addictive. During the CH3 interrupt, CHCl
It is accepted and processed by l. After that, the hold is released,
Returning to the startup processing routine, CHCll again checks the CH status and subchannel status. If the status of the same subchannel has changed, the corresponding condition code is returned to the CPUIO. If there is no change, CHC
ll informs CH3 of the I/0 device number and
Instructs to start. CHCll then receives C from MMl2
Proceeding to a processing routine for fetching CW, etc., and after fetching CCW, a command is sent to CH3 to set it in a holding state. C
H3 controls the I/O startup sequence and command sending sequence, and when a status input is received from the I/O, CHC
Issue an interrupt to ll. CHCll accepts the interrupt, determines the I/O status, and returns the condition code of the I/O start instruction to the CPUIO. After that, CH3 moves to a data transfer sequence. In this way, there are five interrupt factors to the CHC: CPU1CHO to 3.

CHO has the highest priority, CHO〉CHl〉CH2〉
The order is CH3>CPU. The reason why CH has a high priority is to prevent an overrun caused by data transfer capture. By the way, from the point of view of CPU instruction processing time, CHC
It is unfavorable in terms of performance that the time from when the condition code is returned as a response is slow. Previous/
In the example of a 0 start instruction, it can be said that there are three input conflict points in order to receive control of the CHC.

The first is when the startup instruction from the CPU is accepted by the CHC.The second is when CH3 issues an interrupt immediately and the interrupt is being harvested by CH3.The third is when the status report from I/0 is received by CH3. This is the point at which the application is accepted by CHC via . In the first case, the CHC interrupt priority is CCPU>CHO>CHl>CH2>CH3,
CHC processing is started once, but there is a method that allows interrupts from CHO to 3 to steal the startup processing routine from the CPU at any time, or if a startup request from the CPU
When you have to wait for more than a certain time on HC CPU>CHO>C
A method of setting Hl>CH2>CH3 has been proposed. However, in the second and third cases, since it was not possible to raise the priority of a specific CH, there were problems such as exceeding the specified time or extremely slow response time. In the present invention, when the second or third case occurs,
The CHC microprogram gives a high priority to only the specified CH, so that a response to the CPU can be returned more quickly. FIG. 2 shows an embodiment of the present invention.
2 shows a channel interrupt priority circuit within the CHCll of FIG. 1; In FIG. 2, the numbers on the signal lines represent the number of bits. The priority level up register UPREG2l allows the microprogram to update the code of the processing request to be prioritized, and also has a valid display bit for that code, and its output is sent to the selection circuit A (SEL-A).
22 selection terminals and selection circuit B (SEL-B)
24 input data terminal A. SEL-A
22 is an interrupt signal 1NT0-1NT from each channel
3 as input, and IN corresponding to the code of UPREG2l
It selects one of TO to INT3, and its output is connected to the selection terminal of SEL-B24. The priority circuit 23 receives INTO to INT3 as input, selects and encodes one of INTO to INT3 according to a predetermined fixed priority order, and its output is SEL-
It is connected to input data terminal B of B24. SEL-
B24 is UREG2l by the signal from SEL-A22.
or the output of the priority circuit 23, and select the IN
The signal line 2 is encoded with one of l'0 to INT3.
6. When the CHCll microprogram interrupts an urgent process, it sets the code (for example, the channel number currently being processed) i to UPREG2l from the signal line 25, and at the same time sets the valid display bit. 1” and pause temporarily.

After that, NTi occurs after a certain period of time and SEL-A
22 input data terminal.

SEL-A22 is connected to signal lines 29 and 30 from UPREG2l
When receiving the code i and the valid indication bit through the signal line 30, the valid indication bit on the signal line 30 becomes "r" and becomes active, and selects the interrupt signal corresponding to the code i on the signal line 29, that is, INTi. . As a result, the signal line 28
is "1", and the SEL-B24 is informed that an interrupt corresponding to the code stored in the UPREG2l is coming.When the signal line 28 is "1", the SEL-B24 The code i of UPREG2l on 29 is selected and an interrupt is issued to the microprogram control unit through the signal line 26.

The microprogram control unit accepts the interrupt and resets the contents of UPREG2l when the desired processing is completed. - If INTi comparable to code i stored in UPREG2l has not arrived, priority circuit 23
takes the priority order of INTO to INT3 and sends the encoded output to SEL-B24. At this time SEL-
Since the output signal line 28 of A22 is "0", SEL
-B24 sends the output code of the priority circuit 23 to the signal line 26 and issues an interrupt to the microprogram module. Signal line 27 is an interrupt display line indicating that at least one interrupt request exists. Moreover, when the valid bit of UPREG2l is O, the signal line 30 becomes "0"", and SEL
-A22 is inactive and the signal line 28 becomes "0", so
In this case as well, the output of the priority circuit 23 is output to the signal line 26. As is clear from the above explanation, when the CHC is activated from the CPU, it is possible to store the identification information of the corresponding CH in the microprogram control section of the CHC. In the interrupt conflict in , since the interrupt request of the channel is accepted by the microprogram with priority, the response time from the CHC to the CPU can be made faster.

Moreover, if the identification information is not stored, the predetermined order of the priority circuits remains valid, so there is no need to change the selection order of the priority circuits one by one, and the configuration becomes complicated. There isn't. Of course, this is just an example;
It goes without saying that the present invention is also applicable to other cases of interrupt contention.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of an information processing device, and FIG. 2 is a block diagram showing an embodiment of the channel control device of the present invention, particularly an interrupt priority circuit section. DESCRIPTION OF SYMBOLS 10... Arithmetic processing unit, 11... Channel control device, 12... Main storage device, 13... Channel, 21...
...Priority up designation register, 22, 24...Selection circuit, 23...Priority circuit.

Claims (1)

[Claims] 1 In a channel control device that controls a plurality of channels, a priority circuit that accepts interrupts from the plurality of channels and selects one of them according to a predetermined order, and corresponds to an operation instruction for priority processing. A memory circuit that stores channel identification information, and if there is no interrupt from a channel that matches the channel whose identification information is stored in the memory circuit, the interrupt selected by the priority circuit is accepted as is; 1. A channel control device comprising: a selection circuit that accepts an interrupt of the channel with priority over an interrupt selected by the priority circuit when an interrupt is received from the channel.