JPS5913288A - Liquid crystal driving circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Ancient Technical Field] The present invention relates to a liquid crystal drive circuit having a charge generation circuit, and particularly to a liquid crystal drive circuit that can reduce the power consumed in the voltage generation circuit. It is.

The present invention also relates to a liquid crystal drive circuit that can reduce the power and prevent shortening of the life of the liquid crystal.

[Technical Background of the Invention] Generally, a liquid crystal driving circuit as shown in FIG. 1 is well known. Such a liquid crystal drive circuit is disclosed in Japanese Patent Publication No. 53-11171.
The 1/3 bias method, which is known in Japanese Patent Application Laid-open No. 101989/1989, is realized using a voltage generating circuit shown in Japanese Patent Application Laid-open No. 101989/1989.

The circuit shown in Figure 1 is a liquid crystal drive circuit configured with a duty ratio of 1/3, and is composed of a voltage divider circuit (1), a common drive circuit (2), and a segment drive circuit (3).
, the voltage divider circuit (1) has a voltage divider resistance ratio, ~R, between the first power supply terminal vDD and the second power supply terminal VLCD.
4 (L12=L12=L3=R4=L=100KG) are connected in series. Similarly, the first power supply terminal V
An auxiliary resistor "1" is connected between DD and the second power supply terminal VLCD.
4 (r1=r2=r3=r4=r=IOKΩ), P-channel switch transistors T1 and T2, and N-channel switch transistors T3 and T4 are alternately connected in series.Then, each node A of the series circuit
-a.

B-b and C-C are short-circuited. The above switch transistors T1 and T2. The gates of T3 and T4 are commonly connected. In addition, switch transistors T1 and T
The clock pulse φ shown in FIG. 2 is applied to the gate of No. 2. is supplied. Further, a clock pulse φ is applied to the gates of the switch transistors T3 and T4. is supplied. Further, a P-channel switch transistor T5 is connected between the first voltage supply terminal VDD and the node A, and an N-channel switch transistor T6 is connected between the second voltage supply terminal VLCD and the node C. Ru. A liquid crystal voltage polarity designation signal W is supplied to the gates of each of the switch transistors T and T6. According to these voltage dividing circuits (1)K, intermediate level voltages formed between the first voltage supply terminal VDD and the second voltage supply terminal VLCD are output to nodes A-B and C, respectively. can do. That is, when the switch transistors T5 and T6 are alternately switched by the polarity designation signal W, two voltage levels are outputted to each node A-I3-C as shown in the following table.

Table T4 was formed to speed up the voltage charging to each node A-B-C, and clock pulse φ. + By supplying FC, the switch transistors T1 to T4 are turned on simultaneously, and the resistance components R1, '11R2, and T2. R3 and '3
* By connecting R4 and T4 in parallel, the 0 common drive circuit (2), which is designed to reduce each resistance component, is formed by the voltage dividing circuit (1).
” B (D voltage (ivDD, 1vDD) and $1-second
The power supply voltages VDD and VLCD are connected to the liquid crystal voltage polarity designation signal W and common output control signal '1+d2yd shown in Fig. 2.
3+ and a blanking signal 1 (not shown), and as shown in FIG. 5, a four-level common drive signal C0M1. C0M2. C0M3
It forms the

The first common drive circuit Cυ has a P-channel type switch transistor T7/Tg and an N-channel type switch transistor T9/'I'io connected in series between a first power supply terminal VDD and a second power supply terminal VLCD. , the gate electrodes of switch transistors T7 and TIO are commonly connected. In addition, the switch transistor T8 J
N-channel switch transistors To, P are connected between the common connection point 01 of T9 and the 7-de B of the voltage divider circuit (1).
Channel switch transistor T1□.

CMO8 transmission gate TG consisting of inverter 11
is connected. Further, the gate of the switch transistor T8 and the gate of the switch transistor 3 are connected via an inverter I2, and the gate of the switch transistor T8 and the gate of the switch transistor T9 are connected via an inverter I3. Then, a liquid crystal voltage polarity designation signal W is supplied to the gates of the switch transistors T7 and TIO via the inverter I4, and the CMO
8 transmission game) TG has control signal 81 common control signal d
1. The blanking signal BLK is supplied via the NAND circuit N1. Although this explanation has been given for the first common drive circuit C11), these configurations are similar to the second common drive circuit C11) except that the switch transistors T7 and TIO are common.
．． The third common drive circuit (0 or more, which is the same for all 23+21, these common drive circuits eυ~ (according to 23, outputs four-level common drive output signals COMI~C0M3 to the common output pads P1~P3) I can do it.

The segment drive circuit (3) selects the voltage level of nodes A-C possessed by the voltage dividing circuit (1) using a P-channel switch transistor T13 and an N-channel switch transistor T14, and outputs the selected signal to the segment output pad P4. ~ Po.

The segment drive circuit Gυ of t, jc l has a P-channel switch transistor T between node A and node C
, 3, 'NN channel switch transistors T15 are connected in series, and the gates of switch transistors TI3 and T14 are connected in common. Further, the common connection point 04 of each switch transistor is connected to the segment output pad P4. Also,
A latch circuit (4) is connected to the gates of the switch transistors T13 and 'r14.

A segment data register (5) is also connected to the latch circuit (4). Note that the circuit configuration of these first segment drive circuits 0υ is different from that of other segment drive circuits Oa.
~(3n) are constructed in the same manner.

According to these segment drive circuits (3), the voltage level of the nodes A to C is selected by the segment data, and the segment drive signal of the four-level level is applied to the segment output pads P4 to Pn as shown in FIG. 8EGQ
-8FfG2 can be output.

According to these liquid crystal drive circuits, as shown in FIG.
= "l', an output waveform as shown in COMI K is output to output pad P1, and when common data d1 (not shown) is d, == l t @, VDD level and VLCD level are output. Then, at this time,
For example, if the first segment (not shown) is selected and the segment signal 8FfG is output at the vDI) level and vLcD level as shown in the diagram, the liquid crystal displays
As shown by the C0M1-8EIGl waveform, when a voltage higher than the threshold voltage is applied, the liquid crystal (selected segment) becomes cloudy.

On the other hand, the blank signal i (not shown) is BLK.
= “O”, output P1 has VDD level, VLC
Since the D level is not output and is always at the intermediate level,
The LCD does not become cloudy even when a segment is selected. (For example, the state of the C0M2-8FI02 waveform shown in FIG. 5.) [Problems with the background technology] By the way, in these liquid crystal drive circuits, it is necessary to consider reducing power consumption of the liquid crystal drive circuit as shown in FIG. CM08
When used in a 1-chip microcomputer, the circuit operates even while the display is turned off by the blank signal 13LKK, so most of the power is spent in those liquid crystal drive circuits, and the computer
The drawback was that the characteristics of MO8 could not be fully utilized.

That is, the liquid crystal drive circuit has a first power supply terminal, a terminal VDD.
Since there is a series circuit of resistors KR1 to R4 between the terminal and the second power supply terminal VLC0, a current path is formed, and the power generated by them is wasted even if the display is stopped. Ta. Furthermore, when the switch transistors T1 to T4 are turned on, the combined resistance of these currents becomes even smaller, and the current reaches, for example, 100n amperes, resulting in a large amount of power consumption.

Therefore, in order to reduce the power consumption, the inventors developed a fourth
As shown in the figure, a power off circuit (6) is interposed between the first power supply terminal VDD and the second power supply terminal VLCD, and the voltage supply to the drive circuit is stopped for the time when the display device is turned off. proposed a method. Those are patent applications from 1984-164.
No. 702 has been filed. These power power-off circuits are specifically N-channel switch transistor T1
5 is connected in series to the above-mentioned series resistor on the second power supply terminal side.

According to these power power-off circuits (6), when the switch transistor T15 is turned off by the LCD stop signal DCNT, the current path is cut off, and the intermediate No voltage appears and all are at the VDD level. Therefore, these divided voltages are supplied to the common drive circuit (2) and the segment drive circuit (
3), since only the VDD level is supplied to common output pads P, ~P3, and segment output pads P4 to Pn.
As shown in FIG. 5, all K outputs are at the VDD level. Therefore, no bias voltage is supplied to the liquid crystal, and the threshold value becomes zero, so the liquid crystal does not turn on. In this way, according to the liquid crystal drive circuit shown in FIG. 4, when the display device is stopped, the drive circuit stops its operation, so power is not consumed.

However, in the drive circuits shown in Figure 4, the operation of the voltage divider circuit (1) is stopped, so although it was fully operating when voltage was being supplied, the voltage supply stopped. As a result, a transistor/TIO# T14 whose operation is incomplete has been formed.As a result, there is a drawback that a DC level ΔV is output to the common output terminals S1 to P3 and segment output terminals P4 to P0. there were.

That is, in the circuit shown in FIG.
is applied, and the respective button switching operations are performed alternately.
The transmission gate TG and the switch transistors T8 and T are alternately operated by the output Sl of the Nantes gate N1. However, when W=111 and switch transistor T7 is on and TIO is off,
Then, the transmission gate TG is turned off, and the switch transistor T
8・When T9 turns on (d 1== @ Q
# , d 2 == l 1 @ , d 3 == l l
#), when the power of the dividing circuit ゛(■) is turned off by the power-off circuit (6), the source S and gate G of the switch transistor T are both applied with the KvI)I) level, so that the switch transistor T9 is not completely conductive, and the voltage level of common output terminal P1 is as shown in Figure 5C.
OM 1 waveform <Unable to reach vDD level, Δ
V becomes lower.

Therefore, the terminal P, (SEG, ), ! whose segment output has risen to the VDD level. : A voltage difference ΔV occurs as shown in the waveform of COMl-SEG in Figure 5,
A state was formed in which a DC bias was applied to the liquid crystal. Therefore, in these circuits, the DC
The disadvantage is that the lifespan of the liquid crystal is shortened because a bias is applied. These drawbacks are problems that occur in C0M1, but at this time C0M2, C0M
Which terminal P1.3 is the terminal P1. In P2, the transmission gate TG is d 2 == l 1m , d 3 == e 1 #
Therefore, the voltage VDD of node B is output.

Therefore, such a problem has not occurred.

The above problem may occur on the segment terminal side. This means that the gate G and source S voltages 1E of the switch transistor T14 are both Vl)D due to the data signal.
10 cases. In this case as well, as shown in Figure 5 (
Here, the case is shown that occurs in 8gG3. ), a potential difference of ΔV occurs at the output terminal P4, so this potential difference ΔV, together with the normal common voltage waveform, causes a DC voltage to be applied to the liquid crystal. Even so, the lifespan of the LCD was shortened.

These DC bias application force states are shown in Figure 5 C0M2-
As shown in the 5E02 waveform, this occurs even when the light is not lit (warning).

(Object of the Invention) The present invention relates to a liquid crystal drive circuit devised in view of the above drawback Kfi, and its purpose is to reduce the power generated when stopping display, and to extend the life of the liquid crystal display device. An object of the present invention is to provide a liquid crystal driving circuit that can prevent shortening.

[Summary of the Invention] According to the present invention, its features include connecting a power-off circuit to a voltage divider circuit.

When these power-off circuits are operated, the common electrode and segment electrode of the liquid crystal display device are simultaneously applied with the same voltage and pressure is forced to the stagnation level, but the details of these circuits are clear from Figure 6. 0 [Embodiment of the Invention] According to FIG. 6, a first embodiment of the present invention is shown. In Fig. 6, parts that are the same as those in Fig. 1 are given the same reference numerals, and their explanations are omitted.
When the power is turned off, the outputs P1 to P3 of the common drive circuit (2) and the output P of the segment drive circuit (3)
The first voltage level setting means (8) for forcibly setting S~Pn to one level (vDD level) is provided. (7) is formed by two human-powered NOR gates N4, the liquid crystal voltage polarity designation signal W is supplied as the first input signal, and the LCD stop signal DCNT is supplied as the second human-powered signal.
is supplied. The output of these NOR gates N4 is supplied to the gates of the switch transistors T7 and TIO. The purpose is to forcibly turn on the switch transistor T7 when the

In other words, if you do this, the common, drive circuit (2)
Even if all the voltages supplied to VDD become VDD, the switch transistor T7 is turned on by the NOR circuit N4, so the switch transistor T7 is connected to the output terminal P1.
・VDD level is supplied via T8, DC level △
■ will no longer be output. Therefore, these circuits prevent the common output terminal from outputting a waveform that causes deterioration of the liquid crystal.

The second voltage level setting means (8) is formed by a two-person gate N5. These two are so cute.

The signal applied to the first input terminal of is the segment data, and the signal applied to the second input terminal is the LCD stop signal DCNT. has been done.

The functions of the second voltage level setting means (8) are as follows:
When the voltage divider circuit (1) is stopped, the switch transistor T13 is forcibly turned on.

That is, by doing this, the segment drive circuit (3
) even if all the voltages supplied to VDD are turned on by the NOR gate N5, the switch transistor T13 is turned on by the NOR gate N5.
The VDD level is supplied through 13, and the DC level ΔV
will no longer be output. Therefore, according to these circuits, waveforms that cause deterioration of the liquid crystal are not outputted from the segment output terminals. By using the first and second voltage level setting means (7) and (8) simultaneously with the cutoff,
Common output terminal P, %P3, segment output terminal P4~
Since the Pn signal can be outputted at the same level as the bell signal (vDD level), no DC bias is applied to the liquid crystal. Therefore, according to these circuits, the life of the liquid crystal will not be shortened.In the present invention, circuit changes are possible within the scope of not altering the technical idea. For example, the form of the power off circuit (6) attached to the voltage dividing circuit (1) is as follows:
The structure may be such that an N-channel switch transistor T16 and a P-channel switch transistor T17 are connected in series between the first power supply terminal VDD and the second power supply terminals vt, co, or a common gate and common drain structure may be used. Further, as shown in FIG. 8, the switch transistor T15 shown in FIG. 6 may be replaced by a P-channel type switch transistor T'ss.

[Effects of the Invention] As described above, according to the present invention, in the liquid crystal drive circuit, when the voltage supply to the voltage dividing circuit is stopped, the D
By providing the first and second voltage level setting means for the C bias supply, it is possible to set the voltage levels of the common output terminal and the segment output terminal to the same level (VDD level), and to supply 1' to the liquid crystal. ) There is no need to apply C bias. Therefore, according to the present invention, shortening of the life of the liquid crystal can be prevented.

4. Brief explanation of the drawings □ Fig. 1 is a conventional liquid crystal drive circuit diagram, Fig. 2 is a clock waveform diagram applied to each terminal in Fig. 1, and Fig. 3 is a diagram of voltage application form to a microcomputer. , FIG. 4 is a liquid crystal drive circuit diagram on the way to the present invention, FIG. 5 is a waveform diagram appearing at each electrode terminal in FIG. 4, FIG. 6 is a circuit diagram of a first embodiment of the present invention, and FIG. The figure is a voltage division circuit diagram that is a partial modification of FIG. 6, and FIG. 8 is a voltage division circuit diagram that is a partial modification of FIG.

l... Voltage division circuit, 2... Common drive circuit, 3...
...Segment drive circuit, 4...Latch circuit, 5...
- Segment data register, 6... Power off circuit, 7... First voltage level setting means, 8... 1g2 voltage level setting means, φ. ...Clock pulse, W...Liquid crystal voltage polarity designation signal.

dl, d2, d3...Common data signals.

DLK...blanking signal, 1) CN T...LCD stop signal.

(7317) Agent Patent Attorney Noriyuki Chika (and 1 other person)

Claims (1)

[Claims] A power source for supplying voltage, a plurality of resistor means for dividing the voltage into multi-value levels, a switch means for short-circuiting the resistor means and taking out the multi-value levels, and a common connection for the multi-value levels by the resistor means. a common drive circuit for supplying to the output terminal, a segment drive circuit for supplying the multi-value level from the resistor means to the segment output terminal, a power-off means connected in series to the plurality of resistor means, and the common drive circuit. a first voltage level setting means for forcibly setting the output level of the segment drive circuit to one level; and a second voltage level setting means to set the output level of the segment drive circuit to one level, similar to the output level of the common drive circuit. When the liquid crystal is not displayed, the power off means is used to stop the power supply to the resistor means, and also to stop the power supply to the resistor means when the liquid crystal is not displayed. A liquid crystal drive circuit characterized in that the voltage levels of the common output terminal and the segment output terminal are set to the same level by operating the voltage level setting means.